MC100LVEL34DT

3.3 V ECL ÷2, ÷4, ÷8 Clock Generation Chip MC100LVEL34 Description The MC100LVEL34 is a low skew ÷ 2, ÷ 4, ÷ 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start−up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEL34s in a system. Features • • • • • • 50 ps Typical Output-to-Output Skew www.onsemi.com MARKING DIAGRAMS* 16 16 1 SOIC−16 D SUFFIX CASE 751B 100LVEL34G AWLYWW 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F 100 VL34 ALYW G G 1 A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Synchronous Enable/Disable Master Reset for Synchronization 1.5 GHz Toggle Frequency ORDERING INFORMATION The 100 Series Contains Temperature Compensation. See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V • Open Input Default State • LVDS Input Compatible • These Devices are Pb-Free, Halogen Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 March, 2021 − Rev. 5 1 Publication Order Number: MC100LVEL34/D MC100LVEL34 Table 1. PIN DESCRIPTION Q0 1 Q Q0 VCC 15 EN ÷2 2 R VCC 16 Q D 3 14 NC 13 CLK R Q1 4 Q Q1 ÷4 5 12 CLK Q2 6 7 11 VBB CLK*, CLK** ECL Diff Clock Inputs EN* ECL Sync Enable MR* ECL Master Reset Q0, Q0 ECL Diff ÷2 Outputs Q1, Q1 ECL Diff ÷4 Outputs Q2, Q2 ECL Diff ÷8 Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect 10 MR Table 2. FUNCTION TABLE Q Q2 FUNCTION * Pins will default LOW when left open. ***Pins will default to VCC/2 when left open. R VCC PIN ÷8 8 9 VEE R CLK EN MR FUNCTION Z ZZ X L H X L L H Divide Hold Q0−3 Reset Q0−3 Z = Low-to-High Transition ZZ = High-to-Low Transition Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 16−Lead Pinout (Top View) and Logic Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb−Free Pkg SOIC−16 TSSOP−16 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 210 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC100LVEL34 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−16 SOIC−16 100 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−16 33 to 36 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−16 TSSOP−16 138 108 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−16 33 to 36 °C/W Tsol Wave Solder 265 °C VI v VCC VI w VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. 100LVEL DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 2)) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 40 50 60 40 50 60 42 52 62 mA VOH Output HIGH Voltage (Note 3) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 3) 1305 1570 1725 1305 1570 1725 1305 1570 1725 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1305 1675 1305 1675 1305 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV 3.3 1.2 3.3 1.2 3.3 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) IIH Input HIGH Current IIL Input LOW Current D D 1875 1.2 150 0.5 −150 1875 150 0.5 −150 0.5 −150 1875 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 3. All loading with 50 W to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 3 MC100LVEL34 Table 6. 100LVEL DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = −3.8 V to −3.0 V (Note 5)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 23 30 40 23 30 40 23 30 40 mA IEE Power Supply Current IEE Power Supply Current 40 50 60 40 50 60 42 52 62 mA VOH Output HIGH Voltage (Note 6) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 6) −1995 −1700 −1575 −1995 −1700 −1575 −1995 −1700 −1575 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV VBB Output Voltage Reference −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current D D −1425 VEE + 1.2 0.0 −1425 VEE + 1.2 150 0.5 −150 0.0 −1425 VEE + 1.2 150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 W to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 8) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max 1.5 Min Typ Max fmax Maximum Toggle Frequency (Figure 4) 1.5 tPLH tPHL Propagation Delay to Output CLK to Q0, Q1, Q2 MR to Q 550 500 tJITTER Cycle−to−Cycle Jitter (Figure 4)