MC100LVEL40DW

MC100LVEL40 3.3/5V
ECL Differential Phase−Frequency Detector The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V power supply. When the reference (R) and the feedback (FB) inputs are unequal in frequency and/or phase the differential up (U) and down (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. For application information, refer to AND8040/D, “Phase Lock Loop Operation.” The 100 Series Contains Temperature Compensation http://onsemi.com MARKING DIAGRAM 20 100LVEL40 AWLYYWW 20 1 1 SO−20 DW SUFFIX CASE 751D A WL YY WW • 250 MHz Typical Bandwidth • ESD Protection: >2 kV HBM • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • • • Moisture Sensitivity Level 1 • • = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC100LVEL40DW SO−20 38 Units/Rail MC100LVEL40DWR2 SO−20 1000 Tape &Reel For Additional Information, refer to Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 356 devices  Semiconductor Components Industries, LLC, 2002 October, 2002 − Rev. 6 229 Publication Order Number: MC100LVEL40/D MC100LVEL40 NC VCCO U U VEE D D 20 17 16 15 14 19 18 VCCO NC NC 12 11 13 1 2 3 4 5 6 7 8 9 10 NC NC R R VBB FB FB VCC NC NC PIN DESCRIPTION PIN FUNCTION U, U D, D FB, FB R, R VBB VCC, VCCO VEE NC ECL Up Differential Outputs ECL Down Differential Outputs ECL Feedback Differential Inputs ECL Reference Differential Inputs Reference Voltage Output Positive Supply Negative Supply No Connect Figure 1. 20−Lead Pinout (Top View) Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. R S R U Q U R VBB VEE D D R FB S FB Q Figure 2. Logic Diagram MAXIMUM RATINGS (Note 1) Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 20 SOIC 20 SOIC 90 60 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 20 SOIC 30 to 35 °C/W Tsol Wave Solder