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MC100LVEP111
2.5V / 3.3V 2:1:10
Differential ECL/PECL/HSTL
Clock Driver
Description
The MC100LVEP111 is a low skew 2:1:10 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single−ended (if the VBB output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50 W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single−ended CLK input operation is limited to a VCC ≥
3.0 V in PECL mode, or VEE v −3.0 V in NECL mode when using VBB
(See Figure 11). Full operating range is available when using an external
voltage reference (See Figure 10). Designers can take advantage of the
LVEP111’s performance to distribute low skew clocks across the
backplane or the board.
Features
•
•
•
•
•
•
•
•
•
85 ps Typical Device−to−Device Skew
20 ps Typical Output−to−Output Skew
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MARKING
DIAGRAMS*
MC100
LVEP111
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
32
1
1
1
32
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G or G
MC100
LVEP111
AWLYYWW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Jitter Less than 1 ps RMS
Additive RMS Phase Jitter: 60 fs @ 156.25 MHz, Typ.
Maximum Frequency > 3 GHz Typical
ORDERING INFORMATION
VBB Output
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
430 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.8 V
Open Input Default State
•
• LVDS Input Compatible
• Fully Compatible with MC100EP111
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 23
1
Publication Order Number:
MC100LVEP111/D
MC100LVEP111
Q3
24
Q3
23
Q4
22
Q4
21
Q5
20
Q5
Q6
19
18
Table 1. PIN DESCRIPTION
Q6
17
PIN
FUNCTION
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
VCC
25
16
VCC
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q2
26
15
Q7
Q0:9, Q0:9
ECL/PECL Outputs
Q2
27
14
Q7
CLK_SEL*
ECL/PECL Active Clock Select Input
28
13
Q8
VBB
Reference Voltage Output
Q1
VCC
Positive Supply
Q1
29
12
Q8
VEE
Negative Supply
Q0
30
11
Q9
EP
The exposed pad (EP) on the package
Q0
31
10
Q9
VCC
32
9
VCC
MC100LVEP111
1
2
3
4
5
6
7
bottom must be attached to a heat−sinking conduit. The exposed pad may only
be electrically connected to VEE.
8
CLK1
VBB
CLK1
CLK0
CLK0
VCC
CLK_SEL
* Pins will default LOW when left open.
** Pins will default to 2/3VCC when left open.
VEE
Table 2. FUNCTION TABLE
CLK_SEL
Active Input
L
H
CLK0, CLK0
CLK1, CLK1
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. LQFP−32 Pinout (Top View)
VCC
Q0
Q0
Q1
Q1
Q2
Q2 VCC
32
31
30
29
28
27
26
25
1
24 Q3
CLK_SEL
2
23 Q3
CLK0
3
22 Q4
CLK0
4
VCC
21 Q4
MC100LVEP111
5
20 Q5
CLK1
6
19 Q5
CLK1
7
18 Q6
8
17 Q6
VBB
VEE
9
10
11
12
13
14
15
16
VCC Q9
Q9
Q8
Q8
Q7
Q7
VCC
Exposed Pad (EP)
Figure 2. QFN−32 Pinout (Top View)
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2
MC100LVEP111
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
LQFP
QFN
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 100 V
> 2 kV
Pb Pkgs
Pb−Free Pkgs
Level 2
Level 1
Level 2
Level 1
UL 94 V−0 @ 0.125 in
602 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
CLK0
Q4
0
Q4
CLK0
Q5
CLK1
Q5
1
Q6
CLK1
VBB
CLK_SEL
VEE
Q6
Q7
Q7
Q8
VCC
Q8
Q9
Q9
Figure 3. Logic Diagram
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3
MC100LVEP111
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
LQFP−32
12 to 17
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
Tsol
Wave Solder
< 3 sec @ 248°C
< 3 sec @ 260°C
265
265
°C
Pb
Pb−Free (QFN−32 Only)
Condition 1
Condition 2
VI ≤ VCC
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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4
MC100LVEP111
Table 5. PECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
90
120
60
90
120
60
90
120
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 3)
505
730
900
505
730
900
505
730
900
mV
VIH
Input HIGH Voltage (Single−Ended)
(Note 4)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 4)
505
875
505
875
505
875
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 5)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
CLK
CLK
150
0.5
−150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to −1.3 V.
3. All loading with 50 W to VEE.
4. Do not use VBB at VCC < 3.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. PECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 6)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
90
120
60
90
120
60
90
120
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 7)
1305
1530
1700
1305
1530
1700
1305
1530
1700
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1305
1675
1305
1675
1305
1675
mV
VBB
Output Reference Voltage (Note 8)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1875
1875
150
CLK
CLK
1875
150
0.5
−150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to −0.5 V.
7. All loading with 50 W to VCC − 2.0 V.
8. Single ended input operation is limited VCC ≥ 3.0 V in PECL mode.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
90
120
60
90
120
60
90
120
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 11)
−1995
−1770
−1600
−1995
−1770
−1600
−1995
−1770
−1600
mV
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5
MC100LVEP111
Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10)
−40°C
Symbol
Characteristic
Min
VIH
Input HIGH Voltage (Single−Ended)
VIL
25°C
Typ
Max
Min
−1165
−880
Input LOW Voltage (Single−Ended)
−1995
VBB
Output Reference Voltage (Note 12)
−1525
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IIH
Input HIGH Current
IIL
Input LOW Current
−1425
Max
Min
−1165
−880
−1625
−1995
−1325
−1525
VEE + 1.2
0.0
Typ
−1425
VEE + 1.2
150
CLK
CLK
85°C
0.5
−150
Max
Unit
−1165
−880
mV
−1625
−1995
−1625
mV
−1325
−1525
−1325
mV
0.0
V
150
mA
0.0
Typ
−1425
VEE + 1.2
150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
10. Input and output parameters vary 1:1 with VCC.
11. All loading with 50 W to VCC − 2.0 V.
12. Single ended input operation is limited VEE ≤ −3.0V in NECL mode.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. HSTL DC CHARACTERISTICS VCC = 2.375 to 3.8 V, VEE = 0 V
−40°C
Symbol
Characteristic
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Vx
Input Crossover Voltage
680
ICC
Power Supply Current
70
Typ
25°C
Max
1200
Min
Typ
85°C
Max
1200
Typ
680
120
70
100
900
680
120
70
Unit
mV
400
900
Max
1200
400
100
Min
100
400
mV
900
mV
120
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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6
MC100LVEP111
Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 to −3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 14)
−40°C
Characteristic
Symbol
Min
fmaxPECL/HSTL
Maximum Frequency (Figure 4)
tPLH
tPHL
Propagation Delay
(Differential Configuration)
tskew
Within−Device Skew (Note 15)
Within−Device Skew @ 2.5 V (Note 15)
Device−to−Device Skew (Note 16)
tJITTER
CLOCK Random Jitter (RMS)
@ v0.5 GHz
@ v1.0 GHz
@ v1.5 GHz
@ v2.0 GHz
@ v2.5 GHz
@ v3.0 GHz
Typ
25°C
Max
Min
3
325
Typ
85°C
Max
Min
3
400
475
20
20
85
0.209
0.200
0.197
0.220
0.232
0.348
350
Typ
Max
3
430
500
25
25
150
20
20
85
0.5
0.5
0.4
0.5
0.4
0.6
0.204
0.214
0.213
0.224
0.290
0.545
375
Unit
GHz
510
590
ps
25
25
150
25
20
85
35
25
150
ps
0.5
0.6
0.5
0.5
0.5
0.8
0.221
0.229
0.243
0.292
0.522
0.911
0.5
0.5
0.4
0.6
0.8
1.3
ps
tjit(f)
Additive RMS Phase Jitter
fc = 156.25 MHz, Integration Range:
12 kHz to 20 MHz (See Figure 5)
60
fs
VPP
Input Swing (Differential Interconnect
Configuration) Measured Single−Ended
150
800
1200
150
800
1200
150
800
1200
mV
tr/tf
Output Rise/Fall Time (20%−80%)
105
200
255
125
200
275
150
230
320
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14. Measured with 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
15. Skew is measured between outputs under identical transitions and conditions on any one device.
16. Device−to−Device skew for identical transitions at identical VCC levels.
800
VOUTpp (mV)
700
600
500
400
300
200
100
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 4. Fmax Typical
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7
5000
6000
MC100LVEP111
Figure 5. Typical MC100LVEP111 Phase Noise Plot at fCarrier = 156.25 MHz, VCC = 3.3 V, 255C
notably lower than that of the DUT. If the phase noise of the
source is greater than the noise floor of the device under test,
the source noise will dominate the additive phase jitter
calculation and lead to an incorrect negative result for the
additive phase noise within the integration range. The
Figure above is a good example of the MC100LVEP111
source generator phase noise having a significantly lower
floor than the DUT and results in an additive phase jitter of
53 fs.
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 53 fs. The additive RMS phase jitter
performance of the fanout buffer is highly dependent on the
phase noise of the input source.
To obtain the most precise additive phase noise
measurement, it is vital that the source phase noise be
Additive RMS phase jitter = √RMS phase jitter of output2 − RMS phase jitter of input2
53 fs + Ǹ138.18 fs2 * 127.59 fs2
Figure 5 was created with measured data from
Agilent−E5052B Signal Source Analyzer using ON
Semiconductor Phase Noise Explorer web tool. This free
application enables an interactive environment for advanced
phase noise and jitter analysis of timing devices and clock
tree designs. To see the performance of MC100LVEP111
beyond conditions outlined in this datasheet, please visit the
ON Semiconductor Green Point Design Tools homepage.
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8
MC100LVEP111
VCC
VCC
Z0 = 50 W
VCC
VCC
Z0 = 50 W
MC100LVEP111
CLKx
50 W
LVPECL
Driver
LVDS
Driver
VTT
50 W
MC100LVEP111
CLKx
50 W*
100 W
50 W*
Z0 = 50 W
CLK
CLK
Z0 = 50 W
VT = VCC − 2.0 V
VEE
VEE
GND
Figure 6. LVPECL in Interface
VCC
Figure 7. LVDS in Interface
VCC
Z0 = 50 W
GND
VCC
VCC
Z0 = 50 W
MC100LVEP111
CLKx
50 W
50 W
HSTL
Driver
MC100LVEP111
CLKx
CML
Driver
VDDQ
VCC
50 W
50 W
CLK
CLK
Z0 = 50 W
VEE
Z0 = 50 W
VEE
VEE
VEE
Figure 9. Standard 50 W Load CML in Interface
Figure 8. HSTL in Interface
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9
MC100LVEP111
VCC
VCC
Z0 = 50 W
LVCMOS
LVTTL Single−Ended
Driver
MC100LVEP111
CLKx
VCC
1k
CLK
1k
VEE
VEE
Figure 10. Single−Ended Interface LVCMOS/LVTTL in Interface Using an External Voltage Reference
VCC
VCC
Z0 = 50 W
MC100LVEP111
CLKx
LVCMOS
LVTTL Single−Ended
Driver
CLK
VEE
VEE
VBB
VEE
Figure 11. Single−Ended Interface LVCMOS/LVTTL in Interface Using VBB
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10
MC100LVEP111
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Zo = 50 W
Q
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Round Sprocket Holes
Designations
Quadrant A = Upper Left
Quadrant B = Upper Right
Quadrant C = Lower Left
Quadrant D = Lower Right
Quadrant
A
Quadrant
B
User Direction
of Unreeling
Quadrant
C
Quadrant
D
Figure 13. Tape and Reel Pin 1 Quadrant Orientation
ORDERING INFORMATION
Package
Shipping†
MC100LVEP111FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100LVEP111FARG
LQFP−32
(Pb−Free)
2000 / Tape & Reel
(Pin 1 Orientation in Quadrant B, Figure 13)
M100LVEP111FATWG
LQFP−32
(Pb−Free)
2000 / Tape & Reel
(Pin 1 Orientation in Quadrant A, Figure 13)
MC100LVEP111MNG
QFN−32
(Pb−Free)
74 Units / Rail
MC100LVEP111MNRG
QFN−32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
MC100LVEP111
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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12
MC100LVEP111
PACKAGE DIMENSIONS
A
4X
A1
32
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
25
0.20 (0.008) AB T-U Z
1
−U−
AE
V
DETAIL Y
17
8
V1
BASE
METAL
AE
ÉÉ
ÉÉ
ÉÉ
N
DETAIL Y
9
−Z−
9
S1
4X
0.20 (0.008) AC T-U Z
F
S
8X
M_
J
R
D
DETAIL AD
G
SECTION AE−AE
−AB−
C E
−AC−
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
www.onsemi.com
13
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
AC T-U Z
B1
P
M
B
0.20 (0.008)
−T−
MC100LVEP111
PACKAGE DIMENSIONS
QFN32 5x5, 0.5 P
CASE 488AM
ISSUE A
PIN ONE
LOCATION
ÉÉ
ÉÉ
A
D
L
L
B
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
0.15 C
0.15 C
A
DETAIL B
0.10 C
ÉÉÉ
ÇÇÇ
ÇÇÇ
EXPOSED Cu
TOP VIEW
(A3)
A1
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
0.08 C
SEATING
PLANE
C
SIDE VIEW
NOTE 4
K
D2
5.30
17
8
32X
MILLIMETERS
MIN
MAX
1.00
0.80
−−−
0.05
0.20 REF
0.18
0.30
5.00 BSC
2.95
3.25
5.00 BSC
2.95
3.25
0.50 BSC
0.20
−−−
0.30
0.50
−−−
0.15
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
9
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
3.35
32X
0.63
L
E2
1
32
3.35 5.30
25
e
e/2
BOTTOM VIEW
32X
b
0.10
M
C A B
0.05
M
C
NOTE 3
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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