MC100LVEP16DG

2.5V/3.3V ECL Differential Receiver/Driver MC10LVEP16, MC100LVEP16 Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency and low voltage (2.5 V) sources. Single-Ended CLK input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤ −3.0 V in NECL mode. The VBB pin, an internally generated Voltage supply, is available to this device only. For Single-Ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. www.onsemi.com 8 8 1 1 SOIC−8 NB TSSOP−8 DFN8 D SUFFIX DT SUFFIX MN SUFFIX CASE 751−07 CASE 948R−02 CASE 506AA MARKING DIAGRAMS* Features 8 • 240 ps Propagation Delay • Maximum Frequency = > 4 GHz Typical • PECL Mode Operating Range: 8 8 • • Open Input Default State • LVDS Input Compatible • These Devices are Pb-Free, Halogen Free and are RoHS Compliant 1 KVP16 ALYW G 1 SOIC−8 NB KU16 ALYWG G TSSOP−8 4L MG G • 1 VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V VBB Output HU16 ALYWG G 1 4 DFN8 H = MC10 L = Wafer Lot K = MC100 Y = Year 4L = MC100 W = Work Week M = Date Code G = Pb-Free Package A = Assembly Location (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2016 April, 2021 − Rev. 13 1 Publication Order Number: MC10LVEP16/D MC10LVEP16, MC100LVEP16 Table 1. PIN DESCRIPTION NC D D VBB 1 2 3 4 8 7 6 5 VCC Pin Q Q VEE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Function D*, D** ECL Data Inputs Q, Q ECL Data Outputs VBB Ref. Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. * Pins will default LOW when left open. **Pins will default to VCC/2 when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8 NB TSSOP−8 DFN8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC10LVEP16, MC100LVEP16 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8 NB SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W qJC Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). Table 4. 10EP DC CHARACTERISTICS, PECL (VCC = 2.5 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 22 27 17 22 27 17 22 28 mA Output HIGH Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV Output LOW Voltage (Note 2) 565 740 865 630 805 930 690 865 990 mV Input HIGH Voltage Common Mode Range (Differential Configuration) (Notes 3, 4) 1.2 2.5 1.2 2.5 1.2 2.5 V 150 mA IEE Power Supply Current VOH VOL VIHCMR 25°C IIH Input HIGH Current IIL Input LOW Current D D 150 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. 2. All loading with 50ĂW to VCC − 2.0 V. 3. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC ≥ 3.0 V in PECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 3 MC10LVEP16, MC100LVEP16 Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 22 27 17 22 27 17 22 28 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 2) 1365 1540 1665 1430 1605 1730 1490 1665 1790 mV VIH Input HIGH Voltage (Single Ended) 2090 2415 2155 2480 2215 2540 mV 1690 1430 1755 1490 1815 mV 1990 1855 2055 1915 2115 mV 3.3 1.2 3.3 1.2 3.3 V 150 mA VIL Input LOW Voltage (Single Ended) 1365 VBB Output Voltage Reference (Note 3) 1790 VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 1.2 IIH Input HIGH Current IIL Input LOW Current D D 1890 1955 150 2015 150 0.5 −150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 2. All loading with 50 W to VCC − 2.0 V. 3. Single ended input CLK pin operation is limited to VCC ≥ 3.0 V in PECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. 10EP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = −3.8 V to −2.375 V (Note 1)) −40°C Symbol IEE Characteristic Power Supply Current 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 17 22 27 17 22 27 17 22 28 mA VOH Output HIGH Voltage (Note 2) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 2) −1935 −1760 −1635 −1870 −1695 −1570 −1810 −1635 −1510 mV VIH Input HIGH Voltage (Single Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VBB Output Voltage Reference (Note 3) −1510 −1310 −1445 −1245 −1385 −1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 0.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current D D −1410 VEE+1.2 0.0 VEE+1.2 150 0.0 −1285 VEE+1.2 150 0.5 −150 0.5 −150 −1345 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50ĂW to VCC − 2.0 V. 3. Single ended input CLK pin operation is limited to VEE ≤ −3.0 V in NECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 4 MC10LVEP16, MC100LVEP16 Table 7. 100EP DC CHARACTERISTICS, PECL (VCC = 2.5 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 19 24 29 22 28 34 24 30 36 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 2) 555 730 900 555 730 900 555 730 900 mV Input HIGH Voltage Common Mode Range (Differential Configuration) (Notes 3, 4) 1.2 3.3 1.2 3.3 1.2 3.3 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current D D 150 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. 2. All loading with 50 W to VCC − 2.0 V. 3. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC ≥ 3.0 V in PECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. 100EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 19 24 29 22 28 34 24 30 36 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 2) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV VIH Input HIGH Voltage (Single Ended) 2135 2420 2135 2420 2135 2420 mV 1700 1355 1700 1355 1700 mV 1975 1775 1975 1775 1975 mV 3.3 1.2 3.3 1.2 3.3 V 150 mA VIL Input LOW Voltage (Single Ended) 1355 VBB Output Voltage Reference (Note 3) 1775 VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 1.2 IIH Input HIGH Current IIL Input LOW Current D D 1875 150 0.5 −150 1875 150 0.5 −150 0.5 −150 1875 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 2. All loading with 50ĂW to VCC − 2.0 V. 3. Single ended input CLK pin operation is limited to VCC ≥ 3.0 V in PECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 5 MC10LVEP16, MC100LVEP16 Table 9. 100EP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = −3.8 V to −2.375 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 19 24 29 22 28 34 24 30 36 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 2) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV VIH Input HIGH Voltage (Single Ended) −1165 −880 −1165 −880 −1165 −880 mV −1600 −1945 −1600 −1945 −1600 mV −1325 −1525 −1325 −1525 −1325 mV 0.0 V 150 mA VIL Input LOW Voltage (Single Ended) −1945 VBB Output Voltage Reference (Note 3) −1525 VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) IIH Input HIGH Current IIL Input LOW Current D D −1425 VEE+1.2 0.0 −1425 VEE+1.2 0.0 150 0.5 −150 −1425 VEE+1.2 150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC − 2.0 V. 3. Single ended input CLK pin operation is limited to VEE ≤ −3.0 V in NECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 10. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.8 V to −2.375 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 1)) −40°C Symbol fmax Maximum Frequency (See Figure 2. Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 2) tJITTER CLOCK Random Jitter (RMS) @ ≤ 1.0 GHz @ ≤ 1.5 GHz @ ≤ 2.0 GHz @ ≤ 2.5 GHz @ ≤ 3.0 GHz @ ≤ 3.5 GHz VPP tr tf Min Characteristic Max Min >4 150 Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% − 80%) Typ 25°C Q, Q Typ 85°C Max Min >4 220 300 5.0 170 Typ Max >4 240 320 20 5.0 0.134 0.077 0.115 0.117 0.122 0.123 0.2 0.2 0.2 0.2 0.2 0.2 150 800 1200 70 120 170 190 Unit GHz 260 330 ps 20 5.0 20 ps 0.147 0.104 0.141 0.132 0.143 0.145 0.3 0.3 0.3 0.3 0.3 0.3 0.166 0.145 0.153 0.156 0.177 0.202 0.3 0.3 0.3 0.3 0.3 0.3 150 800 1200 150 800 1200 mV 80 130 180 100 150 200 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. www.onsemi.com 6 900 9 800 8 700 7 600 6 500 5 400 4 300 3 200 2 ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ 100 0 0 1000 2000 3000 JITTEROUT ps (RMS) VOUTpp (mV) MC10LVEP16, MC100LVEP16 1 (JITTER) 4000 5000 6000 FREQUENCY (MHz) Figure 2. Fmax/Jitter Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) ORDERING INFORMATION Package Shipping† TSSOP−8 (Pb-Free) 2500 / Tape & Reel MC100LVEP16DG SOIC−8 NB (Pb-Free) 98 Units / Tube MC100LVEP16DR2G SOIC−8 NB (Pb-Free) 2500 / Tape & Reel MC100LVEP16DTG TSSOP−8 (Pb-Free) 100 Units / Tube MC100LVEP16DTR2G TSSOP−8 (Pb-Free) 2500 / Tape & Reel MC100LVEP16MNR4G DFN8 (Pb-Free) 1000 / Tape & Reel Device MC10LVEP16DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 7 MC10LVEP16, MC100LVEP16 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA ISSUE F DATE 04 MAY 2016 1 SCALE 4:1 D PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C A B L1 ÇÇ ÇÇ ÇÇ DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉ ÇÇ ÉÉ ÇÇ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 DETAIL B 0.08 C (A3) NOTE 4 SIDE VIEW DETAIL A ALTERNATE CONSTRUCTIONS A1 C D2 8X 4 1 SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* L 5 8 e/2 e 8X 0.90 b 0.05 C 8X 0.50 2.30 1 0.10 C A B 8X 0.30 NOTE 3 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GENERIC MARKING DIAGRAM* 1 1.30 PACKAGE OUTLINE E2 K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 XXMG G XX = Specific Device Code M = Date Code G = Pb−Free Device *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON18658D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8, 2.0X2.0, 0.5MM PITCH PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2016 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP 8 CASE 948R−02 ISSUE A DATE 04/07/2000 SCALE 2:1 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF T U S V 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S 0.25 (0.010) B −U− A −V− S M M F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E DOCUMENT NUMBER: DESCRIPTION: 98AON00236D TSSOP 8 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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