MC100LVEP210FARG

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The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode. The LVEP210 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The MC100LVEP210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP210 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single−ended CLK input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤ −3.0 V in ECL mode. Designers can take advantage of the LVEP210’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. Features • • • • • • • • http://onsemi.com MARKING DIAGRAMS* MC100 LVEP21 AWLYYWWG 32−LEAD LQFP FA SUFFIX CASE 873A 1 1 32 QFN32 MN SUFFIX CASE 488AM A WL YY WW G or G MC100 LVEP210 AWLYYWWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 85 ps Typical Device−to−Device Skew 20 ps Typical Output−to−Output Skew *For additional marking information, refer to Application Note AND8002/D. VBB Output Jitter Less than 1 ps RMS ORDERING INFORMATION 350 ps Typical Propagation Delay See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Maximum Frequency u 3 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V Open Input Default State • • LVDS Input Compatible • Fully Compatible with MC100EP210 • These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2014 May, 2014 − Rev. 15 1 Publication Order Number: MC100LVEP210/D MC100LVEP210 Exposed Pad (EP) VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC 25 26 27 28 29 30 31 32 4 24 Qa3 Qa3 NC 2 23 Qa3 Qa4 CLKa 3 22 Qa4 Qa4 CLKa 4 21 Qa4 MC100LVEP210 20 19 Qb0 18 Qb1 17 Qb1 8 Qb0 7 VEE 25 1 6 CLKb 26 VCC 5 CLKb 27 Qa3 MC100LVEP210 VBB 28 21 3 CLKa 29 22 CLKa 30 23 2 NC 31 24 1 VCC 32 VBB 5 20 Qb0 CLKb 6 19 Qb0 CLKb 7 18 Qb1 VEE 16 15 14 13 12 11 9 10 17 Qb1 8 9 10 11 12 13 14 15 16 VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 2. LQFP−32 Pinout (Top View) Figure 1. 32−Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION CLKn*, CLKn** ECL/PECL/HSTL CLK Inputs Qn0:4, Qn0:4 ECL/PECL Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply EP The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to VEE. * Pins will default LOW when left open. ** Pins will default to VCC/2 when left open. Qa0 Qb0 Qa0 Qb0 Qb1 Qa1 CLKa CLKb Qa1 CLKa Qb1 CLKb Qa2 Qb2 Qb2 Qa2 Qa3 VBB Qa3 Qb3 Qb3 VCC Qa4 VEE Qa4 Figure 3. Logic Diagram http://onsemi.com 2 Qb4 Qb4 MC100LVEP210 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pull−up Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 1) LQFP−32 QFN−32 Flammability Rating Oxygen Index: 28 to 34 > 2 kV > 100 V > 2 kV Pb Pkg Pb−Free Pkg Level 2 N/A Level 2 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 461 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder