MC10EL31D

MC10EL31, MC100EL31 5 V ECL D Flip‐Flop With Set and Reset The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131, the EL31 is ideally suited for those applications which require the ultimate in AC performance. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* 8 SOIC−8 D SUFFIX CASE 751 Features • 475 ps Propagation Delay • 2.8 GHz Toggle Frequency • ESD Protection: > 1 kV Human Body Model, 1 > 100 V Machine Model • • • • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on D, CLK, S, and R Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Metastability 125 ps (see Application Note AN1504) Transistor Count = 79 devices Pb−Free Packages are Available HEL31 ALYW G TSSOP−8 DT SUFFIX CASE 948R 1 1 KEL31 ALYW G 8 HL31 ALYWG G 4T M G G • • • 1 8 8 8 • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • 8 1 4 1 KL31 ALYWG G 2I M G G 1 1 4 DFN8 MN SUFFIX CASE 506AA H K 4T 2I A = MC10 = MC100 = MC10 = MC100 = Assembly Location L Y W M G = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2008 August, 2008 − Rev. 6 1 Publication Order Number: MC10EL31/D MC10EL31, MC100EL31 Table 1. TRUTH TABLE S 1 D 2 CLK 3 8 S D VCC D S* R* CLK Q 7 Q L H X X X L L H L H L L L H H Z Z X X X L H H L Undef 6 Q Z = LOW to HIGH Transition * Pins will default low when left open. R Table 2. PIN DESCRIPTION PIN R 4 5 FUNCTION VEE Figure 1. Logic Diagram and Pinout Assignment S D R CLK Q, Q VCC VEE ECL Set Input ECL Data Input ECL Reset Input ECL Clock Input ECL Data Outputs Positive Supply Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder