MC10EL35D

MC10EL35, MC100EL35 5V ECL JK Flip‐Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* • 525 ps Propagation Delay • 2.2G Hz Toggle Frequency • ESD Protection: > 1 kV Human Body Model, • • • • 1 > 100 V Machine Model PECL Mode Operating Range: VCC = 4.2 V to 5.7 with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on J, K, CLK, and R Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL−94 V−0 @ 0.125 in, Oxygen Index 28 to 34 Transistor Count = 81 devices SOIC−8 D SUFFIX CASE 751 8 8 HEL35 ALYW G 1 8 8 1 TSSOP−8 DT SUFFIX CASE 948R KEL35 ALYW G 1 1 8 HL35 ALYWG G 4W M G G • • 8 • • Pb−Free Packages are Available 1 4 1 KL35 ALYWG G 2L M G G Features 1 4 DFN8 MN SUFFIX CASE 506AA H K 4W 2L A = MC10 = MC100 = MC10 = MC100 = Assembly Location L Y W M G = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2008 August, 2008 − Rev. 7 1 Publication Order Number: MC10EL35/D MC10EL35, MC100EL35 Table 1. PIN DESCRIPTION J K CLK 1 2 8 J 7 K 3 6 VCC PIN Q Q R R 4 5 VEE FUNCTION J ECL Input K ECL Input R ECL Reset CLK ECL Clock Input Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Figure 1. Logic Diagram and Pinout Assignment Table 1. TRUTH TABLE J* K* R* CLK Qn+1 L L H H X L H L H X L L L L H Z Z Z Z X Qn L H Qn L Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 SOIC 8 SOIC 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 TSSOP 8 TSSOP 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder