MC10EL51, MC100EL51
5V ECL Differential Clock D
Flip‐Flop
Description
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
HEL51
ALYW
G
1
1
1
•
•
•
•
•
•
•
8
HL51
ALYWG
G
4X M G
G
> 100 V Machine Model
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input Pulldown Resistors on D, R, and CLK
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 73 devices
Pb−Free Packages are Available
KEL51
ALYW
G
1
8
8
TSSOP−8
DT SUFFIX
CASE 948R
• 475 ps Propagation Delay
• 2.8 GHz Toggle Frequency
• ESD Protection: > 1 kV Human Body Model,
8
1
4
1
KL51
ALYWG
G
2M M G
G
The MC10EL/100EL51 is a differential clock D flip-flop with reset.
The device is functionally similar to the E151 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E151 the EL51 is ideally
suited for those applications which require the ultimate in AC
performance.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EL51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input (pulled down to VEE) conditions.
The 100 Series contains temperature compensation.
1
4
DFN8
MN SUFFIX
CASE 506AA
H = MC10
K = MC100
4X = MC10
2M = MC100
A = Assembly Location
L
Y
W
M
G
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 7
1
Publication Order Number:
MC10EL51/D
MC10EL51, MC100EL51
Table 1. TRUTH TABLE
R
1
D
2
CLK
3
8
VCC
7
Q
6
Q
R
D
D*
R*
CLK*
Q**
L
H
X
L
L
H
Z
Z
X
L
H
L
Z = LOW to HIGH Transition
* Pin will default low when left open.
**Pin will default low when inputs are left open.
Table 2. PIN DESCRIPTION
PIN
CLK
4
5
VEE
Figure 1. Logic Diagram and Pinout Assignment
FUNCTION
R
D
CLK, CLK
Q, Q
VCC
VEE
ECL Reset Input
ECL Data Input
ECL Clock Inputs
ECL Data Outputs
Positive Supply
Negative Supply
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 TSSOP
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
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