MC10EP139DWR2G

3.3V/5V ECL ÷2/4, ÷4/5/6 Clock Generation Chip MC10EP139, MC100EP139 Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; therefore the master reset (MR) input may require assertion to ensure system synchronization. Internal divider design ensures synchronization between the ÷2/4 and the ÷4/5/6 outputs within a device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The VBB Pin, an internally generated voltage supply, is available to this device only. For Single-Ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. Features • Maximum Frequency = > 1.0 GHz Typical • 50 ps Output-to-Output Skew • PECL Mode Operating Range: • • • • • • • VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com 1 1 SOIC−20 WB DW SUFFIX CASE 751D TSSOP−20 WB DT SUFFIX CASE 948E MARKING DIAGRAMS* 20 HEP or KEP 139 ALYWG G MCXXXEP139 AWLYYWWG 1 TSSOP−20 WB HEP KEP XXX A L,WL Y, YY W, WW G or G SOIC−20 WB = MC10EP = MC100EP = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device MC10EP139DTG MC100EP139DTG Package Shipping† TSSOP−20 WB (Pb-Free) 75 Units / Tube TSSOP−20 WB (Pb-Free) 75 Units / Tube MC100EP139DTR2G TSSOP−20 WB 2500 / (Pb-Free) Tape & Reel MC100EP139DWG TSSOP−20 WB (Pb-Free) 38 Units / Tube †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 April, 2021 − Rev. 15 1 Publication Order Number: MC10EP139/D MC10EP139, MC100EP139 VCC 1 20 VCC EN 2 19 Q0 Table 1. PIN DESCRIPTION PIN FUNCTION CLK*, CLK* ECL Differential Clock Inputs EN* ECL Sync Enable MR* ECL Master Reset VBB ECL Reference Output Q0, Q1, Q0, Q1 ECL Differential B2/4 Outputs Q2, Q3, Q2, Q3 ECL Differential B4/5/6 Outputs DIVSELa* ECL Frequency Select Input B2/4 DIVSELb0 3 18 Q0 CLK 4 17 Q1 CLK 5 16 Q1 VBB 6 15 Q2 MR 7 14 Q2 VCC 8 13 Q3 DIVSELb1 9 12 Q3 DIVSELb0* ECL Frequency Select Input B4/5/6 10 11 VEE DIVSELb1* ECL Frequency Select Input B4/5/6 VCC ECL Positive Supply VEE ECL Negative Supply DIVSELa MC10/100EP139 Warning: All VCC and VEE pins must be externally connected to a Power Supply to guarantee proper operation. Figure 1. 20-Lead Pinout (Top View) *Pins will default low when left open. DIVSELa Q0 CLK ÷2/4 CLK R Q0 Q1 Q1 Q2 EN ÷4/5/6 R Q2 Q3 MR DIVSELb0 DIVSELb1 Q3 VEE Figure 2. Logic Diagram Table 2. FUNCTION TABLES CLK EN MR Function Z ZZ X L H X L L H Divide Hold Q0:3 Reset Q0:3 Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa Q0:1 Outputs L H Divide by 2 Divide by 4 DIVSELb0 DIVSELb1 Q2:3 Outputs L H L H L L H H Divide by 4 Divide by 6 Divide by 5 Divide by 5 www.onsemi.com 2 MC10EP139, MC100EP139 CLK Q (÷2) Q (÷4) Q (÷5) Q (÷6) Figure 3. CLK and OUTPUT Timing Diagram CLK tRR RESET Q (÷n) Figure 4. Timing Diagram www.onsemi.com 3 MC10EP139, MC100EP139 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−20 WB TSSOP−20 W Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 758 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−20 WB TSSOP−20 WB 140 100 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−20 WB 23 to 41 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−20 WB SOIC−20 WB 90 60 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB 33 to 35 °C/W Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 4 MC10EP139, MC100EP139 Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 65 82 105 65 83 105 65 84 105 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single-Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single-Ended) 1365 1690 1460 1755 1490 1815 mV VBB Output Voltage Reference 1790 1990 1855 2055 1915 2115 mV 3.3 2.0 3.3 2.0 3.3 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) IIH Input HIGH Current IIL Input LOW Current 1890 2.0 1955 150 0.5 2015 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 2. All loading with 50 W to VCC − 2.0 V (see Figure 9). 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. 10EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 65 82 105 65 83 105 65 84 105 mA Output HIGH Voltage (Note 2) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 2) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single-Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single-Ended) 3065 3390 3130 3455 3190 3515 mV VBB Output Voltage Reference 3490 3690 3555 3755 3615 3815 mV 5.0 2.0 5.0 2.0 5.0 V 150 mA IEE Power Supply Current VOH VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) IIH Input HIGH Current IIL Input LOW Current 3590 2.0 150 0.5 3655 150 0.5 0.5 3715 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 2. All loading with 50 W to VCC − 2.0 V (see Figure 9). 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 5 MC10EP139, MC100EP139 Table 7. 10EP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 65 82 105 65 83 105 65 84 105 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 2) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single-Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single-Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VBB Output Voltage Reference −1510 −1310 −1445 −1245 −1385 −1185 mV 0.0 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) IIH Input HIGH Current IIL Input LOW Current −1410 VEE+2.0 0.0 −1345 VEE+2.0 0.0 150 0.5 −1285 VEE+2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC − 2.0 V (see Figure 9). 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. 100EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 83 100 70 87 105 75 90 110 mA Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 2) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV VIH Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single-Ended) 1305 1675 1305 1675 1305 1675 mV VBB Output Voltage Reference 1725 1925 1725 1925 1725 1925 mV 3.3 2.0 3.3 2.0 3.3 V 150 mA IEE Power Supply Current VOH VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) IIH Input HIGH Current IIL Input LOW Current 1825 2.0 150 0.5 1825 150 0.5 0.5 1825 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 2. All loading with 50 W to VCC − 2.0 V (see Figure 9). 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 6 MC10EP139, MC100EP139 Table 9. 100EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 100 70 90 105 75 95 110 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 2) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mV VIH Input HIGH Voltage (Single-Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single-Ended) 3005 3375 3005 3375 3005 3375 mV VBB Output Voltage Reference 3425 3625 3425 3625 3425 3625 mV 5.0 2.0 5.0 2.0 5.0 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) IIH Input HIGH Current IIL Input LOW Current 3525 2.0 3525 150 3525 150 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 2. All loading with 50 W to VCC − 2.0 V (see Figure 9). 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 10. 100EP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 100 70 90 105 75 95 110 mA Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 2) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV VIH Input HIGH Voltage (Single-Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single-Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV VBB Output Voltage Reference −1575 −1375 −1575 −1375 −1575 −1375 mV 0.0 V 150 mA IEE Power Supply Current VOH VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) IIH Input HIGH Current IIL Input LOW Current −1475 VEE+2.0 0.0 VEE+2.0 150 0.5 −1475 0.0 VEE+2.0 150 0.5 −1475 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC − 2.0 V (see Figure 9). 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 7 MC10EP139, MC100EP139 Table 11. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 1)) −40°C Symbol Characteristic Min Typ fmax Maximum Frequency (See Figures 5, 6, 7 and 8 Fmax /JITTER) tPLH, tPHL Propagation Delay CLK, Q (Diff) MR, Q 550 700 700 800 tRR Reset Recovery 200 ts Setup Time EN, CLK DIVSEL, CLK th tPW >1 Typ 100 200 200 400 120 180 Hold Time CLK, EN CLK, DIVSEL 100 200 Minimum Pulse Width MR 550 tJITTER Random Clock Jitter (RMS) (See Figures 5, 6, 7 and 8 Fmax/JITTER) Input Voltage Swing (Differential Configuration) Output Rise/Fall Times Q, Q (20%−80%) Q, Q 85°C Max Min >1 750 850 Within Device Skew Device-to-Device Skew (Note 2) tr tf Min 600 700 tSKEW VPP 25°C Max 800 900 Typ Max >1 900 1000 675 800 825 950 100 200 100 200 400 120 180 200 400 120 180 50 140 100 200 50 140 100 200 50 140 450 550 450 550 450 Unit GHz 975 1100 ps ps ps ps ps 50 200 100 300 50 200 100 300 50 200 100 300 ps 0.2 < 1.0 0.2 < 1.0 0.2 < 1.5 ps 150 800 1200 150 800 1200 150 800 1200 mV 110 180 250 125 190 275 150 215 300 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V (see Figure 9). 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. www.onsemi.com 8 900 8 800 7 700 6 600 5 500 4 400 3 300 2 200 (JITTER) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ 1 100 0 JITTEROUT ps (RMS) VOUTpp (mV) MC10EP139, MC100EP139 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 900 8 800 7 700 6 600 5 500 4 400 3 300 2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 200 (JITTER) 1 100 0 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) Figure 6. B5, Fmax/Jitter www.onsemi.com 9 1600 1800 2000 JITTEROUT ps (RMS) VOUTpp (mV) Figure 5. B2, Fmax/Jitter ÉÉ ÉÉ ÉÉ 900 8 800 7 700 6 600 5 500 4 400 3 300 2 200 (JITTER) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ 1 100 0 JITTEROUT ps (RMS) VOUTpp (mV) MC10EP139, MC100EP139 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 900 8 800 7 700 6 600 5 500 4 400 3 300 2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 200 (JITTER) 1 100 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) Figure 8. B6, Fmax/Jitter Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) www.onsemi.com 10 JITTEROUT ps (RMS) VOUTpp (mV) Figure 7. B4, Fmax/Jitter ÉÉ ÉÉ ÉÉ MC10EP139, MC100EP139 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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