MC10EP89
3.3V / 5V ECL Coaxial
Cable Driver
Description
The MC10EP89 is a differential fanout gate specifically designed to
drive coaxial cables. The device is especially useful in digital video
broadcasting applications; for this application, since the system is
polarity free, each output can be used as an independent driver. The
driver produces swings 70% larger than a standard ECL output. When
driving a coaxial cable, proper termination is required at both ends of
the line to minimize signal loss. The 1.6 V (5 V) and 1.4 V (3.3 V)
swing allow for termination at both ends of the cable, while
maintaining a 800 mV (5 V) and 700 mV (3.3 V) swing at the
receiving end of the cable. Because of the larger output swings, the
device cannot be terminated into the standard VCC-2.0 V. All of the
DC parameters are tested with a 50 W to VCC-3.0 V load. The driver
accepts a standard differential ECL input and can run off of the digital
video broadcast standard -5.0 V supply.
http://onsemi.com
MARKING
DIAGRAMS*
8
8
SOIC-8
D SUFFIX
CASE 751
1
8
8
Features
HEP89
ALYWG
G
1
1
•310 ps Typical Propagation Delay
•Maximum Frequency > 2 GHz Typical
•1.6 V (5 V) and 1.4 V (3.3 V) VOUTpp Swing
•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
TSSOP-8
DT SUFFIX
CASE 948R
1
5V DG
G
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
•Open Input Default State
•Safety Clamp on Inputs
•Q Output Will Default LOW with Inputs Open or at VEE
•Pb-Free Packages are Available
HP89
ALYWG
G
DFN8
MN SUFFIX
CASE 506AA
1
4
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
D
= Date Code
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 7
1
Publication Order Number:
MC10EP89/D
MC10EP89
Q0
Q0
1
8
2
7
Table 1. PIN DESCRIPTION
VCC
PIN
FUNCTION
D*, D*
ECL Data Inputs
Q0, Q1, Q0, Q1
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
D
* Pins will default LOW when left open.
Q1
3
6
D
Q1
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC-8
TSSOP-8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb-Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL-94 V-0 @ 0.125 in
152 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
2
MC10EP89
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
8 TSSOP
41 to 44
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
2
280
340
Within Device Skew
Q, Q
Device to Device Skew (Note 15)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing
(Differential Configuration)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Q, Q
Typ
250
Max
>2
310
370
20
120
5.0
.5
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