MC10H124
Quad TTL‐to‐MECL
Translator With
TTL Strobe Input
Description
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The MC10H124 is a quad translator for interfacing data and control
signals between a saturated logic section and the MECL section of
digital systems. The 10H part is a functional/pinout duplication of the
standard MECL 10K™ family part, with 100% improvement in
propagation delay, and no increase in power-supply current.
Features
16
• Propagation Delay, 1.5 ns Typical
• Improved Noise Margin 150 mV
•
•
•
MARKING DIAGRAMS*
4
2
6
7
1 20
16
3
MC10H124P
AWLYYWWG
1
10
PLLC−20
FN SUFFIX
CASE 775−02
PDIP−16
P SUFFIX
CASE 648−08
(Over Operating Voltage and Temperature Range)
Voltage Compensated
MECL 10K Compatible
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
5
20 1
1
12
10H124G
AWLYYWW
1
15
11
13
14
A
WL, L
YY, Y
WW, W
G or G
GND = PIN 16
VCC ( +5.0 VDC) = PIN 9
VEE ( -5.2 VDC) = PIN 8
Figure 1. Logic Diagram
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping†
MC10H124FNG
PLCC−20
(Pb-Free)
46 Units/Tube
MC10H124FNR2G
PLCC−20
(Pb-Free)
500/Tape & Reel
MC10H124PG
PDIP−16
(Pb-Free)
25 Units/Tube
†For information on tape and reel specifications, including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 12
1
Publication Order Number:
MC10H124/D
MC10H124
GND COUT DOUT DOUT Exposed Pad (EP)
BOUT
1
16
GND
AOUT
2
15
COUT
BOUT
3
14
DOUT
AOUT
4
13
AIN
5
16
BOUT
1
DOUT
AOUT
2
12
COUT
BOUT
6
11
DIN
AOUT
BIN
7
10
CIN
VEE
8
9
VCC
COMMON
STROBE
15
14
13
12
COUT
11
DIN
3
10
CIN
4
9
VCC
MC10H124
5
6
7
8
AIN COMMON BIN VEE
STROBE
Pin assignment for QFN16 Package.
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see Table 1.
Figure 2. Pin Assignment
Table 1. DIP CONVERSION TABLE
16-Pin DIL to 20-Pin PLCC
16 PIN DIL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20 PIN PLCC
2
3
4
5
7
8
9
10
12
13
14
15
17
18
19
20
Table 2. MAXIMUM RATINGS
Symbol
Rating
Unit
VEE
Power Supply (VCC = 5.0 V)
Characteristic
−8.0 to 0
Vdc
VCC
Power Supply (VEE = −5.2 V)
0 to +7.0
Vdc
0 to VCC
Vdc
VI
Input Voltage (VCC = 5.0 V) TTL
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
Plastic
Ceramic
50
100
0 to +75
−55 to +150
−55 to +165
mA
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
MC10H124
Table 3. ELECTRICAL CHARACTERISTICS (VEE = −5.2 V ±5%, VCC = 5.0 V ± 5.0%)
0°
Symbol
Characteristic
25°
75°
Min
Max
Min
Max
Min
Max
Unit
IE
Negative Power
Supply Drain Current
−
72
−
66
−
72
mA
ICCH
ICCL
Positive Power
Supply Drain Current
−
−
16
25
−
−
16
25
−
−
18
25
mA
IR
Reverse Current
Pin 6
Pin 7
−
−
200
50
−
−
200
50
−
−
200
50
IF
Forward Current
Pin 6
Pin 7
−
−
−12.8
−3.2
−
−
−12.8
−3.2
−
−
−12.8
−3.2
5.5
−
5.5
−
5.5
−
Vdc
V(BR)in
Input Breakdown Voltage
mA
mA
VI
Input Clamp Voltage
−
−1.5
−
−1.5
−
−1.5
Vdc
VOH
High Output Voltage
−1.02
−0.84
−0.98
−0.81
−0.92
−0.735
Vdc
VOL
Low Output Voltage
−1.95
−1.63
−1.95
−1.63
−1.95
−1.60
Vdc
VIH
High Input Voltage
2.0
−
2.0
−
2.0
−
Vdc
VIL
Low Input Voltage
−
0.8
−
0.8
−
0.8
Vdc
1. Each MECL 10H™ series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.
Outputs are terminated through a 50 W resistor to −2.0 V.
Table 4. AC CHARACTERISTICS
0°
Symbol
75°
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
0.55
2.5
0.55
2.65
0.85
3.1
ns
tr
Rise Time
0.5
1.5
0.5
1.6
0.5
1.7
ns
tf
Fall Time
0.5
1.5
0.5
1.6
0.5
1.7
ns
tpd
Characteristic
25°
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H124
APPLICATIONS INFORMATION
The MC10H124 has TTL-compatible inputs and MECL
complementary open-emitter outputs that allow use as an
inverting/non-inverting translator or as a differential line
driver. When the common strobe input is at the low-logic
level, it forces all true outputs to a MECL low-logic state and
all inverting outputs to a MECL high-logic state.
An advantage of this device is that TTL-level information
can be transmitted differentially, via balanced twisted pair
lines, to MECL equipment, where the signal can be received
by the MC10H115 or MC10H116 differential line receivers.
The power supply requirements are ground, +5.0 V, and
−5.2 V.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
MECL is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE V
16
1
SCALE 1:1
D
A
16
9
E
H
E1
1
NOTE 8
b2
8
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
A1
C
D1
e
SEATING
PLANE
M
eB
END VIEW
16X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
16
STYLE 1:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
STYLE 2:
PIN 1. COMMON DRAIN
2. COMMON DRAIN
3. COMMON DRAIN
4. COMMON DRAIN
5. COMMON DRAIN
6. COMMON DRAIN
7. COMMON DRAIN
8. COMMON DRAIN
9. GATE
10. SOURCE
11. GATE
12. SOURCE
13. GATE
14. SOURCE
15. GATE
16. SOURCE
98ASB42431B
PDIP−16
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
20 LEAD PLCC
CASE 775−02
ISSUE G
20 1
DATE 06 APR 2021
SCALE 1:1
B
0.007 (0.180)
Y BRK
−N−
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
−L−
−M−
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D−D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
C
H
−T−
VIEW S
G1
0.010 (0.250) S T L-M
SEATING
PLANE
DESCRIPTION:
N
S
F
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M,
1982.
2. DIMENSIONS IN INCHES.
3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP
OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT
DATUM −T−, SEATING PLANE.
5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER
THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
DOCUMENT NUMBER:
S
K
0.004 (0.100)
J
T L-M
M
K1
E
G
0.007 (0.180)
98ASB42594B
20 LEAD PLCC
GENERIC
MARKING DIAGRAM*
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.021
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
−−−
0.020
2_
10 _
0.310
0.330
0.040
−−−
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.53
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10 _
7.88
8.38
1.02
−−−
1 20
XXXXXXXXX
XXXXXXXXG
AWLYYWW
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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