MC10H645FNR2

MC10H645 2:1:9 TTL Clock Driver Description The MC10H645 is a single supply, low skew, TTL I/O 2:1:9 Clock Driver. Devices in the H600 clock driver family utilizes the PLCC−28 for optimal power and signal pin placement. The device features a 24 mA TTL output stage with AC performance specified into a 50 pF load capacitance. A 2:1 input Mux is provided on chip to allow for distributing both system and diagnostic clock signals or designing clock redundancy into a system. With the SEL input held LOW the DO input will be selected, while the D1 input is selected when the SEL input is forced HIGH. www.onsemi.com Features • • • • • • • PLCC FN SUFFIX CASE 776 Low Skew Typically 0.65 ns Within Device Guaranteed Skew Spec 1.25 ns Part−to−Part Input Clock Muxing Differential ECL Internal Design Single Supply Extra TTL and ECL Power/Ground Pins These Devices are Pb−Free and are RoHS Compliant* MARKING DIAGRAM MC10H645G AWLYYWW A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2015 April, 2015 − Rev. 7 1 Publication Order Number: MC10H645/D MC10H645 TTL Outputs Q0 TTL Inputs MUX D0 D0 D0 D1 D1 D1 S GT Q6 VT Q7 VT Q8 GT 25 24 23 22 21 20 19 GT 26 18 NC Q5 27 17 D0 VT 28 16 D1 Q3 Q4 1 15 VE Q4 VT 2 14 SEL Q5 Q3 3 13 GE Q6 GT 4 12 NC Q1 Q2 Q Q S SEL 5 6 7 8 9 10 11 GT Q2 VT Q1 VT Q0 GT Q7 Figure 2. Pinout: 28−Lead PLCC (Top View) Q8 Figure 1. Logic Diagram Table 1. PIN NAMES PIN FUNCTION GT VT VE GE Dn Q0 − Q8 SEL TTL Ground (0 V) TTL VCC (+5.0 V) ECL VCC (+5.0 V) ECL Ground (0 V) TTL Signal Input TTL Signal Outputs TTL Mux Select Table 2. PIN DESCRIPTIONS Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Q4 VT Q3 GT GT Q2 VT Q1 VT Q0 GT NC GE SEL Description Pin Symbol 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VE D1 D0 NC GT Q8 VT Q7 VT Q6 GT GT Q5 VT Signal Output (TTL) TTL VCC (+5.0 V) Signal Output (TTL) TTL Ground (0 V) TTL Ground (0 V) Signal Output (TTL) TTL VCC (+5.0 V) Signal Output (TTL) TTL VCC (+5.0 V) Signal Output (TTL) TTL Ground (0 V) No Connection ECL Ground Select Input (TTL) Description ECL VCC (+5.0 V) Signal Input (TTL) Signal Input (TTL) No Connection TTL Ground (0 V) Signal Output (TTL) TTL VCC (+5.0 V) Signal Output (TTL) TTL VCC (+5.0 V) Signal Output (TTL) TTL Ground (0 V) TTL Ground (0 V) Signal Output (TTL) TTL VCC (+5.0 V) Table 3. TRUTH TABLE D0 D1 SEL Q L H X X X X L H L L H H L H L H www.onsemi.com 2 MC10H645 Table 4. ABSOLUTE RATINGS (Do not exceed) Symbol Characteristic Value Unit VE (ECL) Power Supply Voltage −0.5 to +7.0 V VT (TTL) Power Supply Voltage −0.5 to +7.0 V VI (TTL) Input Voltage −0.5 to +7.0 V Vout Disabled 3−State Output 0.0 to VT V Tstg Storage Temperature −65 to 150 °C Tamb Operating Temperature 0.0 to +85 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol IEE Characteristic Power Supply Current ICCH Min 25°C Max Min 85°C Max Min Max Unit Condition ECL 30 30 30 mA VE Pin TTL 30 30 30 mA Total all VT pins 35 35 35 mA ICCL VOH Output HIGH Voltage VOL Output LOW Voltage IOS Output Short Circuit Current 2.5 2.0 2.5 2.0 2.5 2.0 0.5 −100 V IOH = −3.0 mA IOH = −15 mA 0.5 V IOL = 24 mA −225 mA VOUT = 0 V 0.5 −225 −100 −225 −100 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Table 6. TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic VIH VIL Input HIGH Voltage Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current VOH Output HIGH Voltage VOL Output LOW Voltage VIK Input Clamp Voltage IOS Output Short Circuit Current Min 25°C Max Min 2.0 2.0 Min Max 2.0 Unit Condition V 0.8 0.8 0.8 20 100 20 100 20 100 mA VIN = 2.7 V VIN = 7.0 V −0.6 mA VIN = 0.5 V −0.6 −0.6 2.5 2.0 2.5 2.0 0.5 2.5 2.0 0.5 −1.2 −100 85°C Max −100 −225 IOH = −3.0 mA IOH = −24 mA V IOL = 24 mA −1.2 V IIN = −18 mA −225 mA 0.5 −1.2 −225 V −100 VOUT = 0 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 3 MC10H645 Table 7. AC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic tPLH Propagation Delay D0 to Output Only tPLH Propagation Delay D1 to Output tPHL Propagation Delay D0 to Output D1 to Output Q0−Q8 25°C 85°C Min Max Min Max Min Max Unit 4.8 5.8 4.8 5.8 5.2 6.2 ns 4.8 5.8 4.8 5.8 5.2 6.2 ns 4.8 4.8 5.8 5.8 4.8 4.8 5.8 5.8 5.2 5.2 6.2 6.2 Condition CL = 50 pF ns tskpp Part−to−Part Skew D0 to Output Only 1.0 1.0 1.0 ns tskwd* Within−Device Skew D0 to Output Only 0.65 0.65 0.65 ns tPLH Propagation Delay SEL to Q Q0−Q8 4.5 6.5 5.0 7.0 5.2 7.2 ns CL = 50 pF tr tf Output Rise/Fall Time 0.8V to 2.0V Q0−Q8 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 ns CL = 50 pF tS Setup Time SEL to D ns 1.0 1.0 1.0 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. *Within−Device Skew defined as identical transitions on similar paths through a device. Table 8. DUTY CYCLE SPECIFICATIONS (0°C ≤ TA ≤ 85°C; Duty Cycle Measured Relative to 1.5 V) Symbol PW Characteristic Range of VCC and CL to Meet Min Pulse Width (HIGH or LOW) at fout ≤50MHz VCC CL PW Min Nom Max Unit 4.875 10.0 9.0 5.0 5.125 50.0 11.0 V pF ns Condition All Outputs ORDERING INFORMATION Package Shipping† MC10H645FNG PLCC−28 (Pb−Free) 37 Units / Rail MC10H645FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 4 MC10H645 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX CASE 776−02 ISSUE E 0.007 (0.180) B M T L-M N S T L-M S S Y BRK −N− 0.007 (0.180) U M N S D Z −M− −L− W 28 D X G1 0.010 (0.250) T L-M S N S S V 1 VIEW D−D A 0.007 (0.180) R 0.007 (0.180) M T L-M S N S 0.007 (0.180) H M T L-M N S S Z M T L-M S N S K1 C E 0.004 (0.100) G S K SEATING PLANE F VIEW S G1 0.010 (0.250) −T− J T L-M S N NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). VIEW S S DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.021 0.050 BSC 0.026 0.032 0.020 --0.025 --0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10_ 0.410 0.430 0.040 --- MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.53 1.27 BSC 0.66 0.81 0.51 --0.64 --11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10_ 10.42 10.92 1.02 --- www.onsemi.com 5 0.007 (0.180) M T L-M S N S MC10H645 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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