MC14012BDR2G

MC14012B Dual 4-Input NAND Gates The MC14012B dual 4−input NAND gates are constructed with P−Channel and N−Channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. http://onsemi.com Features • Supply Voltage Range = 3.0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low−Power TTL Loads or One Low−Power • • • • Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant SOIC−14 D SUFFIX CASE 751A MARKING DIAGRAM 14 14012BG AWLYWW 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Symbol VDD Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 11 1 Publication Order Number: MC14012B/D MC14012B MC14012B Dual 4−Input NAND Gate OUTA 1 14 VDD IN 1A 2 13 OUTB IN 2A 3 12 IN 4B IN 3A 4 11 IN 3B IN 4A 5 10 IN 2B NC 6 9 IN 1B VSS 7 8 NC 2 3 4 5 9 10 11 12 1 13 NC = 6, 8 VDD = PIN 14 VSS = PIN 7 NC = NO CONNECTION Figure 1. Pin Assignment Figure 2. Logic Diagram ORDERING INFORMATION Package Shipping† MC14012BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14012BDG* SOIC−14 (Pb−Free) 55 Units / Rail MC14012BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel NLV14012BDR2G* SOIC−14 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14012B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 0.25 0.5 1.0 − − − 0.0005 0.0010 0.0015 0.25 0.5 1.0 − − − 7.5 15 30 mAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) mAdc IT = (0.3 mA/kHz) f + IDD/N IT = (0.6 mA/kHz) f + IDD/N IT = (0.9 mA/kHz) f + IDD/N mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. http://onsemi.com 3 MC14012B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns tTLH Output Fall Time tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 160 65 50 300 130 100 Unit ns ns tPLH, tPHL ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 14 20 ns VDD 20 ns PULSE GENERATOR INPUT OUTPUT tPHL CL * 7 OUTPUT INVERTING *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. 90% 50% 10% tTHL tPLH Figure 3. Switching Time Test Circuit and Waveforms VDD VDD 2, 9 * 3, 10 VSS 4, 11 5, 12 1, 13 SAME AS ABOVE 7 *Inverter omitted VSS Figure 4. Circuit Schematic − One of Two Gates Shown http://onsemi.com 4 VOH tTLH tPHL tTLH 14 0V tPLH OUTPUT NON−INVERTING VSS VDD 90% 50% 10% INPUT 90% 50% 10% tTHL VOL VOH VOL MC14012B TYPICAL B−SERIES GATE CHARACTERISTICS N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE) −10 5.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) −9.0 4.0 TA = −55°C 3.0 −40°C +85°C +25°C 2.0 +125°C 1.0 −8.0 TA = −55°C −7.0 −40°C −6.0 −5.0 +25°C +85°C −4.0 −3.0 +125°C −2.0 −1.0 0 0 0 1.0 2.0 3.0 4.0 0 5.0 VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) Figure 5. VGS = 5.0 Vdc −4.0 −5.0 −45 TA = −55°C 16 14 −40°C 12 +25°C +85°C 10 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) −3.0 −50 18 +125°C 8.0 6.0 −40 −35 TA = −55°C −30 −25 + 25°C −20 +85°C +125°C −10 2.0 −5.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0 0 10 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −8.0 −9.0 −10 VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) Figure 7. VGS = 10 Vdc Figure 8. VGS = − 10 Vdc - 100 45 - 90 40 - 80 ID , DRAIN CURRENT (mA) 50 TA = −55°C 35 30 −40°C 25 +25°C 20 +85°C +125°C 15 −40°C −15 4.0 0 ID , DRAIN CURRENT (mA) −2.0 Figure 6. VGS = − 5.0 Vdc 20 10 5.0 0 −1.0 VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc) - 70 - 60 TA = −55°C - 50 −40°C +25°C - 40 +85°C - 30 +125°C - 20 - 10 0 2.0 4.0 6.0 8.0 10 12 14 16 18 0 20 0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 9. VGS = 15 Vdc −2.0 −4.0 −6.0 −8.0 −10 −12 −14 −16 −18 −20 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 10. VGS = − 15 Vdc These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin. http://onsemi.com 5 MC14012B V out , OUTPUT VOLTAGE (Vdc) V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 5.0 4.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 3.0 2.0 1.0 0 0 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 10 8.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 6.0 4.0 2.0 0 1.0 0 2.0 3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc) 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 11. VDD = 5.0 Vdc DC NOISE MARGIN SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 16 V out , OUTPUT VOLTAGE (Vdc) Figure 12. VDD = 10 Vdc The DC noise margin is defined as the input voltage range from an ideal “1” or “0” input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the “1” and “0” levels = 1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply 14 12 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, A 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 13. VDD = 15 Vdc VDD Vout Vout VO VO VO VO VDD VDD VDD 0 Vin 0 VIL Vin VIL VIH VIH VSS = 0 VOLTS DC (a) Inverting Function (b) Non−Inverting Function Figure 14. DC Noise Immunity http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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