MC14014BFEL

MC14014B, MC14021B 8-Bit Static Shift Register The MC14014B and MC14021B 8−bit static shift registers are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These shift registers find primary use in parallel−to−serial data conversion, synchronous and asynchronous parallel input, serial output data queueing; and other general purpose register applications requiring low power and/or high noise immunity. http://onsemi.com Features • • • • • • • • • • • • Synchronous Parallel Input/Serial Output (MC14014B) Asynchronous Parallel Input/Serial Output (MC14021B) Synchronous Serial Input/Serial Output Full Static Operation “Q” Outputs from Sixth, Seventh, and Eighth Stages Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range MC14014B Pin−for−Pin Replacement for CD4014B MC14021B Pin−for−Pin Replacement for CD4021B NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol VDD Unit −0.5 to +18.0 V V Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) PIN ASSIGNMENT P8 1 16 VDD Q6 2 15 P7 Q8 3 14 P6 P4 4 13 P5 P3 5 12 Q7 P2 6 11 DS P 1 7 10 C 8 9 VSS P/S MARKING DIAGRAM Value −0.5 to VDD + 0.5 Vin, Vout SOIC−16 D SUFFIX CASE 751B TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C 16 140xxBG AWLYWW 1 xx A WL, L YY, Y WW, W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 9 1 Publication Order Number: MC14014B/D MC14014B, MC14021B TRUTH TABLE SERIAL OPERATION: t Clock DS P/S n n+1 n+2 n+3 Q6 t=n+6 Q7 t=n+7 Q8 t=n+8 0 1 0 1 0 0 0 0 0 1 0 1 ? 0 1 0 ? ? 0 1 X 0 Q6 Q7 Q8 PARALLEL OPERATION: Clock MC14014B MC14021B DS X X X X P/S Pn *Qn 1 0 0 1 1 1 *Q6, Q7, & Q8 are available externally X = Don’t Care LOGIC DIAGRAM P1 P2 7 9 P3 6 P6 5 P7 14 P8 15 1 P/S 11 DS D C Q D C Q D Q C D Q D Q D C Q C Q C Q 10 CLOCK VDD = PIN 16 VSS = PIN 8 P4 = PIN 4 P5 = PIN 13 http://onsemi.com 2 2 Q6 12 Q7 3 Q8 MC14014B, MC14021B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit Output Voltage Vin = VDD or 0 “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc Vin = 0 or VDD “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) “1” Level 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 −1.3 −3.4 –4.2 –0.88 –2.25 −8.8 − − − − –1.7 −0.36 –0.9 −2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 15 − − − 0.005 0.010 0.015 5.0 10 15 − − − 150 300 600 mAdc IT 5.0 10 15 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) VIH Vdc IOH Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Vdc mAdc IT = (0.75 mA/kHz) f + IDD IT = (1.50 mA/kHz) f + IDD IT = (2.25 mA/kHz) f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.0015. http://onsemi.com 3 MC14014B, MC14021B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 400 170 115 800 340 230 Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time (Clock to Q, P/S to Q) tPHL, tPLH = (1.7 ns/pF) CL + 315 ns tPHL, tPLH = (0.66 ns/pF) CL + 137 ns tPHL, tPLH = (0.5 ns/pF) CL + 90 ns tPLH, tPHL Clock Pulse Width tWH 5.0 10 15 400 175 135 150 75 40 − − − ns fcl 5.0 10 15 − − − 3.0 6.0 8.0 1.5 3.0 4.0 MHz Parallel/Serial Control Pulse Width tWH 5.0 10 15 400 175 135 150 75 40 − − − ns Setup Time P/S to Clock tsu 5.0 10 15 200 100 80 100 50 40 − − − ns Hold Time Clock to P/S th 5.0 10 15 20 20 25 – 2.5 – 10 0 − − − ns Setup Time Data (Parallel or Serial) to Clock or P/S tsu 5.0 10 15 350 80 60 150 50 30 − − − ns Hold Time Clock to Ds th 5.0 10 15 45 35 35 0 0 5 − − − ns Hold Time Clock to Pn th 5.0 10 15 50 45 45 25 20 20 − − − ns tr(cl) 5.0 10 15 − − − − − − 15 5 4 ms Clock Frequency Input Clock Rise Time ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14014B, MC14021B VDD PULSE GENERATOR P/S C P6 P7 P8 DS VDD Vout Q6 P/S C P6 P7 P8 DS PULSE GENERATOR Q7 IOH Q8 EXTERNAL POWER SUPPLY Vout Q6 Q7 Q8 IOL EXTERNAL POWER SUPPLY Preset output under test to a logic “1” level. Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit VDD 500 mF ID 0.01 mF CERAMIC P/S C P1 P2 P3 P4 P5 P6 P7 P8 DS PULSE GENERATOR 1 PULSE GENERATOR 2 Q6 CL Q7 CL Q8 VSS CL 1 f CLOCK 50% DATA Figure 3. Power Dissipation Test Circuit and Waveform http://onsemi.com 5 MC14014B, MC14021B SW 1 VDD 1 PULSE GENERATOR 1 2 2 PULSE GENERATOR 2 1 2 1 SWITCH POSITION 1 = PARALLEL IN SWITCH POSITION 2 = SERIAL IN VDD P/S C P1 P2 P3 P4 P5 P6 P7 P8 DS 20 ns PARALLEL OR SERIAL DATA INPUT Q6 90% 50% 10% tsu VSS tWH Q7 CLOCK OR P/S INPUT CL Q8 VSS tTHL 90% 50% 10% tWH tPLH VDD VSS tWL tPHL VOH 90% 50% 10% Q OUTPUT SW 2 20 ns VDD tTLH VOL tTHL tWL = tWH = 50% DUTY CYCLE Figure 4. Switching Time Test Circuit and Waveforms ORDERING INFORMATION Package Shipping† MC14014BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14014BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14014BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel MC14021BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14021BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14021BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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