MC14015BFEL

MC14015B Dual 4-Bit Static Shift Register The MC14015B dual 4−bit static shift register is constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4−state serial−input/parallel−output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master−slave flip−flops. Data is shifted from one stage to the next during the positive−going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial−to−parallel conversion where low power dissipation and/or noise immunity is desired. • • • SOIC−16 D SUFFIX CASE 751B MARKING DIAGRAM Features • • • • http://onsemi.com Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge−Clocked Flip−Flop Design Logic State is Retained Indefinitely with Clock Level either High or Low; Information is Transferred to the Output only on the Positive-going Edge of the Clock Pulse Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant 16 14015BG AWLYWW 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 9 1 Publication Order Number: MC14015B/D MC14015B PIN ASSIGNMENT CB 1 16 VDD Q3B 2 15 DB Q2A 3 14 RB Q1A 4 13 Q0B Q0A 5 12 Q1B RA 6 11 Q2B DA 7 10 Q3A VSS 8 9 CA BLOCK DIAGRAM Q0 5 Q1 4 Q2 3 D 7 C 9 R Q3 10 Q0 13 Q1 12 Q2 11 6 D 15 C 1 R Q3 2 14 VDD = PIN 16 VSS = PIN 8 TRUTH TABLE C X D R Q0 Qn 0 0 0 Qn−1 1 0 1 Qn−1 X 0 No Change No Change X 1 0 0 X = Don’t Care Qn = Q0, Q1, Q2, or Q3, as applicable. Qn−1 = Output of prior stage. ORDERING INFORMATION Package Shipping† MC14015BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14015BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14015BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14015B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit Output Voltage Vin = VDD or 0 “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc Vin = 0 or VDD “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage (VO = 4.5 or .05 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) “1” Level 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 −1.3 −3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 −0.36 –0.9 −2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) VIH Vdc IOH Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Vdc mAdc IT = (1.2 mA/kHz)f + IDD IT = (2.4 mA/kHz)f + IDD IT = (3.6 mA/kHz)f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002. http://onsemi.com 3 MC14015B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock, Data to Q tPLH, tPHL = (1.7 ns/pF) CL + 225 ns tPLH, tPHL = (0.66 ns/pF) CL + 92 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Reset to Q tPLH, tPHL = (1.7 ns/pF) CL + 375 ns tPLH, tPHL = (0.66 ns/pF) CL + 147 ns tPLH, tPHL = (0.5 ns/pF) CL + 95 ns tPLH, tPHL Clock Pulse Width VDD Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns 5.0 10 15 − − − 310 125 90 750 250 170 5.0 10 15 − − − 460 180 120 750 250 170 tWH 5.0 10 15 400 175 135 185 85 55 − − − ns fcl 5.0 10 15 − − − 2.0 6.0 7.5 1.5 3.0 3.75 MHz tTLH, tTHL 5.0 10 15 − − − − − − 15 5 4 ms Reset Pulse Width tWH 5.0 10 15 400 160 120 200 80 60 − − − ns Setup Time tsu 5.0 10 15 350 100 75 100 50 40 − − − ns Clock Pulse Frequency Clock Pulse Rise and Fall Times 5. The formulas given are for typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14015B VDD PULSE GENERATOR 2 D PULSE GENERATOR 1 0.01 mF CERAMIC ID 500 mF C R VDD Q0 Q1 Q2 Q3 CL CL CL CL VSS 1 f CLOCK 50% DATA Figure 1. Power Dissipation Test Circuit and Waveform tTLH tTHL DATA INPUT VDD 90% 50% 10% 0V tsu PULSE GENERATOR 2 VDD D PULSE GENERATOR 1 Q0 CL Q1 SYNC CLOCK INPUT CL Q2 C R t- tTLH tWH tPLH CL Q3 tTHL 90% Q0 tWL = tWH = 50% Duty Cycle tTLH = tTHL ≤ 20 ns 0V tPHL CL VSS VDD 90% 50% 10% tWL 50% 10% tTHL tTLH Figure 2. Switching Test Circuit and Waveforms PULSE GENERATOR 2 VDD D CL Q1 SYNC PULSE GENERATOR 1 Q0 0V tsu CL Q3 VDD 50% CL Q2 C R CLOCK INPUT th CL DATA INPUT VSS 50% Figure 3. Setup and Hold Time Test Circuit and Waveforms http://onsemi.com 5 VDD 0V http://onsemi.com 6 DATA IN VSS VDD DATA INPUT BUFFER DATA IN CLOCK RESET DATA TO FIRST BIT RESET IN VSS VDD RESET INPUT BUFFER VSS VDD SINGLE BIT RESET TO 4 BITS CLOCK IN TO D OF NEXT BIT VSS VDD CLOCK TO 4 BITS CLOCK INPUT BUFFER Q MC14015B CIRCUIT SCHEMATICS MC14015B LOGIC DIAGRAMS SINGLE BIT Q C C TO D OF NEXT BIT DATA C C C C C C RESET C C C COMPLETE DEVICE 5 4 Q0 3 Q1 10 Q2 Q3 DATA INPUT BUFFER D D 7 C CLOCK INPUT BUFFER C R Q D Q C R Q D Q C R Q D Q C Q R Q 9 R 6 13 RESET INPUT BUFFER 12 Q0 11 Q1 2 Q2 Q3 DATA INPUT BUFFER D D 15 CLOCK INPUT BUFFER C C R Q D Q C R Q D Q C R Q D Q C Q R Q 1 VDD = PIN 16 VSS = PIN 8 R 14 RESET INPUT BUFFER http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative