MC14025BDR2G

MC14001B Series B-Suffix Series CMOS Gates MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. http://onsemi.com Features • Supply Voltage Range = 3.0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low−power TTL Loads or One Low−power • • • • Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant TSSOP−14 DT SUFFIX CASE 948G MARKING DIAGRAMS 14 14 14 0xxB ALYWG G 140xxBG AWLYWW 1 1 SOIC−14 MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter SOIC−14 D SUFFIX CASE 751A xx A WL, L YY, Y WW, W G or G TSSOP−14 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C MC14001B Quad 2−Input NOR Gate Tstg Storage Temperature Range −65 to +150 °C MC14011B Quad 2−Input NAND Gate TL Lead Temperature (8−Second Soldering) 260 °C MC14023B Triple 3−Input NAND Gate MC14025B Triple 3−Input NOR Gate MC14071B Quad 2−Input OR Gate MC14073B Triple 3−Input AND Gate MC14081B Quad 2−Input AND Gate MC14082B Dual 4−Input AND Gate Symbol VDD Vin, Vout Iin, Iout VESD DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) ESD Withstand Voltage Human Body Model Machine Model Charged Device Model V > 3000 > 300 N/A This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. July, 2014 − Rev. 11 DEVICE INFORMATION Device Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C © Semiconductor Components Industries, LLC, 2014 (Note: Microdot may be in either location) 1 Description ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Publication Order Number: MC14001B/D MC14001B Series LOGIC DIAGRAMS NAND OR AND MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14071B Quad 2−Input OR Gate MC14081B Quad 2−Input AND Gate 2 INPUT NOR 1 2 3 1 2 3 1 2 3 1 2 3 5 6 4 5 6 4 5 6 4 5 6 4 8 9 10 8 9 10 8 9 10 8 9 10 12 13 11 12 13 11 12 13 11 12 13 11 3 INPUT MC14025B Triple 3−Input NOR Gate 1 2 8 3 4 5 11 12 13 9 6 10 MC14073B Triple 3−Input AND Gate MC14023B Triple 3−Input NAND Gate 1 2 8 3 4 5 11 12 13 1 2 8 3 4 5 11 12 13 9 6 10 9 6 10 MC14082B Dual 4−Input AND Gate 2 3 4 5 9 10 11 12 1 13 NC = 6, 8 VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES PIN ASSIGNMENTS MC14001B Quad 2−Input NOR Gate MC14023B Triple 3−Input NAND Gate MC14011B Quad 2−Input NAND Gate MC14025B Triple 3−Input NOR Gate IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C OUTA 3 12 IN 1D OUTA 3 12 IN 1D IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C OUTB 4 11 OUTD OUTB 4 11 OUTD IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 1B 5 10 OUTC IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C OUTB 6 9 OUTA OUTB 6 9 OUTA VSS 7 8 IN 1C VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 3A MC14071B Quad 2−Input OR Gate MC14073B Triple 3−Input AND Gate MC14081B Quad 2−Input AND Gate MC14082B Dual 4−Input AND Gate IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 2D IN 1A 2 13 OUTB OUTA 3 12 IN 1D IN 1B 3 12 IN 2C OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTB 4 11 OUTD IN 2B 4 11 IN 1C OUTB 4 11 OUTD IN 3A 4 11 IN 3B IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 2B 6 9 IN 2C OUTB 6 9 OUTA IN 2B 6 9 IN 2C NC 6 9 IN 1B VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 1C VSS 7 8 NC NC = NO CONNECTION http://onsemi.com 2 MC14001B Series ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 0.25 0.5 1.0 − − − 0.0005 0.0010 0.0015 0.25 0.5 1.0 − − − 7.5 15 30 mAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) mAdc IT = (0.3 mA/kHz) f + IDD/N IT = (0.6 mA/kHz) f + IDD/N IT = (0.9 mA/kHz) f + IDD/N mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. http://onsemi.com 3 MC14001B Series B−SERIES GATE SWITCHING TIMES SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time, All B−Series Gates tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns tTLH Output Fall Time, All B−Series Gates tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time MC14001B, MC14011B only tPLH, tPHL = (0.90 ns/pF) CL + 80 ns tPLH, tPHL = (0.36 ns/pF) CL + 32 ns tPLH, tPHL = (0.26 ns/pF) CL + 27 ns All Other 2, 3, and 4 Input Gates tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 8−Input Gates (MC14068B, MC14078B) tPLH, tPHL = (0.90 ns/pF) CL + 155 ns tPLH, tPHL = (0.36 ns/pF) CL + 62 ns tPLH, tPHL = (0.26 ns/pF) CL + 47 ns VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns tPLH, tPHL ns 5.0 10 15 − − − 125 50 40 250 100 80 5.0 10 15 − − − 160 65 50 300 130 100 5.0 10 15 − − − 200 80 60 350 150 110 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 14 PULSE GENERATOR 20 ns VDD 20 ns INPUT INPUT OUTPUT 7 0V tPLH tPHL CL * VDD 90% 50% 10% OUTPUT INVERTING VSS tTHL tPLH OUTPUT NON-INVERTING *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. tTLH Figure 1. Switching Time Test Circuit and Waveforms http://onsemi.com 4 VOH 90% 50% 10% tTLH tPHL 90% 50% 10% tTHL VOL VOH VOL MC14001B Series CIRCUIT SCHEMATIC NOR, OR GATES MC14001B, MC14071B One of Four Gates Shown MC14025B One of Three Gates Shown VDD VDD 14 VDD 1, 3, 11 1, 6, 8, 13 * 2, 4, 12 2, 5, 9, 12 14 VDD 3, 4, 10, 11 * VSS VSS 7 9, 6, 10 VSS VDD *Inverter omitted in MC14001B 8, 5, 13 7 VSS VSS *Inverter omitted in MC14025B CIRCUIT SCHEMATIC NAND, AND GATES MC14023B, MC14073B One of Three Gates Shown MC14011B, MC14081B One of Four Gates Shown VDD 14 VDD * 3, 4, 10, 11 2, 4, 12 1, 3, 11 14 2, 5, 9, 12 VDD 1, 6, 8, 13 VSS 7 VSS *Inverter omitted in MC14011B * VDD 9, 6, 10 8, 5, 13 7 VSS VSS *Inverter omitted in MC14023B http://onsemi.com 5 MC14001B Series TYPICAL B−SERIES GATE CHARACTERISTICS N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE) - 10 5.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) - 9.0 4.0 TA = - 55°C 3.0 - 40°C + 85°C + 25°C 2.0 + 125°C 1.0 - 8.0 TA = - 55°C - 7.0 - 40°C - 6.0 - 5.0 + 25°C + 85°C - 4.0 - 3.0 + 125°C - 2.0 - 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 0 5.0 0 Figure 2. VGS = 5.0 Vdc - 50 - 45 TA = - 55°C 16 14 - 40°C 12 + 25°C + 85°C 10 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 18 + 125°C 8.0 6.0 - 40 - 35 - 25 + 85°C - 15 2.0 - 5.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 9.0 0 10 - 40°C + 25°C - 20 - 10 0 TA = - 55°C - 30 4.0 + 125°C 0 Figure 4. VGS = 10 Vdc - 100 45 - 90 40 - 80 35 TA = - 55°C 30 - 40°C 25 + 25°C ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 5. VGS = − 10 Vdc 50 + 85°C 20 + 125°C 15 10 5.0 0 - 5.0 Figure 3. VGS = − 5.0 Vdc 20 0 - 1.0 - 2.0 - 3.0 - 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) - 70 - 60 TA = - 55°C - 50 - 40°C + 25°C - 40 + 85°C - 30 + 125°C - 20 - 10 0 2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 18 0 20 0 Figure 6. VGS = 15 Vdc - 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 7. VGS = − 15 Vdc These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin. http://onsemi.com 6 - 18 - 20 MC14001B Series TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d) V out , OUTPUT VOLTAGE (Vdc) V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 5.0 4.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 3.0 2.0 1.0 0 0 1.0 2.0 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 10 8.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 6.0 4.0 2.0 0 3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc) 0 2.0 Figure 8. VDD = 5.0 Vdc V out , OUTPUT VOLTAGE (Vdc) 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 9. VDD = 10 Vdc DC NOISE MARGIN 16 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 14 The DC noise margin is defined as the input voltage range from an ideal “1” or “0” input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the “1” and “0” levels = 12 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 10 8.0 6.0 4.0 2.0 0 4.0 0 2.0 4.0 1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 10. VDD = 15 Vdc Vout VDD Vout VO VO VO VO VDD VDD 0 VDD Vin VIL 0 VIH Vin VIL VIH VSS = 0 VOLTS DC (a) Inverting Function (b) Non−Inverting Function Figure 11. DC Noise Immunity http://onsemi.com 7 MC14001B Series ORDERING INFORMATION Device MC14001BDG NLV14001BDG* MC14001BDR2G NLV14001BDR2G* MC14001BDTR2G NLV14001BDTR2G* MC14001BFELG MC14011BDG NLV14011BDG* MC14011BDR2G NLV14011BDR2G* MC14011BDTR2G NLV14011BDTR2G* MC14011BFG MC14011BFELG Package Shipping† SOIC−14 (Pb−Free) 55 Units / Rail SOIC−14 (Pb−Free) 2500 Units / Tape & Reel TSSOP−14 (Pb−Free) SOEIAJ−14 (Pb−Free) 2000 Units / Tape & Reel SOIC−14 (Pb−Free) 55 Units / Rail SOIC−14 (Pb−Free) 2500 Units / Tape & Reel TSSOP−14 (Pb−Free) SOEIAJ−14 (Pb−Free) 50 Units / Rail 2000 Units / Tape & Reel MC14023BDG SOIC−14 (Pb−Free) 55 Units / Rail MC14023BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel SOEIAJ−14 (Pb−Free) 2000 Units / Tape & Reel SOIC−14 (Pb−Free) 55 Units / Rail SOIC−14 (Pb−Free) 2500 Units / Tape & Reel SOIC−14 (Pb−Free) 55 Units / Rail SOIC−14 (Pb−Free) 2500 Units / Tape & Reel NLV14023BDR2G* MC14023BFELG MC14025BDG NLV14025BDG* MC14025BDR2G NLV14025BDR2G* MC14071BDG NLV14071BDG* MC14071BDR2G NLV14071BDR2G* MC14071BDTG MC14071BDTR2G 96 Units per Rail TSSOP−14 (Pb−Free) NLV14071BDTR2G* 2500 Units / Tape & Reel MC14073BDG SOIC−14 (Pb−Free) 55 Units / Rail MC14073BDR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel http://onsemi.com 8 MC14001B Series ORDERING INFORMATION (continued) Device MC14081BDG NLV14081BDG* MC14081BDR2G NLV14081BDR2G* MC14081BDTR2G NLV14081BDTR2G* Package Shipping† SOIC−14 (Pb−Free) 55 Units / Rail SOIC−14 (Pb−Free) 2500 Units / Tape & Reel TSSOP−14 (Pb−Free) MC14082BDG NLV14082BDG* SOIC−14 (Pb−Free) MC14082BDR2G 55 Units / Rail 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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