MC14029B
Binary/Decade Up/Down
Counter
The MC14029B Binary/Decade up/down counter is constructed
with MOS P−channel and N−channel enhancement mode devices in
a single monolithic structure. The counter consists of type D flip−flop
stages with a gating structure to provide toggle flip−flop capability.
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
difference counting and frequency synthesizer applications where low
power dissipation and/or high noise immunity is desired. It is also
useful in A/D and D/A conversion and for magnitude and sign
generation.
Features
•
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge−Clocked Design − Count Occurs on Positive Going Edge
of Clock
Asynchronous Preset Enable Operation
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin for Pin Replacement for CD4029B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
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SOIC−16
D SUFFIX
CASE 751B
MARKING DIAGRAM
16
14029BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
VDD
DC Supply Voltage Range
Value
Unit
−0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range (DC or Transient)
−0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package (Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 10
1
Publication Order Number:
MC14029B/D
MC14029B
PIN ASSIGNMENT
PE
1
16
VDD
Q3
2
15
CLK
P3
3
14
Q2
P0
4
13
P2
Cin
5
12
P1
Q0
6
11
Q1
Cout
7
10
U/D
VSS
8
9
B/D
TRUTH TABLE
Carry In
Up/Down
Preset Enable
Action
1
X
0
No Count
0
1
0
Count Up
0
0
0
Count Down
X
X
1
Preset
X = Don’t Care
ORDERING INFORMATION
Package
Shipping†
MC14029BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
NLV14029BDR2G*
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14029B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C
25_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
125_C
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance, (Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent, Per Package)
(CL = 50 pF on all outputs, all buffers
switching)
mAdc
IT = (0.58 mA/kHz) f + IDD
IT = (1.20 mA/kHz) f + IDD
IT = (1.70 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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3
MC14029B
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Clk to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Clk to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Cin to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
tPLH,
tPHL
PE to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
VDD
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
−
−
−
200
100
90
400
200
180
5.0
10
15
−
−
−
250
130
85
500
260
190
5.0
10
15
−
−
−
175
50
50
360
120
100
5.0
10
15
−
−
−
235
100
80
470
200
160
5.0
10
15
−
−
−
320
145
105
640
290
210
tW(cl)
5.0
10
15
180
80
60
90
40
30
−
−
−
ns
fcl
5.0
10
15
−
−
−
4.0
8.0
10
2.0
4.0
5.0
MHz
Preset Removal Time
The Preset Signal must be low prior to a positive−going
transition of the clock.
trem
5.0
10
15
160
80
60
80
40
30
−
−
−
ns
Clock Rise and Fall Time
tr(cl)
tf(cl)
5.0
10
15
−
−
−
−
−
−
15
5
4
ms
Carry In Setup Time
tsu
5.0
10
15
150
60
40
75
30
20
−
−
−
ns
Up/Down Setup Time
5.0
10
15
340
140
100
170
70
50
−
−
−
ns
Binary/Decade Setup Time
5.0
10
15
320
140
100
160
70
50
−
−
−
ns
5.0
10
15
130
70
50
65
35
25
−
−
−
ns
Clock Pulse Width
Clock Pulse Frequency
Preset Enable Pulse Width
ns
ns
ns
ns
tW
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
www.onsemi.com
4
MC14029B
VDD
Q0
PE
Cin
B/D
U/D
CLK
P0
P1
P2
P3
PULSE
GENERATOR
0.01 mF
CERAMIC
ID
500 pF
Q1
Q2
CL
CL
Q3
CL
Cout
CL
CL
20 ns
20 ns
90%
50%
CLK
10%
VARIABLE
WIDTH
VDD
VSS
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
PE
Cin
B/D
U/D
CLK
P0
P1
P2
P3
PROGRAMMABLE
PULSE
GENERATOR
Q0
Q1
Q2
CL
CL
Q3
CL
CL
Cout
CL
VSS
tW
tsu
CARRY IN OR
UP/DOWN
OR BINARY/DECADE
trem
1/fcl
VDD
50%
CLOCK
VSS
VDD
50%
VSS
VDD
tW
PRESET ENABLE
20 ns
Cout ONLY
90%
10%
Q0 OR CARRY OUT
10%
VSS
tTLH
90%
VOL
tPLH
tTHL
tPHL
tPLH
Figure 2. Switching Time Test Circuit and Waveforms
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5
VOH
MC14029B
TIMING DIAGRAM
CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT 0
1
2
3
4
5
6
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
MSD
PE
B/D
P3 P2 P1 P0 CLK
“1"
7
8
9
8
7
6
5
4
Q3 Q2 Q1 Q0
Cout
Cin
U/D
MC14029B
PE
B/D
P3 P2 P1 P0 CLK
VDD
“2"
3
2
1
0
0
9
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
LSD
PE
B/D
P3 P2 P1 P0 CLK
VDD
VDD VDD
“3"
INPUT
CLOCK
CLOCK
Cout1 (LSD)
Cout2
Cout3 (MSD)
122
123
0
1
9
10
11
99
100
101
119
120
121
122
COUNT
123
PE
*tW ^ 900 ns @ VDD = 5 V
Figure 3. Divide by N BCD Down Counter and Timing Diagram
(Shown for N = 123)
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6
6
7
0
OUTPUT
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7
CLOCK
UP/DOWN
CARRY IN
PRESET ENABLE
BINARY/DECADE
15
10
5
1
9
P0
6
Q0
CLK Q1
CLK Q0
11
P1
TE Q1
PE P1
12
TE Q0
PE P0
4
Q1
P2
14
CLK Q2
TE Q2
PE P2
13
Q2
P3
2
CLK Q3
TE Q3
PE P3
3
Q3
CARRY OUT
7
MC14029B
LOGIC DIAGRAM
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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