MC14094BF

DATA SHEET www.onsemi.com 8-Stage Shift/Store Register with Three-State Outputs SOIC−16 D SUFFIX CASE 751B MC14094B The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in high−speed cascaded systems. The QS output data is shifted on the following negative clock transition for use in low−speed cascaded systems. Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high. Outputs of the eight data latches are controlled by 3−state buffers which are placed in the high−impedance state by a logic Low on Output Enable. Features • 3−State Outputs • Capable of Driving Two Low−Power TTL Loads or One Low−Power • • • • • • • Schottky TTL Load Over the Rated Temperature Range Input Diode Protection Data Latch Dual Outputs for Data Out on Both Positive and Negative Clock Transitions Useful for Serial−to−Parallel Data Conversion Pin−for−Pin Compatible with CD4094B NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant TSSOP−16 DT SUFFIX CASE 948F MARKING DIAGRAMS 16 16 14094BG AWLYWW 1 14 094B ALYWG G 1 SOIC−16 A WL, L YY, Y WW, W G or G TSSOP−16 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 March, 2022 − Rev. 11 1 Publication Order Number: MC14094B/D MC14094B PIN ASSIGNMENT STROBE 1 16 DATA 2 15 CLOCK 3 14 VDD OUTPUT ENABLE Q5 Q1 4 13 Q6 Q2 5 12 Q7 Q3 6 11 Q8 Q4 7 10 Q′S VSS 8 9 QS TRUTH TABLE Clock Parallel Outputs Output Enable Strobe Data Q1 QN 0 X X Z 0 X X Z 1 0 X 1 1 1 1 1 1 Z = High Impedance Serial Outputs QS * Q′S Z Q7 No Chg. Z No Chg. Q7 No Chg. No Chg. Q7 No Chg. 0 0 QN−1 Q7 No Chg. 1 1 QN−1 Q7 No Chg. 1 No Chg. No Chg. No Chg. Q7 X = Don’t Care * At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS. ORDERING INFORMATION Package Shipping† MC14094BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14094BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14094BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel MC14094BDTR2G TSSOP−16 (Pb−Free) 2500 Units / Tape & Reel NLV14094BDTR2G* TSSOP−16 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 2 MC14094B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 3−State Output Leakage Current ITL 15 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink VIH IOH Vdc Vdc mAdc IT = (4.1 mA/kHz) f + IDD IT = (14 mA/kHz) f + IDD IT = (140 mA/kHz) f + IDD − ±0.1 − ±0.0001 ±0.1 mAdc − ±3.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. www.onsemi.com 3 MC14094B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTLH, tTHL = (0.6 ns/pF) CL + 20 ns tTLH, tTHL = (0.4 ns/pF) CL + 20 ns tTLH, tTHL Propagation Delay Time (Figure 1) Clock to Serial out QS tPLH, tPHL = (0.90 ns/pF) CL + 305 ns tPLH, tPHL = (0.36 ns/pF) CL + 107 ns tPLH, tPHL = (0.26 ns/pF) C L + 82 ns tPLH, tPHL VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns 5.0 10 15 − − − 350 125 95 600 250 190 Clock to Serial out Q’S tPLH, tPHL = (0.90 ns/pF) CL + 350 ns tPLH, tPHL = (0.36 ns/pF) CL + 149 ns tPLH, tPHL = (0.26 ns/pF) CL + 62 ns 5.0 10 15 − − − 230 110 75 460 220 150 Clock to Parallel out tPLH, tPHL = (0.90 ns/pF) CL + 375 ns tPLH, tPHL = (0.35 ns/pF) CL + 177 ns tPLH, tPHL = (0.26 ns/pF) CL + 122 ns 5.0 10 15 − − − 420 195 135 840 390 270 Strobe to Parallel out tPLH, tPHL = (0.90 ns/pF) CL + 245 ns tPLH, tPHL = (0.36 ns/pF) C L + 127 ns tPLH, tPHL = (0.26 ns/pF) CL + 87 ns 5.0 10 15 − − − 290 145 100 580 290 200 tPHZ, tPZL 5.0 10 15 − − − 140 75 55 280 150 110 tPLZ, tPZH 5.0 10 15 − − − 225 95 70 450 190 140 Setup Time Data in to Clock tsu 5.0 10 15 125 55 35 60 30 20 − − − ns Hold Time Clock to Data th 5.0 10 15 0 20 20 – 40 – 10 0 − − − ns Clock Pulse Width, High tWH 5.0 10 15 200 100 83 100 50 40 − − − ns Clock Rise and Fall Time tr(cl) tf(cl) 5 10 15 − − − − − − 15 5.0 4.0 ms fcl 5.0 10 15 − − − 2.5 5.0 6.0 1.25 2.5 3.0 MHz tWL 5.0 10 15 200 80 70 100 40 35 − − − ns Output Enable to Output tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns Clock Pulse Frequency Strobe Pulse Width 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. www.onsemi.com 4 MC14094B 3−STATE TEST CIRCUIT FOR tPHZ AND tPZH VSS FOR tPLZ AND tPZL VDD O.E. R1 = 1 k = tPHL, tPLH R1 = 10 k = tPHZ, tPZH, tPLZ, tPZL R1 DATA OUTPUT ST 50 pF CLOCK Figure 1. BLOCK DIAGRAM REGISTER STAGE 1 CLOCK 2 CLOCK STROBE VDD CLOCK CLOCK STROBE STROBE CLOCK CLOCK STROBE 4 Q1 * 2 OUTPUT ENABLE 3 4 5 6 7 8 REGISTER STAGE 2 LATCH 2 3-STATE BUFFER2 5 Q2 REGISTER STAGE 3 LATCH 3 3-STATE BUFFER3 6 Q3 REGISTER STAGE 4 LATCH 4 3-STATE BUFFER4 7 Q4 REGISTER STAGE 5 LATCH 5 3-STATE BUFFER5 14 Q5 REGISTER STAGE 6 LATCH 6 3-STATE BUFFER6 13 Q6 REGISTER STAGE 7 LATCH 7 3-STATE BUFFER7 12 Q7 LATCH 8 3-STATE BUFFER8 11 Q8 10 Q′S 9 QS REGISTER STAGE 8 CLOCK 3 3-STATE BUFFER 1 * SERIAL DATA IN 15 LATCH 1 * STROBE STROBE CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK 1 * STROBE STROBE *Input Protection Diodes CLOCK STROBE www.onsemi.com 5 MC14094B DYNAMIC TIMING DIAGRAM tWH 3 tf tr CLOCK 50% 90% 50% 10% tsu 2 th DATA IN tWL 1 STROBE 15 OUTPUT ENABLE 50% tPLH N Q1 ³ Q7 tPHL 9 QS tPHZ 90% 90% tTHL tPLZ tPZL 90% 10% 10% tPHL tPLH 50% 50% tPLH 10 Q′S tPZH 90% 10% 10% tTLH tPLH 50% 50% tPHL 50% www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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