MC14503BFELG

MC14503B Hex Non-Inverting 3-State Buffer The MC14503B is a hex non−inverting buffer with 3−state outputs, and a high current source and sink capability. The 3−state outputs make it useful in common bussing applications. Two disable controls are provided. A high level on the Disable A input causes the outputs of buffers 1 through 4 to go into a high impedance state and a high level on the Disable B input causes the outputs of buffers 5 and 6 to go into a high impedance state. http://onsemi.com 1 SOIC−16 D SUFFIX CASE 751B Features • 3−State Outputs • TTL Compatible − Will Drive One TTL Load Over Full Temperature • • • • • Range Supply Voltage Range = 3.0 Vdc to 18 Vdc Two Disable Controls for Added Versatility Pin for Pin Replacement for MM80C97 and 340097 NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant PIN ASSIGNMENT MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1) Symbol Value Unit VDD −0.5 to +18.0 V Vin, Vout −0.5 to VDD + 0.5 V Input Current (DC or Transient) per Pin Iin ±10 mA Output Current (DC or Transient) per Pin Iout ±25 mA Power Dissipation, per Package (Note 2) PD 500 mW Ambient Temperature Range TA −55 to +125 °C −65 to +150 °C 260 °C Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Storage Temperature Range Lead Temperature (8−Second Soldering) DIS A 1 16 VDD IN 1 2 15 DIS B OUT 1 3 14 IN 6 IN 2 4 13 OUT 6 OUT 2 5 12 IN 5 IN 3 6 11 OUT 5 OUT 3 7 10 IN 4 VSS 8 9 OUT 4 MARKING DIAGRAM 16 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 14503BG AWLYWW 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package TRUTH TABLE Inn Appropriate Disable Input Outn 0 0 0 1 0 1 X 1 High Impedance X = Don’t Care ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 10 1 Publication Order Number: MC14503B/D MC14503B LOGIC DIAGRAM DISABLE B IN 5 IN 6 15 ONE OF TWO/FOUR BUFFERS 12 11 14 13 2 3 4 5 6 7 10 9 IN 1 IN 2 IN 3 IN 4 CIRCUIT DIAGRAM 1 DISABLE A VDD OUT 5 OUT 6 *INn OUT 1 OUTn OUT 2 OUT 3 *DISABLE *INPUT OUT 4 VSS TO OTHER BUFFERS VDD = PIN 16 VSS = PIN 8 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ *Diode protection on all inputs (not shown) ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C VDD 125_C Symbol Vdc Min Max Min Typ (Note 3) Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 4.5 5.0 5.0 10 15 –4.3 –5.8 –1.2 –3.1 –8.2 − − − − − –3.6 –4.8 –1.02 –2.6 –6.8 –5.0 –6.1 –1.4 –3.7 –14.1 − − − − − –2.5 –3.0 –0.7 –1.8 –4.8 − − − − − IOL 4.5 5.0 10 15 2.2 2.6 6.5 19.2 − − − − 1.8 2.1 5.5 16.1 2.1 2.3 6.2 25 − − − − 1.2 1.3 3.8 11.2 − − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance, (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current, (Per Package) IQ 5.0 10 15 − − − 1.0 2.0 4.0 − − − 0.002 0.004 0.006 1.0 2.0 4.0 − − − 30 60 120 mAdc Total Supply Current (Note 4, 5) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs) (All outputs switching, 50% Duty Cycle) IT 3−State Output Leakage Current ITL Characteristic Output Voltage Vin = 0 Vin = VDD Input Voltage (VO = 3.6 or 1.4 Vdc) (VO = 7.2 or 2.8 Vdc) (VO = 11.5 or 3.5 Vdc) “1” Level VIH (VO = 1.4 or 3.6 Vdc) (VO = 2.8 or 7.2 Vdc) (VO = 3.5 or 11.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Source (VOL = 0.4 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink Vdc Vdc IOH mAdc 5.0 IT = (2.5 mA/kHz) f + IDD 10 15 IT = (6.0 mA/kHz) f + IDD IT = (10 mA/kHz) f + IDD 15 ±0.1 − − ±0.0001 ±0.1 mAdc − ±3.0 mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006. http://onsemi.com 2 MC14503B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol VDD VCC Typ (Note 7) Max 5.0 10 15 45 23 18 90 45 35 5.0 10 15 45 23 18 90 45 35 5.0 10 15 75 35 25 150 70 50 5.0 10 15 75 35 25 150 70 50 Unit Output Rise Time tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.3 ns/pF) CL + 8.0 ns tTLH = (0.2 ns/pF) CL + 8.0 ns tTLH ns Output Fall Time tTHL = (0.5 ns/pF) CL + 20 ns tTHL = (0.3 ns/pF) CL + 8.0 ns tTHL = (0.2 ns/pF) CL + 8.0 ns tTHL Turn−Off Delay Time, all Outputs tPLH = (0.3 ns/pF) CL + 60 ns tPLH = (0.15 ns/pF) CL + 27 ns tPLH = (0.1 ns/pF) CL + 20 ns tPLH Turn−On Delay Time, all Outputs tPHL = (0.3 ns/pF) CL + 60 ns tPHL = (0.15 ns/pF) CL + 27 ns tPHL = (0.1 ns/pF) CL + 20 ns tPHL 3−State Propagation Delay Time Output “1” to High Impedance tPHZ 5.0 10 15 75 40 35 150 80 70 ns Output “0” to High Impedance tPLZ 5.0 10 15 80 40 35 160 80 70 ns High Impedance to “1” Level tPZH 5.0 10 15 65 25 20 130 50 40 ns High Impedance to “0” Level tPZL 5.0 10 15 100 35 25 200 70 50 ns ns ns ns 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. DISABLE INPUT 20 ns 20 ns VDD 90% VDD 16 50% INPUT INPUT OUTPUT VSS 90% OUTPUT CL tTLH tPLH Figure 1. Switching Time Test Circuit and Waveforms (tTLH, tTHL, tPHL, and tPLH) http://onsemi.com 3 VSS tPHL tPLH PULSE GENERATOR 10% VOH 50% 10% VOL tTHL tPHL MC14503B DISABLE INPUT DISABLE INPUT PULSE GENERATOR tPLZ, tPZL CIRCUIT PULSE GENERATOR VDD VDD 16 tPHZ, tPZH CIRCUIT 16 INPUT OUTPUT 1k 8 VSS OUTPUT INPUT CL 8 20 ns VSS CL 20 ns VDD 90% 50% DISABLE INPUT 1k 10% tPZL tPLZ VOH 90% 10% OUTPUT FOR tPZH, tPZL CIRCUIT VSS ≈ VOL + 0.05 V tPHZ tPZH OUTPUT FOR tPHZ, tPLZ CIRCUIT ≈ VOH - 0.15 V 90% 10% VOL Figure 2. 3−State AC Test Circuit and Waveforms (tPLZ, tPHZ, tPZH, tPZL) ORDERING INFORMATION Package Shipping† MC14503BDG SOIC−16 (Pb−Free) 48 / Rail MC14503BDR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel NLV14503BDR2G* SOIC−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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