MC14521BCPG

MC14521B 24-Stage Frequency Divider The MC14521B consists of a chain of 24 flip−flops with an input circuit that allows three modes of operation. The input will function as a crystal oscillator, an RC oscillator, or as an input buffer for an external oscillator. Each flip−flop divides the frequency of the previous flip−flop by two, consequently this part will count up to 224 = 16,777,216. The count advances on the negative going edge of the clock. The outputs of the last seven−stages are available for added flexibility. http://onsemi.com Features • All Stages are Resettable • Reset Disables the RC Oscillator for Low Standby Power Drain • RC and Crystal Oscillator Outputs Are Capable of Driving External • • • • • • Loads Test Mode to Reduce Test Time VDD′ and VSS′ Pins Brought Out on Crystal Oscillator Inverter to Allow the Connection of External Resistors for Low−Power Operation Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load over the Rated Temperature Range NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant 1 SOIC−16 D SUFFIX CASE 751B PIN ASSIGNMENT Q24 1 16 VDD RESET 2 15 Q23 VSS4 3 14 Q22 OUT 2 4 13 Q21 VDD4 5 12 Q20 IN 2 6 11 Q19 OUT1 7 10 Q18 VSS 8 9 IN 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Value Unit VDD −0.5 to +18.0 V Vin, Vout −0.5 to VDD +0.5 V Input or Output Current (DC or Transient) per Pin Iin, Iout ±10 mA 1 Power Dissipation, per Package (Note 1) PD 500 mW Ambient Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8−Second Soldering) TL 260 °C A WL, L YY, Y WW, W G Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 10 1 MARKING DIAGRAMS 16 14521BG AWLYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: MC14521B/D MC14521B BLOCK DIAGRAM RESET 2 9 IN 1 STAGES 1 THRU 17 6 IN 2 7 OUT 1 5 VDD′ 3 VSS′ 4 OUT2 STAGES 18 THRU 24 Q18 Q19 Q20 Q21 Q22 Q23 Q24 VDD = PIN 16 VSS = PIN 8 10 11 12 13 14 15 1 Output Count Capacity Q18 Q19 Q20 Q21 Q22 Q23 Q24 218 = 262,144 219 = 524,288 220 = 1,048,576 221 = 2,097,152 222 = 4,194,304 223 = 8,388,608 224 = 16,777,216 ORDERING INFORMATION Package Shipping† MC14521BDG SOIC−16 (Pb−Free) 48 Units / Rail NLV14521BDG* SOIC−16 (Pb−Free) 48 Units / Rail MC14521BDR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel NLV14521BDR2G* SOIC−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14521B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C VDD Characteristic Output Voltage Vin = VDD or 0 “0” Level “1” Level Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) 125_C Symbol Vdc Min Max Min Typ (Note 2) Max Min Max Unit VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 10 15 –0.25 –0.62 –1.8 − − − –0.2 –0.5 –1.5 –0.36 –0.9 –3.5 − − − –0.14 –0.35 –1.1 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − mAdc VIL Vdc VIH Vdc Output Drive Current (VOH = 4.5 Vdc) Source (VOH = 9.0 Vdc) Pin 4 (VOH = 13 Vdc) (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) Pins 1, 7, 10, (VOH = 9.5 Vdc) 11, 12, 13, 14 and 15 (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (0.42 mA/kHz) f + IDD IT = (0.85 mA/kHz) f + IDD IT = (1.40 mA/kHz) f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003. http://onsemi.com 3 MC14521B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time (Counter Outputs) tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns tTLH, tTHL Propagation Delay Time Clock to Q18 tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns Clock to Q24 tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns tPHL, tPLH Propagation Delay Time Reset to Qn tPHL = (1.7 ns/pF) CL + 1215 ns tPHL = (0.66 ns/pF) CL + 467 ns tPHL = (0.5 ns/pF) CL + 350 ns VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ms 5.0 10 15 − − − 4.5 1.7 1.3 9.0 3.5 2.7 5.0 10 15 − − − 6.0 2.2 1.7 12 4.5 3.5 tPHL 5.0 10 15 − − − 1300 500 375 2600 1000 750 tWH(cl) 5.0 10 15 385 150 120 140 55 40 − − − ns fcl 5.0 10 15 − − − 3.5 9.0 12 2.0 5.0 6.5 MHz tTLH, tTHL 5.0 10 15 − − − − − − 15 5.0 4.0 ms tWH(R) 5.0 10 15 1400 600 450 700 300 225 − − − ns trem 5.0 10 15 30 0 – 40 –200 –160 –110 − − − ns Clock Pulse Width Clock Pulse Frequency Clock Rise and Fall Time ns Reset Pulse Width Reset Removal Time 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD 500 mF VDD PULSE GENERATOR 0.01 mF CERAMIC ID IN 2 R VSS VDD Q18 Q19 Q20 Q21 Q22 Q23 Q24 CL CL Vin CL 20 ns 90% 50% 10% 50% DUTY CYCLE CL CL CL CL VSS Figure 1. Power Dissipation Test Circuit and Waveform http://onsemi.com 4 20 ns VDD 0V MC14521B VDD VDD′ VDD PULSE GENERATOR IN 2 R 20 ns CL CL tWL CL CL Qn CL 50% 20 ns 90% 50% 10% CL VSS′ VSS 20 ns IN 2 Q18 Q19 Q20 Q21 Q22 Q23 Q24 tWH 90% 10% tPLH tTLH CL tPHL tTHL Figure 2. Switching Time Test Circuit and Waveforms 500 kHz Circuit 50 kHz Circuit Unit Crystal Characteristics Resonant Frequency Equivalent Resistance, RS 500 1.0 50 6.2 kHz kW External Resistor/Capacitor Values Ro CT CS 47 82 20 750 82 20 kW pF pF + 6.0 + 2.0 + 2.0 + 2.0 ppm ppm – 4.0 + 100 – 2.0 + 120 ppm ppm – 2.0 – 160 – 2.0 – 560 ppm ppm Characteristic VDD Ro 18 M CS CT VDD R* VDD′ IN 1 OUT 1 OUT 2 Q18 Q19 IN 2 Q20 Q21 Q22 Q23 R Q24 VSS VSS′ R* *Optional for low power operation, 10 kW ≤ R ≤ 70 kW. Figure 3. Crystal Oscillator Circuit Frequency Stability Frequency Change as a Function of VDD (TA = 25_C) VDD Change from 5.0 V to 10 V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature (VDD = 10 V) TA Change from – 55_C to + 25_C MC14521 only Complete Oscillator* TA Change from + 25_C to + 125_C MC14521 only Complete Oscillator* ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ *Complete oscillator includes crystal, capacitors, and resistors. Figure 4. Typical Data for Crystal Oscillator Circuit http://onsemi.com 5 MC14521B 100 FREQUENCY DEVIATION (%) VDD = 15 V 4.0 f, OSCILLATOR FREQUENCY (kHz) 8.0 TEST CIRCUIT FIGURE 7 0 10 V -4.0 -8.0 5.0 V -12 f AS A FUNCTION OF RTC (C = 1000 pF) (RS ≈ 2RTC) 20 10 5.0 2.0 1.0 TEST CIRCUIT FIGURE 7 VDD = 10 V 50 f AS A FUNCTION OF C (RTC = 56 kW) (RS = 120 k) 0.5 0.2 RTC = 56 kW, C = 1000 pF -16 -55 { RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C 0.1 1.0 k -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY 0.0001 Figure 5. RC Oscillator Stability RS RTC 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (mF) 125 1.0 m 0.1 Figure 6. RC Oscillator Frequency as a Function of RTC and C VDD VDD C VDD′ VDD IN 1 IN 2 R VDD′ IN 1 OUT 1 OUT 2 Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS Q18 Q19 Q20 Q21 IN 2 Q22 Q23 Q24 OUT 1 R OUT 2 PULSE GENERATOR VSS VSS′ Figure 7. RC Oscillator Circuit VSS Figure 8. Functional Test Circuit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ FUNCTIONAL TEST SEQUENCE Inputs A test function (see Figure 8) has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8−stage sections, and 255 counts are loaded in each of the 8−stage sections in parallel. All flip−flops are now at a logic “1”. The counter is now returned to the normal 24−stages in series configuration. One more pulse is entered into Input 2 (In 2) which will cause the counter to ripple from an all “1” state to an all “0” state. Outputs Comments Reset In 2 Out 2 VSS′ VDD′ Q18 thru Q24 1 0 0 VDD GND 0 0 1 1 First “0” to “1” transition on In 2, Out 2 node. 0 1 − − − 0 1 − − − 255 “0” to “1” transitions are clocked into this In 2, Out 2 node. 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 GND http://onsemi.com 6 VDD Counter is in three 8−stage sections in parallel mode Counter is reset. In 2 and Out 2 are connected together. The 255th “0” to “1” transition. 1 Counter converted back to 24−stages in series mode. 1 Out 2 converts back to an output. 0 Counter ripples from an all “1” state to an all “0” stage. MC14521B LOGIC DIAGRAM VDD 5 RESET 2 9 1 2 IN 1 3 VSS 9 17 18 19 10 Q18 8 4 OUT 2 6 IN 2 7 OUT 1 STAGES 3 THRU 7 20 11 Q19 21 12 Q20 22 10 23 13 Q21 14 Q22 16 24 15 Q23 http://onsemi.com 7 STAGES 11 THRU 15 1 Q24 VDD = PIN 16 VSS = PIN 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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