MC14528BCPG

MC14528B Dual Monostable Multivibrator The MC14528B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an output pulse over a wide range of widths, the duration of which is determined by the external timing components, CX and RX. http://onsemi.com Features • • • • • • • • Separate Reset Available Diode Protection on All Inputs Triggerable from Leading or Trailing Edge Pulse Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range This part should only be used in new designs where the pulse width is < 10 s Note: For designs requiring a pulse width > 10 s, please see MC14538, which is pin−for−pin compatible NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Value Unit VDD −0.5 to +18.0 V Vin, Vout −0.5 to VDD + 0.5 V Iin, Iout ± 10 mA Power Dissipation, per Package (Note 1) PD 500 mW Ambient Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8−Second Soldering) TL 260 °C Rating DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 9 1 1 SOIC−16 D SUFFIX CASE 751B PIN ASSIGNMENT VSS 1 16 VDD CX1/RX1 2 15 VSS RESET 1 3 14 CX2/RX2 A1 4 13 RESET 2 B1 5 12 A2 Q1 6 11 B2 Q1 7 10 Q2 VSS 8 9 Q2 MARKING DIAGRAM 14528BG AWLYWW 1 A WL YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: MC14528B/D MC14528B ONE−SHOT SELECTION GUIDE 1 s 100 ns 10 s 100 s 1 ms 10 ms 100 ms 1s 10 s MC14528B MC14536B MC14538B MC14541B 23 HR 5 MIN MC4538A* *LIMITED OPERATING VOLTAGE (2-6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE BLOCK DIAGRAM CX 1 1 RX 2 VDD VDD 2 15 6 4 A1 5 B1 RESET 1 CX 2 RX 1 7 10 12 A2 11 B2 Q1 Q1 3 RESET 2 9 13 VDD = PIN 16 VSS = PIN 1, PIN 8, PIN 15 RX AND CX ARE EXTERNAL COMPONENTS FUNCTION TABLE Outputs Inputs Reset A H H L H H H H H L B Q Q H L Not Triggered Not Triggered L, H, L H L, H, Not Triggered Not Triggered X X X X L H Not Triggered http://onsemi.com 2 14 Q2 Q2 MC14528B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C VDD 125_C Symbol Vdc Min Max Min Typ (Note 2) Max Min Max Unit VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − IOH 5.0 5.0 10 15 –1.2 –0.64 –1.6 –4.2 − − − − –1.0 –0.51 –1.3 –3.4 –1.7 –0.88 –2.25 –8.8 − − − − –0.7 –0.36 –0.9 –2.4 − − − − 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 Adc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 Adc Characteristic Output Voltage Vin = VDD or 0 “0” Level “1” Level Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL Vdc Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) mAdc Source Sink Total Supply Current at an external load Capacitance (CL) and at external timing capacitance (CX), use the formula. (Note 3) − IT IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x10−8 RXCX(VDD−2)2f] x 10−3 where: IT in A (per circuit), CL and CX in pF, RX in megohms, VDD in Vdc, f in kHz is input frequency. Adc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. http://onsemi.com 3 MC14528B SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) (Note 4) Characteristic Symbol CX pF RX k − VDD Vdc Min Typ (Note 5) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 325 120 90 650 240 180 5.0 10 15 − − − 705 290 210 − − − Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL − ns Turn−Off, Turn−On Delay Time — A or B to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 240 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns tPLH, tPHL 15 Turn−Off, Turn−On Delay Time — A or B to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 620 ns tPLH, tPHL = (0.66 ns/pF) CL + 257 ns tPLH, tPHL = (0.5 ns/pF) CL + 185 ns tPLH, tPHL 1000 Input Pulse Width — A or B tWH 15 5.0 5.0 10 15 150 75 55 70 30 30 − − − ns 1000 10 5.0 10 15 − − − 70 30 30 − − − ns 5.0 ns 10 tWL ns Output Pulse Width — Q or Q (For CX < 0.01 F use graph for appropriate VDD level.) tW 15 5.0 5.0 10 15 − − − 550 350 300 − − − ns Output Pulse Width — Q or Q (For CX > 0.01 F use formula: tW = 0.2 RX CX Ln [VDD – VSS]) (Note 6) tW 10,000 10 5.0 10 15 15 10 15 30 50 55 45 90 95 s t1 – t2 10,000 10 5.0 10 15 − − − 6.0 8.0 8.0 25 35 35 % 15 5.0 5.0 10 15 − − − 325 90 60 600 225 170 ns 1000 10 5.0 10 15 − − − 1000 300 250 − − − ns 15 5.0 5.0 10 15 0 0 0 − − − − − − ns 1000 10 5.0 10 15 0 0 0 − − − − − − ns 5.0 − 1000 k Pulse Width Match between Circuits in the same package Reset Propagation Delay — Reset to Q or Q tPLH, tPHL Retrigger Time trr External Timing Resistance RX − − − External Timing Capacitance CX − − − 4. 5. 6. 7. No Limits (Note 7) The formulas given are for the typical characteristics only at 25_C. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. If CX > 15 F, Use Discharge Protection Diode DX, per Figure 9. RXis in , CX is in farads, VDD and VSS in volts, PWout in seconds. http://onsemi.com 4 F MC14528B ORDERING INFORMATION Package Shipping† MC14528BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14528BDR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel NLV14528BDR2G* SOIC−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. VDD 16 VDD 16 IOL A B A OPEN Q Q RESET IOH VSS 8 VOL B VOH RESET Q 8 Figure 1. Output Source Current Test Circuit Q OPEN VSS Figure 2. Output Sink Current Test Circuit VDD 500 pF 0.1 F CERAMIC ID RX RX ′ CX ′ CX 20 ns 20 ns Vin 90% VDD A Q B Vin 10% CL RESET DUTY CYCLE = 50% Q CL A′ Q′ B′ Q′ CL CL RESET′ VSS Figure 3. Power Dissipation Test Circuit and Waveforms http://onsemi.com 5 0V MC14528B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD *CX = 15 pF *CL = 15 pF RX = 5.0 k RX ′ RX CX ′ CX INPUT CONNECTIONS A PULSE GENERATOR B Q RESET Q CL PULSE GENERATOR Q′ B′ Q′ CL RESET′ A B tPLH, tPHL, tTLH, tTHL, tW VDD PG1 VDD tPLH, tPHL, tTLH, tTHL, tW VDD VSS PG2 tPLH(R), tPHL(R), tW PG3 PG1 PG2 PG1 = NOTE: AC test waveforms for PG1, PG2, and PG3 on next page. CL PULSE GENERATOR Reset *Includes capacitance of probes, wiring, and fixture parasitic. CL A′ Characteristics PG2 = PG3 = VSS Figure 4. AC Test Circuit A tTLH tWH VDD 90% 10% tTHL 50% 50% tTHL B VSS tTLH VDD 90% 10% 50% VSS tWL tTHL RESET tTLH 90% 10% tTHL tW 50% tPLH 50% 50% Q VSS tWL tTLH 90% 10% trr tPHL VOH 50% tTLH tPHL VDD 50% VOL tTHL tPHL tPHL Q 50% 50% VOH 90% 10% 50% 50% Figure 5. AC Test Waveforms 1000 VDD = 15 V t W, PULSE WIDTH (  s) 10 V 5.0 V 100 15 V 10 V 5.0 V RX = 100 k 15 V 10 V 5.0 V 10 RX = 10 k RX = 5.0 k 1.0 0.1 15 V 10 V 5.0 V 10 100 1000 10,000 CX, EXTERNAL CAPACITANCE (pF) Figure 6. Pulse Width versus CX http://onsemi.com 6 100,000 VOL MC14528B TYPICAL APPLICATIONS Cx Cx Rx Rx VDD VDD RISING EDGE TRIGGER A Q B Q RESET VDD RISING EDGE TRIGGER A Q B Q RESET VDD VDD Cx Cx Rx Rx VDD VDD FALLING EDGE TRIGGER A Q B Q RESET FALLING EDGE TRIGGER A Q B Q RESET VDD VDD Figure 7. Retriggerable Monostables Circuitry Figure 8. Non−Retriggerable Monostables Circuitry DX Cx VDD NC 1, 15 Rx 2, 14 VDD Q NC Q RESET NC A Q B VDD Q RESET VDD VDD Figure 9. Use of a Diode to Limit Power Down Current Surge VDD Figure 10. Connection of Unused Sections ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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