MC14551B
Quad 2-Channel Analog
Multiplexer/Demultiplexer
The MC14551B is a digitally−controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
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Features
MARKING
DIAGRAMS
• Triple Diode Protection on All Control Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (VDD − VEE) = 3.0 to 18 V
•
•
•
•
•
16
Note: VEE must be v VSS
Linearized Transfer Characteristics
Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical
For Low RON, Use The HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
Switch Function is Break Before Make
These Devices are Pb−Free and are RoHS Compliant
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PDIP−16
P SUFFIX
CASE 648
1
MC14551BCP
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
1
14551BG
AWLYWW
1
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VDD
– 0.5 to + 18.0
V
Vin, Vout
– 0.5 to VDD
+ 0.5
V
Input Current (DC or Transient),
per Control Pin
Iin
± 10
mA
Switch Through Current
Isw
± 25
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
– 55 to + 125
_C
Storage Temperature Range
Tstg
– 65 to + 150
_C
TL
260
DC Supply Voltage Range
(Referenced to VEE, VSS ≥ VEE)
Input or Output Voltage (DC or Transient)
(Referenced to VSS for Control Input and
VEE for Switch I/O)
Lead Temperature (8–Second Soldering)
_C
16
SOEIAJ−16
F SUFFIX
CASE 966
1
MC14551B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: − 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD for control inputs and VEE ≤ (Vin or Vout)
≤ VDD for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS, VEE or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1
Publication Order Number:
MC14551B/D
MC14551B
PIN ASSIGNMENT
W1
1
16
VDD
X0
2
15
W0
X1
3
14
W
X
4
13
Z
Y
5
12
Z1
Y0
6
11
Z0
VEE
7
10
Y1
VSS
8
9
9
SWITCHES
IN/OUT
CONTROL
VDD = Pin 16
VSS = Pin 8
VEE = Pin 7
15
1
2
3
6
10
11
12
CONTROL
W
W0
W1
X0
X1
Y0
Y1
Z0
Z1
Control
ON
0
W0 X0 Y0 Z0
1
W1 X1 Y1 Z1
X
14
4
COMMONS
OUT/IN
Y
5
Z
13
NOTE: Control Input referenced to VSS, Analog Inputs and
Outputs reference to VEE. VEE must be v VSS.
ORDERING INFORMATION
Package
Shipping†
MC14551BCPG
PDIP−16
(Pb−Free)
25 Units / Rail
MC14551BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14551BDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
SOEIAJ−16
(Pb−Free)
50 Units / Rail
Device
MC14551BFG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14551B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
– 55_C
Characteristic
VDD
Test Conditions
125_C
25_C
Symbol
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage
Range
−
VDD – 3.0 ≥ VSS ≥ VEE
VDD
3.0
18
3.0
−
18
3.0
18
V
Quiescent Current Per
Package
5.0
10
15
Control Inputs: Vin =
VSS or VDD,
Switch I/O: VEE v VI/O
v VDD, and DVswitch v
500 mV (Note 3 )
IDD
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
Total Supply Current
(Dynamic Plus Quiescent,
Per Package)
5.0
10
15
TA = 25_C only (The
channel component,
(Vin – Vout)/Ron, is
not included.)
ID(AV)
Typical
mA
(0.07 mA/kHz) f + IDD
(0.20 mA/kHz) f + IDD
(0.36 mA/kHz) f + IDD
CONTROL INPUT (Voltages Referenced to VSS)
Low−Level Input Voltage
5.0
10
15
Ron = per spec,
Ioff = per spec
VIL
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
High−Level Input Voltage
5.0
10
15
Ron = per spec,
Ioff = per spec
VIH
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
V
Input Leakage Current
15
Vin = 0 or VDD
Iin
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mA
Input Capacitance
−
Cin
−
−
−
5.0
7.5
−
−
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)
Recommended Peak−to−
Peak Voltage Into or Out
of the Switch
−
Channel On or Off
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 3)
−
Channel On
Output Offset Voltage
−
VI/O
0
VDD
0
−
VDD
0
VDD
Vp–p
DVswitch
0
600
0
−
600
0
300
mV
Vin = 0 V, No Load
VOO
−
−
−
10
−
−
−
mV
DVswitch v 500 mV
(Note 3),
Vin = VIL or VIH
(Control), and Vin = 0 to
VDD (Switch)
Ron
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
DRon
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
Ioff
−
± 100
−
± 0.05
± 100
−
± 1000
nA
CI/O
−
−
−
10
−
−
−
pF
CO/I
−
−
−
17
−
−
−
pF
CI/O
−
−
−
−
−
−
0.15
0.47
−
−
−
−
−
−
pF
ON Resistance
5.0
10
15
DON Resistance Between
Any Two Channels
in the Same Package
5.0
10
15
Off−Channel Leakage
Current (Figure 8)
15
Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
−
Switch Off
Capacitance, Common O/I
−
Capacitance, Feedthrough
(Channel Off)
−
−
Pins Not Adjacent
Pins Adjacent
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14551B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE v VSS)
Characteristic
Symbol
Propagation Delay Times
Switch Input to Switch Output (RL = 10 kW)
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns
tPLH, tPHL
Control Input to Output (RL = 10 kW)
VEE = VSS (Figure 4)
tPLH, tPHL
VDD – VEE
Vdc
Min
Max
−
5.0
10
15
Second Harmonic Distortion
RL = 10 kW, f = 1 kHz, Vin = 5 Vp−p
Typ
(Note 4 )
5.0
10
15
−
Unit
ns
35
15
12
90
40
30
350
140
100
875
350
250
ns
−
10
−
0.07
−
%
BW
10
−
17
−
MHz
Off Channel Feedthrough Attenuation, Figure 5
RL = 1 kW, Vin = 1/2 (VDD − VEE) p−p, fin = 55 MHz
−
10
−
– 50
−
dB
Channel Separation (Figure 6)
RL = 1 kW, Vin = 1/2 (VDD − VEE) p−p, fin = 3 MHz
−
10
−
– 50
−
dB
Crosstalk, Control Input to Common O/I, Figure 7
R1 = 1 kW, RL = 10 kW, Control tr = tf = 20 ns
−
10
−
75
−
mV
Bandwidth (Figure 5)
RL = 1 kW, Vin = 1/2 (VDD − VEE) p−p,
20 Log (Vout / Vin) = − 3 dB, CL = 50 pF
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14551B
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic
16
CONTROL9
VDD
LEVEL
CONVERTER
8
VSS
7
CONTROL
VEE
W015
14W
W11
X02
4X
X13
Y06
5Y
Y110
Z011
13Z
Z112
Figure 2. MC14551B Functional Diagram
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5
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
PULSE
GENERATOR
CONTROL
Vout
LOAD
V
RL
CL
SOURCE
VDD VEE
VEE VDD
Figure 4. Propagation Delay Times,
Control to Output
Figure 3. DV Across Switch
Control input used to turn ON or OFF the switch under test.
RL
ON
CONTROL
Vout
RL
CONTROL
OFF
CL = 50 pF
Vout
RL
CL = 50 pF
Vin
VDD - VEE
2
Vin
VDD - VEE
2
Figure 5. Bandwidth and Off−Channel
Feedthrough Attenuation
Figure 6. Channel Separation
(Adjacent Channels Used for Setup)
OFF CHANNEL UNDER TEST
VDD
CONTROL
CONTROL
SECTION
OF IC
Vout
RL
VEE
OTHER
CHANNEL(S)
CL = 50 pF
VEE
VDD
R1
VEE
VDD
Figure 7. Crosstalk, Control Input
to Common O/I
Figure 8. Off Channel Leakage
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kW
RANGE
VDD
VEE = VSS
Figure 9. Channel Resistance (RON) Test Circuit
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6
X/Y
PLOTTER
MC14551B
350
300
300
250
200
150
TA = 125°C
100
25°C
- 55°C
50
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0
RON, “ON” RESISTANCE (OHMS)
RON, “ON” RESISTANCE (OHMS)
350
0
2.0
4.0
6.0
8.0
250
200
150
TA = 125°C
100
25°C
- 55°C
50
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0
10
0
2.0
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V
Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V
700
350
600
300
RON, “ON” RESISTANCE (OHMS)
RON, “ON” RESISTANCE (OHMS)
TYPICAL RESISTANCE CHARACTERISTICS
500
400
300
TA = 125°C
200
25°C
100
- 55°C
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0
0
2.0
4.0
6.0
8.0
TA = 25°C
VDD = 2.5 V
250
200
150
5.0 V
100
7.5 V
50
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0
10
0
2.0
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V
Figure 13. Comparison at 25_C, VDD @ – VEE
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7
10
10
MC14551B
APPLICATIONS INFORMATION
Figure A illustrates use of the on−chip level converter
detailed in Figure 2. The 0−to−5.0 V Digital Control signal is
used to directly control a 9 Vp−p analog signal.
The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, VDD = + 5.0 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD
and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage determines
the maximum swing below VSS. For the example, VDD – VSS
= 5.0 V maximum swing above VSS; VSS – VEE = 5.0 V
maximum swing below VSS. The example shows a ± 4.5 V
signal which allows a 1/2 V margin at each peak. If voltage
transients above VDD and/or below VEE are anticipated on the
analog channels, external diodes (Dx) are recommended as
shown in Figure B. These diodes should be small signal types
able to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between VDD
and VEE is 18 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
VDD and VEE.
Balanced supplies are not required. However, VSS must be
greater than or equal to VEE. For example, VDD = + 10 V, VSS
= + 5.0 V, and VEE = – 3.0 V is acceptable. See the table below.
+5 V
-5 V
VDD
+5 V
9 Vp-p
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
VSS
SWITCH
I/O
VEE
+ 4.5 V
COMMON
O/I
9 Vp-p
GND
ANALOG SIGNAL
MC14551B
0-TO-5 V DIGITAL
- 4.5 V
CONTROL
CONTROL SIGNAL
Figure A. Application Example
VDD
VDD
Dx
Dx
SWITCH
I/O
COMMON
O/I
Dx
Dx
VEE
VEE
Figure B. External Schottky or Germanium Clipping Diodes
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
VDD
In Volts
VSS
In Volts
VEE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
Maximum Analog Signal Range
In Volts
+8
0
–8
+ 8/0
+ 8 to – 8 = 16 Vp–p
+5
0
– 12
+ 5/0
+ 5 to – 12 = 17 Vp–p
+5
0
0
+ 5/0
+ 5 to 0 = 5 Vp–p
+5
0
–5
+ 5/0
+ 5 to – 5 = 10 Vp–p
–5
+ 10/ + 5
+ 10 to – 5 = 15 Vp–p
+ 10
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8
MC14551B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOEIAJ−16
CASE 966−01
ISSUE A
16
LE
9
Q1
E HE
1
M_
L
8
Z
DETAIL P
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
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9
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
MC14551B
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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