MC1489, MC1489A
Quad Line EIA-232D
Receivers
The MC1489 monolithic quad line receivers are designed to
interface data terminal equipment with data communications
equipment in conformance with the specifications of EIA Standard
No. EIA−232D.
http://onsemi.com
Features
•
•
•
•
•
Input Resistance − 3.0 k to 7.0 kW
Input Signal Range − ± 30 V
Input Threshold Hysteresis Built In
Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
Pb−Free Packages are Available
SOIC−14
D SUFFIX
CASE 751A
14
1
PDIP−14
P SUFFIX
CASE 646
14
1
SOEIAJ−14
M SUFFIX
CASE 965
14
1
PIN CONNECTIONS
Interconnecting
Cable
Line Driver
MC1488
DTL Logic Input
Interconnecting
Cable
Line Receiver
MC1489
DTL Logic Output
Input A
1
14 VCC
Response
Control A
2
13 Input D
Output A
3
12 Response
Control D
Input B
4
11 Output D
Response
Control B
5
10 Input C
Output B
6
9
Response
Control C
Ground
7
8
Output C
Figure 1. Simplified Application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 11
1
Publication Order Number:
MC1489/D
MC1489, MC1489A
14
VCC
9.0 k
5.0 k
1.7 k
RF
Response Control 2
3 Output
3.8 k
Input 1
RF
MC1489
MC1489A
6.7 kW
1.6 kW
10 k
7 GND
Figure 2. Representative Schematic Diagram
(1/4 of Circuit Shown)
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2
MC1489, MC1489A
MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
10
Vdc
Input Voltage Range
VIR
± 30
Vdc
Output Load Current
IL
20
mA
PD
1/qJA
1000
6.7
mW
mW/°C
Operating Ambient Temperature Range
TA
0 to + 75
°C
Storage Temperature Range
Tstg
− 65 to + 175
°C
Power Dissipation (Package Limitation, SOIC−14 and Plastic Dual In−Line Package)
Derate above TA = + 25°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC = + 5.0 Vdc ± 10%, TA = 0 to + 75°C, unless otherwise noted)
Characteristics
Symbol
Min
Typ
Max
Unit
Positive Input Current
(VIH = + 25 Vdc)
(VIH = + 3.0 Vdc)
IIH
3.6
0.43
−
−
8.3
−
mA
Negative Input Current
(VIH = − 25 Vdc)
(VIH = − 3.0 Vdc)
IIL
− 3.6
− 0.43
−
−
− 8.3
−
mA
1.0
1.75
−
1.95
1.5
2.25
0.75
0.75
−
0.8
1.25
1.25
Input Turn−On Threshold Voltage
(TA = + 25°C, VOL p 0.45 V)
VIH
MC1489
MC1489A
Input Turn−Off Threshold Voltage
(TA = + 25°C, VOH q 2.5 V, IL = − 0.5 mA)
VIL
MC1489
MC1489A
Vdc
Vdc
Output Voltage High
(VIH = 0.75 V, IL = − 0.5 mA)
(Input Open Circuit, IL = − 0.5 mA)
VOH
2.5
2.5
4.0
4.0
5.0
5.0
Vdc
Output Voltage Low
(VIL = 3.0 V, IL = 10 mA)
VOL
−
0.2
0.45
Vdc
Output Short−Circuit Current
IOS
−
− 3.0
− 4.0
mA
Power Supply Current (All Gates “on,” Iout = 0 mA, VIH = + 5.0 Vdc)
ICC
−
16
26
mA
Power Consumption
PC
−
80
130
mW
tPLH
−
25
85
ns
(VIH = + 5.0 Vdc)
SWITCHING CHARACTERISTICS (VCC = 5.0 Vdc ± 1%, TA = + 25°C, See Figure 3.)
Propagation Delay Time
(RL = 3.9 kW)
Rise Time
(RL = 3.9 kW)
tTLH
−
120
175
ns
Propagation Delay Time
(RL = 390 kW)
tPHL
−
25
50
ns
Fall Time
(RL = 390 kW)
tTHL
−
10
20
ns
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3
MC1489, MC1489A
TEST CIRCUITS
5.0 Vdc
RL
All diodes
1N3064
or equivalent
Ein
VR
Eo
R
CL
3.0 V
50%
50%
C
Ein
tPLH
EO
tTHL
tTLH and tTHL
measured
10% - 90%
Vin
tTLH
1.5 V
1/4
MC1489A
Response Node
1.5 V
CL = 15 pF = total parasitic capacitance which includes
probe and wiring capacitances
C, capacitor is for noise filtering.
R, resistor is for threshold shifting.
Figure 3. Switching Response
Figure 4. Response Control Node
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4
VO
MC1489, MC1489A
TYPICAL CHARACTERISTICS
(VCC = 5.0 Vdc, TA = +25°C, unless otherwise noted)
10
6.0
5.0
6.0
VO , OUTPUT VOLTAGE (Vdc)
IL, INPUT CURRENT (mA)
8.0
4.0
2.0
0
-2.0
II
-4.0
VI
-6.0
-8.0
-10
-25
-20
-15
-10 -5.0
0
5.0
10
15
20
25
VI
4.0 RT
5.0 k
3.0 Vth
5.0 V
2.0
RT
13 k
Vth
5.0 V
0
-3.0 -2.0 -1.0
VIH , INPUT THRESHOLD VOLTAGE (Vdc)
EO
RT
11 k
Vth
-5.0 V
RT
Vth
1.0
0
-3.0 -2.0
VILH
-1.0
0
1.0
VIHL
2.0
3.0
1.0
2.0
3.0
4.0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-60
MC1489A VIH
MC1489 VIH
MC1489 VIL
MC1489A VIL
0
+60
VI, INPUT VOLTAGE (V)
T, TEMPERATURE (°C)
Figure 7. MC1489A Input Threshold
Voltage Adjustment
Figure 8. Input Threshold Voltage
versus Temperature
2.0
INPUT THRESHOLD VOLTAGE (Vdc)
VO , OUTPUT VOLTAGE (Vdc)
Vin
2.0
0
Figure 6. MC1489 Input Threshold
Voltage Adjustment
5.0
RT
1
Vth
VI, INPUT VOLTAGE (V)
6.0
RT
5.0 k
Vth
5.0 V
RT
VILH VIHL
Figure 5. Input Current
3.0
RT
11 k
Vth
-5.0 V
1.0
VIH MC1489A
VIH MC1489
VIL MC1489
VIL MC1489A
0
3.0
EO
1.0
Vin, INPUT VOLTAGE (V)
4.0
RT
1
4.0
5.0
VCC, POWER SUPPLY VOLTAGE (V)
Figure 9. Input Threshold versus
Power Supply Voltage
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5
6.0
+120
MC1489, MC1489A
APPLICATIONS INFORMATION
General Information
turn−on voltage of 1.25 V and turn−off of 1.0 V for a typical
hysteresis of 250 mV. The MC1489A has typical turn−on of
1.95 V and turn−off of 0.8 V for typically 1.15 V of
hysteresis.
Each receiver section has an external response control
node in addition to the input and output pins, thereby
allowing the designer to vary the input threshold voltage
levels. A resistor can be connected between this node and an
external power supply. Figures 4, 6 and 7 illustrate the input
threshold voltage shift possible through this technique.
This response node can also be used for the filtering of
high frequency, high energy noise pulses. Figures 10 and 11
show typical noise pulse rejection for external capacitors of
various sizes.
These two operations on the response node can be
combined or used individually for many combinations of
interfacing applications. The MC1489 circuits are
particularly useful for interfacing between MOS circuits and
DTL/TTL logic systems. In this application, the input
threshold voltages are adjusted (with the appropriate supply
and resistor values) to fall in the center of the MOS voltage
logic levels (see Figure 12).
The response node may also be used as the receiver input
as long as the designer realizes that he may not drive this
node with a low impedance source to a voltage greater than
one diode above ground or less than one diode below
ground. This feature is demonstrated in Figure 13 where two
receivers are slaved to the same line that must still meet the
EIA−232D impedance requirement.
The Electronic Industries Association (EIA) has released
the EIA−232D specification detailing the requirements for
the interface between data processing equipment and data
communications equipment. This standard specifies not
only the number and type of interface leads, but also the
voltage levels to be used. The MC1488 quad driver and its
companion circuit, the MC1489 quad receiver, provide a
complete interface system between DTL or TTL logic levels
and the EIA−232D defined levels. The EIA−232D
requirements as applied to receivers are discussed herein.
The required input impedance is defined as between
3000 W and 7000 W for input voltages between 3.0 and 25 V
in magnitude; and any voltage on the receiver input in an
open circuit condition must be less than 2.0 V in magnitude.
The MC1489 circuits meet these requirements with a
maximum open circuit voltage of one VBE.
The receiver shall detect a voltage between − 3.0 and
−25 V as a Logic “1” and inputs between 3.0 and 25 V as a
Logic “0.” On some interchange leads, an open circuit of
power “OFF” condition (300 W or more to ground) shall be
decoded as an “OFF” condition or Logic “1.” For this
reason, the input hysteresis thresholds of the MC1489
circuits are all above ground. Thus an open or grounded
input will cause the same output as a negative or Logic “1”
input.
Device Characteristics
The MC1489 interface receivers have internal feedback
from the second stage to the input stage providing input
hysteresis for noise rejection. The MC1489 input has typical
6
6
MC1489A
MC1489
5
10 pF
100 pF 300 pF
500 pF
E in , AMPLITUDE (V)
E in , AMPLITUDE (V)
5
4
3
12 pF
100 pF 300 pF
4
500 pF
3
2
2
1
1
10
100
1000
10
10,000
100
1000
10,000
PW, INPUT PULSE WIDTH (ns)
PW, INPUT PULSE WIDTH (ns)
Figure 10. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND
Figure 11. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND
http://onsemi.com
6
MC1489, MC1489A
+5.0 Vdc
R
MC1489
MOS
Logic
-VGG
DTL or TTL
-VDD
+5.0 Vdc
+5.0 Vdc
Figure 12. Typical Translator Application − MOS to DTL or TTL
VCC
Response-Control Pin
Input
1/2 MC1489
Output
8.0 k
VCC
Input
Output
8.0 k
Response-Control Pin
Figure 13. Typical Paralleling of Two MC1489, A Receivers to Meet EIA−232D
http://onsemi.com
7
MC1489, MC1489A
ORDERING INFORMATION
Device
Package
MC1489D
SOIC−14
MC1489DG
SOIC−14
(Pb−Free)
MC1489DR2
SOIC−14
MC1489DR2G
SOIC−14
(Pb−Free)
MC1489AD
SOIC−14
MC1489ADG
SOIC−14
(Pb−Free)
MC1489ADR2
SOIC−14
MC1489ADR2G
SOIC−14
(Pb−Free)
MC1489P
PDIP−14
MC1489PG
PDIP−14
(Pb−Free)
MC1489AP
PDIP−14
MC1489APG
PDIP−14
(Pb−Free)
Operating Temperature Range
Shipping†
55 Units/Rail
2500 Tape & Reel
55 Units/Rail
2500 Tape & Reel
TA = 0 to +75°C
MC1489M
SOEIAJ−14
MC1489MG
SOEIAJ−14
(Pb−Free)
MC1489MEL
SOEIAJ−14
MC1489MELG
SOEIAJ−14
(Pb−Free)
MC1489AM
SOEIAJ−14
MC1489AMG
SOEIAJ−14
(Pb−Free)
MC1489AMEL
SOEIAJ−14
MC1489AMELG
SOEIAJ−14
(Pb−Free)
25 Units/Rail
50 Units/Rail
2000 Tape & Reel
50 Units/Rail
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MC1489, MC1489A
MARKING DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
14
14
MC1489ADG
AWLYWW
1
PDIP−14
P SUFFIX
CASE 646
14
14
MC1489DG
AWLYWW
MC1489P
AWLYYWWG
MC1489AP
AWLYYWWG
1
1
SOEIAJ−14
M SUFFIX
CASE 965
MC1489
ALYWG
MC1489A
ALYWG
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
http://onsemi.com
9
1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
1
SCALE 1:1
D
A
14
8
E
H
E1
1
NOTE 8
7
b2
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
NOTE 3
L
SEATING
PLANE
A1
C
D1
e
M
eB
END VIEW
14X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO
CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO
CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. DRAIN
2. SOURCE
3. GATE
4. NO
CONNECTION
5. GATE
6. SOURCE
7. DRAIN
8. DRAIN
9. SOURCE
10. GATE
11. NO
CONNECTION
12. GATE
13. SOURCE
14. DRAIN
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. NO CONNECTION
5. SOURCE
6. DRAIN
7. GATE
8. GATE
9. DRAIN
10. SOURCE
11. NO CONNECTION
12. SOURCE
13. DRAIN
14. GATE
STYLE 6:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 7:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON
CATHODE
STYLE 8:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 9:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 10:
PIN 1. COMMON
CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON
CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 12:
PIN 1. COMMON CATHODE
2. COMMON ANODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. COMMON ANODE
7. COMMON CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. ANODE/CATHODE
14. ANODE/CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
DATE 29 FEB 2008
SCALE 1:1
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DOCUMENT NUMBER:
98ASH70108A
DESCRIPTION:
14 LD SOEIAJ
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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