MC3303DR2G

MC3403, MC3303 Single Supply Quad Operational Amplifiers The MC3403 is a low cost, quad operational amplifier with true differential inputs. The device has electrical characteristics similar to the popular MC1741C. However, the MC3403 has several distinct advantages over standard operational amplifier types in single supply applications. The quad amplifier can operate at supply voltages as low as 3.0 V or as high as 36 V with quiescent currents about one third of those associated with the MC1741C (on a per amplifier basis). The common mode input range includes the negative supply, thereby eliminating the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage. http://onsemi.com MARKING DIAGRAMS 14 14 1 Features • • • • • • • • • • • • SOIC−14 D SUFFIX CASE 751A MC3x03DG AWLYWW 1 Short Circuit Protected Outputs Class AB Output Stage for Minimal Crossover Distortion True Differential Input Stage Single Supply Operation: 3.0 V to 36 V Split Supply Operation: ±1.5 V to ±18 V Low Input Bias Currents: 500 nA Max Four Amplifiers Per Package Internally Compensated Similar Performance to Popular MC1741C Industry Standard Pin−outs ESD Diodes Added for Increased Ruggedness Pb−Free Packages are Available 14 PDIP−14 P SUFFIX CASE 646 14 MC3x03P AWLYYWWG 1 x = 3 or 4 A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Package 1 PIN CONNECTIONS Single Supply 3.0 V to 36 V VCC Split Supplies Out 1 1 VCC 1 1 1.5 V to 18 V 2 Inputs 1 3 2 2 3 3 4 4 VEE, GND VCC 1.5 V to 18 V + 1 4 - 13 + 12 4 5 Inputs 2 VEE 14 Out 4 6 Inputs 4 VEE/GND 11 + 2 - 3 + - Out 2 7 10 Inputs 3 9 8 Out 3 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 11 1 Publication Order Number: MC3403/D MC3403, MC3303 ORDERING INFORMATION Device Shipping† Package MC3303D SOIC−14 MC3303DG SOIC−14 (Pb−Free) MC3303DR2 SOIC−14 MC3303DR2G SOIC−14 (Pb−Free) MC3303P PDIP−14 MC3303PG PDIP−14 (Pb−Free) MC3403D SOIC−14 MC3403DG SOIC−14 (Pb−Free) MC3403DR2 SOIC−14 MC3403DR2G SOIC−14 (Pb−Free) MC3403P PDIP−14 MC3403PG PDIP−14 (Pb−Free) 55 Units / Rail 2500 Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Tape & Reel 25 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS Rating Symbol Value VCC VCC, VEE 36 ±18 Input Differential Voltage Range (Note 1) VIDR ±36 Vdc Input Common Mode Voltage Range (Notes 1 and 2) VICR ±18 Vdc Storage Temperature Range Tstg −55 to +125 °C Operating Ambient Temperature Range TA Power Supply Voltages Single Supply Split Supplies MC3303 MC3403 Junction Temperature TJ −40 to +85 0 to +70 150 Unit Vdc °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Split power supplies. 2. For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. http://onsemi.com 2 MC3403, MC3303 ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V for MC3403; VCC = +14 V, VEE = GND for MC3303 TA = 25°C, unless otherwise noted.) MC3403 MC3303 Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage TA = Thigh to Tlow (Note 3) VIO − − 2.0 − 10 12 − − 2.0 − 8.0 10 mV Input Offset Current TA = Thigh to Tlow IIO − − 30 − 50 200 − − 30 − 75 250 nA 20 15 200 − − − 20 15 200 − − − Characteristic Large Signal Open Loop Voltage Gain VO = ±10 V, RL = 2.0 k TA = Thigh to Tlow AVOL V/mV Input Bias Current TA = Thigh to Tlow IIB − − −200 − −500 −800 − − −200 − −500 −1000 nA Output Impedance f = 20 Hz zo − 75 − − 75 −  Input Impedance f = 20 Hz zi 0.3 1.0 − 0.3 1.0 − M ±12 ±10 ±10 ±13.5 ±13 − − − − 12 10 10 12.5 12 − − − − Output Voltage Range RL = 10 k RL = 2.0 k RL = 2.0 k, TA = Thigh to Tlow VO V Input Common Mode Voltage Range VICR +13 V −VEE +13 V −VEE − +12 V −VEE +12.5 V −VEE − V Common Mode Rejection RS ≤ 10 k CMR 70 90 − 70 90 − dB Power Supply Current (VO = 0) RL = ∞ ICC, IEE − 2.8 7.0 − 2.8 7.0 mA ISC ±10 ±20 ±45 ±10 ±30 ±45 mA Positive Power Supply Rejection Ratio PSRR+ − 30 150 − 30 150 V/V Negative Power Supply Rejection Ratio PSRR− − 30 150 − 30 150 V/V Average Temperature Coefficient of Input Offset Current TA = Thigh to Tlow IIO/T − 50 − − 50 − pA/°C Average Temperature Coefficient of Input Offset Voltage TA = Thigh to Tlow VIO/T − 10 − − 10 − V/°C Power Bandwidth AV = 1, RL = 10 k VO = 20 V(p−p), THD = 5% BWp − 9.0 − − 9.0 − kHz Small−Signal Bandwidth AV = 1, RL = 10 k VO = 50 mV BW − 1.0 − − 1.0 − MHz Slew Rate AV = 1, Vi = −10 V to +10 V SR − 0.6 − − 0.6 − V/s Rise Time AV = 1, RL = 10 k VO = 50 mV tTLH − 0.35 − − 0.35 − s Fall Time AV = 1, RL = 10 k VO = 50 mV tTLH − 0.35 − − 0.35 − s Overshoot AV = 1, RL = 10 k VO = 50 mV os − 20 − − 20 − % Phase Margin AV = 1, RL = 2.0 k, VO = 200 pF m − 60 − − 60 − ° − − 1.0 − − 1.0 − % Individual Output Short−Circuit Current (Note 4) Crossover Distortion (Vin = 30 mVpp,Vout= 2.0 Vpp, f = 10 kHz) 3. MC3303: Tlow = −40°C, Thigh = +85°C, MC3403: Tlow = 0°C, Thigh = +70°C 4. Not to exceed maximum package power dissipation. http://onsemi.com 3 MC3403, MC3303 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.) MC3403 MC3303 Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage VIO − 2.0 10 − − 10 mV Input Offset Current IIO − 30 50 − − 75 nA Input Bias Current IIB − −200 −500 − − −500 nA Large Signal Open Loop Voltage Gain RL = 2.0 k AVOL 10 200 − 10 200 − V/mV Power Supply Rejection Ratio PSRR − − 150 − − 150 V/V 3.3 VCC−2.0 3.5 VCC−1.7 − − 3.3 VCC−2.0 3.5 VCC−1.7 − − Characteristic Output Voltage Range (Note 5) RL = 10 k, VCC = 5.0 V RL = 10 k, 5.0 ≤ VCC ≤ 30 V VOR Power Supply Current ICC − 2.5 7.0 − 2.5 7.0 mA Channel Separation f = 1.0 kHz to 20 kHz (Input Referenced) CS − −120 − − −120 − dB 5. Output will swing to ground with a 10 k pull down resistor. Output Q19 VCC Q18 Q27 Q20 Q17 Q23 Q16 40 k 5.0 pF Q29 31k Q28 Q1 + Q22 Q24 Q2 Q6 Q5 Q3 Q4 Q13 37 k Q25 Q21 Q15 2.0 k Q9 Inputs - Bias Circuitry Common to Four Amplifiers Q12 Q10 Q7 60 k Q11 25 Q30 2.4 k Q8 VEE (GND) Figure 1. Representative Schematic Diagram (1/4 of Circuit Shown) http://onsemi.com 4 Vpp MC3403, MC3303 CIRCUIT DESCRIPTION 5.0 V/DIV stage performs not only the first stage gain function but also performs the level shifting and Transconductance reduction functions. By reducing the Transconductance, a smaller compensation capacitor (only 5.0 pF) can be employed, thus saving chip area. The Transconductance reduction is accomplished by splitting the collectors of Q24 and Q22. Another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation, without saturating either the input devices or the differential to single−ended converter. The second stage consists of a standard current source load amplifier stage. The output stage is unique because it allows the output to swing to ground in single supply operation and yet does not exhibit any crossover distortion in split supply operation. This is possible because Class AB operation is utilized. Each amplifier is biased from an internal voltage regulator which has a low temperature coefficient, thus giving each amplifier good temperature characteristics as well as excellent power supply rejection. 20 s/DIV Figure 2. Inverter Pulse Response The MC3403/3303 is made using four internally compensated, two−stage operational amplifiers. The first stage of each consists of differential input device Q24 and Q22 with input buffer transistors Q25 and Q21 and the differential to single ended converter Q3 and Q4. The first 120 50 mV/DIV 0.5 V/DIV A VOL , LARGE SIGNAL OPEN LOOP VOLTAGE GAIN (dB) AV = 100 80 60 40 20 0 -20 *Note Class A B output stage produces distortion less sinewave. VCC = 15 V VEE = -15 V TA = 25°C 100 1.0 10 50 s/DIV Figure 3. Sine Wave Response VO, OUTPUT VOLTAGE RANGE (V pp) VO, OUTPUT VOLTAGE (Vpp ) +15 V 20 VO + -15 V 10 k 15 10 5.0 TA = 25°C 0 -5.0 1.0 k 100 k 1.0 M Figure 4. Open Loop Frequency Response 30 25 100 1.0 k 10 k f, FREQUENCY (Hz) 10 k 100 k f, FREQUENCY (Hz) TA = 25°C 30 20 10 0 1.0 M 0 Figure 5. Power Bandwidth 2.0 4.0 6.0 8.0 10 12 14 16 18 VCC AND (VEE), POWER SUPPLY VOLTAGES (V) 20 Figure 6. Output Swing versus Supply Voltage http://onsemi.com 5 MC3403, MC3303 I IB, INPUT BIAS CURRENT (nA) I IB , INPUT BIAS CURRENT (nA) VCC = 15 V VEE = -15 V TA = 25°C 300 200 100 -75 -55 -35 -15 5.0 25 45 65 85 170 160 150 105 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 T, TEMPERATURE (°C) VCC AND (VEE), POWER SUPPLY VOLTAGES (V) Figure 7. Input Bias Current versus Temperature Figure 8. Input Bias Current versus Supply Voltage VCC 50 k 1N914 VCC 10 k R2 - 5.0 k 1/2 MC3403 + 1N914 VCC 10 k VO Vref - 1/2 10 k R1 fo = 1 Vref =  VCC 2 R1 VO = R1 +R2 R VO = R 1 V 2 CC Figure 9. Voltage Reference + e1 1/2 1 R C e2 For: fo = 1.0 kHz R = 16 k C = 0.01 F C Hysteresis R2 VOH R Vref - a R1 1/2 MC3403 + b R1 - 1/2 MC3403 + C 1 2RC Figure 10. Wien Bridge Oscillator MC3403 − R1 VO MC3403 + R1 1/2 MC3403 + Vin eo - VO VO VOL VinL 1 R C VinL= R1 (VOL -Vref) +Vref R1 +R2 VinH= R1 (VOH -Vref) +Vref R1 +R2 Vh= R1 (VOH -VOL) R1 +R2 R eo = C (1 +a +b) (e2 −e1) Figure 11. High Impedance Differential Amplifier Figure 12. Comparator with Hysteresis http://onsemi.com 6 VinH Vref 20 MC3403, MC3303 R R C1 Vin 100 k C R2 - fo = R1 = QR C 1/2 - MC3403 + 100 k 1/2 1/2 MC3403 + Vref R1 R2 Bandpass Output = 1.0 kHz = 10 =1 =1 Where: - 1 V 2 CC R = 160 k C = 0.001 F R1 = 1.6 M R2 = 1.6 M R3 = 1.6 M C1 Notch Output MC3403 + TBP = center frequency gain TN = passband notch gain Vref = Vref R3 1/2 For: fo Q TBP TN R2 = R1 TBP R3 = TNR2 C1 = 10 C - MC3403 + Vref 1 2RC Vref Figure 13. Bi−Quad Filter VCC C R1 Vin Vref = 1/2 R2 Triangle Wave Output R3 MC3403 - 75 k + R1 100 k Vref C Vref 300 k 1/2 1/2 MC3403 - Given: Square Wave Output R1 +RC 4 CRf R1 if R3 = CO = 10 C Vref = 1 V 2 CC fo = center frequency A(fo) = gain at center frequency Choose value fo, C Then: R3 = Q  fo C R1 = R3 2 A(fo) R2 = R1 R5 4Q2 R1 -R5 Oo fo For less than 10% error from operational amplifier < 0.1 BW where fo and BW are expressed in Hz. If source impedance varies, filter may be preceded with voltage follower buffer to stabilize filter parameters. Rf f= VO MC3403 + R2 Vref CO - 1 V 2 CC + C R3 R2 R1 R2 +R1 Figure 14. Function Generator Figure 15. Multiple Feedback Bandpass Filter http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE S 1 SCALE 1:1 D A 14 8 E H E1 1 NOTE 8 7 b2 c B TOP VIEW END VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A NOTE 3 L SEATING PLANE A1 C D1 e M eB END VIEW 14X b SIDE VIEW 0.010 M C A M B M NOTE 6 DATE 22 APR 2015 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.735 0.775 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 18.67 19.69 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° GENERIC MARKING DIAGRAM* 14 XXXXXXXXXXXX XXXXXXXXXXXX AWLYYWWG STYLES ON PAGE 2 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42428B PDIP−14 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com PDIP−14 CASE 646−06 ISSUE S DATE 22 APR 2015 STYLE 1: PIN 1. COLLECTOR 2. BASE 3. EMITTER 4. NO CONNECTION 5. EMITTER 6. BASE 7. COLLECTOR 8. COLLECTOR 9. BASE 10. EMITTER 11. NO CONNECTION 12. EMITTER 13. BASE 14. COLLECTOR STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. DRAIN 2. SOURCE 3. GATE 4. NO CONNECTION 5. GATE 6. SOURCE 7. DRAIN 8. DRAIN 9. SOURCE 10. GATE 11. NO CONNECTION 12. GATE 13. SOURCE 14. DRAIN STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. NO CONNECTION 5. SOURCE 6. DRAIN 7. GATE 8. GATE 9. DRAIN 10. SOURCE 11. NO CONNECTION 12. SOURCE 13. DRAIN 14. GATE STYLE 6: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 7: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 8: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 9: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE STYLE 10: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 11: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 12: PIN 1. COMMON CATHODE 2. COMMON ANODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. COMMON ANODE 7. COMMON CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. ANODE/CATHODE 14. ANODE/CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42428B PDIP−14 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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