MC33077
Operational Amplifier, Low
Noise, Dual
The MC33077 is a precision high quality, high frequency, low noise
monolithic dual operational amplifier employing innovative bipolar
design techniques. Precision matching coupled with a unique analog
resistor trim technique is used to obtain low input offset voltages.
Dual−doublet frequency compensation techniques are used to enhance
the gain bandwidth product of the amplifier. In addition, the MC33077
offers low input noise voltage, low temperature coefficient of input
offset voltage, high slew rate, high AC and DC open loop voltage gain
and low supply current drain. The all NPN transistor output stage
exhibits no deadband cross−over distortion, large output voltage
swing, excellent phase and gain margins, low open loop output
impedance and symmetrical source and sink AC frequency
performance.
The MC33077 is available in plastic DIP and SOIC−8 packages (P
and D suffixes).
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•
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
8
1
33077
ALYW
1
8
PDIP−8
P SUFFIX
CASE 626
8
Features
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MC33077P
AWL
YYWW
1
Low Voltage Noise: 4.4 nV/ Hz @ 1.0 kHz
Low Input Offset Voltage: 0.2 mV
Low TC of Input Offset Voltage: 2.0 V/°C
High Gain Bandwidth Product: 37 MHz @ 100 kHz
High AC Voltage Gain: 370 @ 100 kHz
1850 @ 20 kHz
Unity Gain Stable: with Capacitance Loads to 500 pF
High Slew Rate: 11 V/s
Low Total Harmonic Distortion: 0.007%
Large Output Voltage Swing: +14 V to −14.7 V
High DC Open Loop Voltage Gain: 400 k (112 dB)
High Common Mode Rejection: 107 dB
Low Power Supply Drain Current: 3.5 mA
Dual Supply Operation: ±2.5 V to ±18 V
Pb−Free Package is Available
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
Output 1 1
8 VCC
−
2
7 Output 2
1
+
Inputs 1
3
−
6
2
Inputs 2
+
VEE 4
5
(Dual, Top View)
ORDERING INFORMATION
Device
Package
Shipping†
MC33077D
SOIC−8
98 Units/Rail
MC33077DR2
SOIC−8
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
PDIP−8
50 Units/Rail
MC33077DR2G
MC33077P
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 5
1
Publication Order Number:
MC33077/D
MC33077
R1
R6
Bias Network
Q1
J1
R8
R11
Q17
Q8
Q13
Q19
D3
Q11
C3
C1
VCC
R16
R3
R9
Q14
Z1
Q21
D6
D4
Q6
R13
Q7
Neg
Q9
Pos
Q16
R17 R18 Vout
C6
Q2
Q4
Q10
R5 C2
R14
Q12
D7
R19
C7
D1
Q22
C8
Q1
Q5
R4
R2
R7
R10
R12
Q20
D5
R20
R15
D2
VEE
Figure 1. Representative Schematic Diagram (Each Amplifier)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+36
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Input Voltage Range
VIR
(Note 1)
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
−60 to +150
°C
ESD Protection at any Pin
Vesd
Supply Voltage (VCC to VEE)
− Human Body Model
− Machine Model
V
550
150
Maximum Power Dissipation
PD
(Note 2)
mW
Operating Temperature Range
TA
−40 to + 85
°C
Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Functional operation
should be restricted to the Recommended Operating Conditions.
1. Either or both input voltages should not exceed VCC or VEE (See Applications Information).
2. Power dissipation must be considered to ensure maximum junction temperature (T J) is not exceeded (See power dissipation performance
characteristic, Figure 2).
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2
MC33077
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Symbol
Input Offset Voltage (RS = 10 , VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
Min
Typ
Max
−
−
0.13
−
1.0
1.5
−
2.0
−
−
−
280
−
1000
1200
−
−
15
−
180
240
±13.5
±14
−
150
125
400
−
−
−
|VIO|
mV
VIO/T
Average Temperature Coefficient of Input Offset Voltage
RS = 10 , VCM = 0 V, VO = 0 V, TA = −40° to +85°C
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
IIB
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
IIO
Common Mode Input Voltage Range (VIO ,= 5.0 mV, VO = 0 V)
VICR
Large Signal Voltage Gain (VO = ±1.0 V, RL = 2.0 k)
TA = +25°C
TA = −40° to +85°C
AVOL
Unit
V/°C
nA
nA
V
kV/V
Output Voltage Swing (VID = ±1.0 V)
RL = 2.0 k
RL = 2.0 k
RL = 10 k
RL = 10 k
VO+
VO −
VO+
VO −
+13.0
−
+13.4
−
+13.6
−14.1
+14.0
−14.7
−
−13.5
−
−14.3
Common Mode Rejection (Vin = ±13 V)
CMR
85
107
−
Power Supply Rejection (Note 3)
VCC/VEE = +15 V/ −15 V to +5.0 V/ −5.0 V
PSR
80
90
−
+10
−20
+26
−33
+60
+60
−
−
3.5
−
4.5
4.8
V
Output Short Circuit Current (VID = ±1.0 V, Output to Ground)
Source
Sink
ISC
Power Supply Current (VO = 0 V, All Amplifiers)
TA = +25°C
TA = −40° to +85°C
ID
3. Measured with VCC and VEE simultaneously varied.
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3
dB
dB
mA
mA
MC33077
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
SR
8.0
11
−
V/s
GBW
25
37
−
MHz
−
−
370
1850
−
−
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 k, CL = 100 pF, AV = +1.0)
Gain Bandwidth Product (f = 100 kHz)
AC Voltage Gain (RL = 2.0 k, VO = 0 V)
f = 100 kHz
f = 20 kHz
AVO
V/V
Unity Gain Bandwidth (Open Loop)
BW
−
7.5
−
Gain Margin (RL = 2.0 k, CL = 10 pF)
Am
−
10
−
dB
Phase Margin (RL = 2.0 k, CL = 10 pF)
∅m
−
55
−
Deg
Channel Separation (f = 20 Hz to 20 kHz, RL = 2.0 k, VO = 10 Vpp)
CS
−
−120
−
dB
Power Bandwidth (VO = 27p−p, RL = 2.0 k, THD ≤ 1%)
BWp
−
200
−
kHz
Distortion (RL = 2.0 k
AV = +1.0, f = 20 Hz to 20 kHz
VO = 3.0 VRMS
AV = 2000, f = 20 kHz
VO = 2.0 Vpp
VO = 10 Vpp
AV = 4000, f = 100 kHz
VO = 2.0 Vpp
VO = 10 Vpp
THD
Open Loop Output Impedance (VO = 0 V, f = fU)
MHz
%
0.007
−
−
−
0.215
0.242
−
−
−
−
0.3.19
0.316
−
−
|ZO|
−
36
−
Differential Input Resistance (VCM = 0 V)
Rin
−
270
−
k
Differential Input Capacitance (VCM = 0 V)
Cin
−
15
−
pF
Equivalent Input Noise Voltage (RS = 100 )
f = 10 Hz
f = 1.0 kHz
en
−
−
6.7
4.4
−
−
Equivalent Input Noise Current (f = 1.0 kHz)
f = 10 Hz
f = 1.0 kHz
in
−
−
1.3
0.6
−
−
2400
nV/ √ Hz
pA/ √ Hz
800
I IB, INPUT BIAS CURRENT (nA)
PD(MAX) , MAXIMUM POWER DISSIPATION (mW)
−
2000
1600
MC33077P
1200
800
MC33077D
400
0
−60 −40 −20
VCM = 0 V
TA = 25°C
600
400
200
0
0
20
40
60
80
100 120 140 160 180
0
2.5
5.0
7.5
10
12.5
15
TA, AMBIENT TEMPERATURE (°C)
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Bias Current
versus Supply Voltage
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4
17.5
20
MC33077
800
1.0
V,
IO INPUT OFFSET VOLTAGE (mV)
I IB, INPUT BIAS CURRENT (nA)
1000
VCC = +15 V
VEE = −15 V
VCM = 0 V
600
400
200
0
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0.5
0
−0.5
VCC = +15 V
VEE = −15 V
RS = 10
VCM = 0 V
AV = +1.0
−1.0
−55
−25
VCC = +15 V
VEE = −15 V
TA = 25°C
400
300
200
100
V
sat , OUTPUT SATURATION VOLTAGE (V)
0
−15
−10
−5.0
0
5.0
10
15
VCC −1.5
VCC = +3.0 V to +15 V
VEE = −3.0 V to −15 V
VIO = 5.0 mV
VO = 0 V
Input
Voltage
Range
VEE +1.5
VEE +1.0
VEE +0.5
−VCM
VEE +0.0
−55
−25
0
25
50
75
100
125
Figure 7. Input Common Mode Voltage Range
versus Temperature
−55°C
25°C
125°C
VCC = +15 V
VEE = −15 V
125°C
25°C
−55°C
0
VCC −1.0
Figure 6. Input Bias Current versus
Common Mode Voltage
VCC −4
VEE 0
+VCM
TA, AMBIENT TEMPERATURE (°C)
VCC −2
VEE +2
VCC −0.5
VCM, COMMON MODE VOLTAGE (V)
VCC 0
VEE +4
125
VCC 0.0
0.5
1.0
1.5
2.0
2.5
RL, LOAD RESISTANCE TO GROUND (k)
3.0
|I|,
SC OUTPUT SHORT CIRCUIT CURRENT (mA)
I IB , INPUT BIAS CURRENT (nA)
600
500
100
Figure 5. Input Offset Voltage
versus Temperature
V ICR , INPUT COMMON MODE VOTAGE RANGE (V)
Figure 4. Input Bias Current
versus Temperature
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
50
40
Sink
VCC = +15 V
VEE = −15 V
VID = ±1.0 V
RL < 100
30
Source
20
10
−55
Figure 8. Output Saturation Voltage versus
Load Resistance to Ground
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 9. Output Short Circuit Current
versus Temperature
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5
125
MC33077
4.0
±15 V
±5.0 V
3.0
2.0
VCM = 0 V
RL = ∞
VO = 0 V
1.0
0
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
120
CMR, COMMON MODE REJECTION (dB)
I,
CC SUPPLY CURRENT (mA)
5.0
80
CMR = 20Log
20
0
100
125
−PSR
60
40
20
GBW, GAIN BANDWIDTH PRODUCT (MHz)
+PSR
80
VCC
VCC = +15 V
VEE = −15 V
TA = 25°C
1.0 k
−
VO
ADM
+
VEE
10 k
100 k
1.0 M
× ADM
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
10 M
48
RL = 10 k
CL = 0 pF
f = 100 kHz
TA = 25°C
44
40
36
32
28
24
0
5
10
15
20
f, FREQUENCY (Hz)
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 12. Power Supply Rejection
versus Frequency
Figure 13. Gain Bandwidth Product
versus Supply Voltage
20
50
VCC = +15 V
VEE = −15 V
f = 100 kHz
RL = 10 k
CL = 0 pF
46
42
15
38
34
30
26
−55
VO
Figure 11. Common Mode Rejection
versus Frequency
VO/ADM
VEE
−PSR = 20Log
VCM
VCC = +15 V
VEE = −15 V
VCM = 0 V
VCM = ±1.5 V
TA = 25°C
40
VO,OUTPUT VOLTAGE (Vp )
PSR, POWER SUPPLY REJECTION (dB)
100
0
100
GBW, GAIN BANDWIDTH PRODUCT (MHz)
VO/ADM
VCC
+PSR = 20Log
VO
60
Figure 10. Supply Current
versus Temperature
120
−
ADM
+
VCM
100
10
RL = 10 k
TA = 25°C
Vp +
RL = 2.0 k
5.0
0
−5.0
Vp −
−10
RL = 2.0 k
−15
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
−20
0
125
Figure 14. Gain Bandwidth Product
versus Temperature
RL = 10 k
5.0
10
15
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 15. Maximum Output Voltage
versus Supply Voltage
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6
20
MC33077
AVOL , OPEN LOOP VOLTAGE GAIN (X1000 V/V)
VO, OUTPUT VOLTAGE (Vpp )
30
25
20
15
VCC = +15 V
VEE = −15 V
RL = 2.0 k
AV =+1.0
THD ≤ 1.0%
TA = 25°C
10
5.0
0
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
1200
RL = 2.0 k
f = 10 Hz
VO = 2/3 (VCC −VEE)
TA = 25°C
1000
800
600
400
200
0
0
5.0
10
15
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 17. Open Loop Voltage Gain
versus Supply Voltage
80
600
VCC = +15 V
VEE = −15 V
RL = 2.0 k
f = 10 Hz
VO = −10 V to +10 V
550
500
| Z|,
Ω
O OUTPUT IMPEDANCE ()
A VOL , OPEN LOOP VOLTAGE GAIN (X1000 V/V)
Figure 16. Output Voltage
versus Frequency
450
400
350
300
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
70
60
50
40
30
AV = 10
20
AV = 1000
AV = 1.0
0
100
125
1.0 k
THD, TOTAL HARMONIC DISTORTION (%)
CS, CHANNEL SEPARATION (dB)
140
Vin
Drive Channel
VCC = +15 V
VEE = −15 V
RL = 2.0 k
VOD = 20 Vpp
TA = 25°C
VO
Measurement Channel
130
120
110
100
10
CS = 20 Log
100
1.0 k
f, FREQUENCY (Hz)
10 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
10 M
Figure 19. Output Impedance
versus Frequency
160
−
+
AV = 100
10
Figure 18. Open Loop Voltage Gain
versus Temperature
150
20
VOD
Vin
100 k
1.0
VCC = +15 V VO = 2.0 Vpp
VEE = −15 V TA = 25°C
AV = +1000
AV = +100
0.1
AV = +10
0.01
RA
Vin
0.001
10
Figure 20. Channel Separation
versus Frequency
100k
2.0k
−
+
VO
100
AV = +1.0
1.0 k
f, FREQUENCY (Hz)
10 k
Figure 21. Total Harmonic Distortion
versus Frequency
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7
100 k
1.0
VCC = +15 V
VEE = −15 V
V0 = −10 Vpp
TA = 25°C
100k
RA
Vin
−
+
THD, TOTAL HARMONIC DISTORTION (%)
2.0k
VO
0.1
AV = +1000
AV = +100
AV = +10
0.01
AV = +1.0
0.001
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
1.0
VCC = +15 V
VEE = −15 V
f = 20 kHz
TA = 25°C
0.5
0.1
Vin
2.0k
−
+
VO
0.05
AV = +100
0.01
AV = +10
0.005
AV = +1.0
0.001
0
2.0
4.0
6.0
8.0
VO, OUTPUT VOLTAGE (Vpp)
10
12
Figure 23. Total Harmonic Distortion
versus Output Voltage
40
16
SR, SLEW RATE (V/µ s)
Vin = 2/3 (VCC −VEE)
TA = 25°C
SR, SLEW RATE (V/s)
µ
RA
AV = +1000
Figure 22. Total Harmonic Distortion
versus Frequency
12
8.0
−
Vin
4.0
VO
+
2.0k
100pF
0
0
2.5
5.0
7.5
10
12.5
15
VCC, |VEE|, SUPPLY VOLTAGE (V)
17.5
30
180
100
Gain
40
80
60
120
20
160
200
−20
−60
10
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
10 M
A,
m OPEN LOOP GAIN MARGIN (dB)
Phase
φ , EXCESS PHASE (DEGREES)
140
+
2.0k
VO
100pF
10
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 25. Slew Rate versus Temperature
0
VCC = +15 V
VEE = −15 V
RL = 2.0 k
TA = 25°C
Vin
20
0
−55
20
−
VCC = +15 V
VEE = −15 V
Vin = 20 V
Figure 24. Slew Rate versus Supply Voltage
A VOL , OPEN−LOOP VOLTAGE GAIN (dB)
100k
14
0
125°C
12
Vin
25°C
10
Figure 26. Voltage Gain and Phase
versus Frequency
+
2.0k
VO
10
CL
20
30
8.0
Phase
−55°C
40
6.0
4.0
Gain
125°C
2.0
−55°C
0
1.0
240
100 M
−
25°C
VCC = +15 V
VEE = −15 V
VO = 0 V
10
100
CL, OUTPUT LOAD CAPACITANCE (pF)
50
60
70
1000
Figure 27. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance
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8
φm , PHASE MARGIN (DEGREES)
THD, TOTAL HARMONIC DISTORTION (%)
MC33077
MC33077
100
60
80
CL = 100 pF
50
40
VCC = +15 V
VEE = −15 V
TA = 25°C
30
CL = 300 pF
CL = 500 pF
20
−
+
Vin
10
125°C and 25°C
10
1
10
3.0
2.0
1.0
Current
0.5
5.0
Voltage
100
1.0 k
f, FREQUENCY (Hz)
0.3
0.2
0.1
100 k
10 k
nV/ √ Hz )
V,
V n TOTAL REFERRED NOISE VOLTAGE (
10
5.0
i,INPUT
REFERRED NOISE CURRENT (pA)
n
e,
nV/ √ Hz )
n INPUT REFERRED NOISE VOLTAGE (
10
10
1000
VCC = +15 V
f = 1.0 kHz
VEE = −15 V
TA = 25°C
Vn (total) =
(inRs)2 en2 4KTRS
100
10
1.0
10
Figure 30. Input Referred Noise Voltage
and Current versus Frequency
1.0 k
10 k
100 k
RS, SOURCE RESISTANCE ()
R1
10
Vin
8.0
10
−
+
20
VO
30
R2
Phase
6.0
40
VCC = +15 V
VEE = −15 V
RT = R1 + R2
VO = 0 V
TA = 25°C
4.0
2.0
50
60
0
1.0
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
0
Gain
φ m ,PHASE MARGIN (DEGREES)
A,
m GAIN MARGIN (dB)
100
1.0 M
Figure 31. Total Input Referred Noise Voltage
versus Source Resistant
14
12
1000
Figure 29. Overshoot versus
Output Load Capacitance
VCC = +15 V
VEE = −15 V
TA = 25°C
1.0
1.0
−55°C
100
CL, OUTPUT LOAD CAPACITANCE (pF)
100
3.0
2.0
100pF
20
Figure 28. Phase Margin versus
Output Voltage
30
20
+
2.0k
40
VO
0
5.0
VO, OUTPUT VOLTAGE (V)
50
VO
60
0
−5.0
Vin
CL
2.0k
0
−10
VCC = +15 V
VEE = −15 V
Vin = 100 mV
−
CL = 0 pF
os, OVERSHOOT (%)
φ m , PHASE MARGIN (DEGREES)
70
70
10 k
10
100
1.0 k
RT, DIFFERENTIAL SOURCE RESISTANCE ()
VCC = +15 V
VEE = −15 V
AV = −1.0
RL = 2.0 k
CL = 100 pF
TA = 25°C
t, TIME (2.0 s/DIV)
Figure 32. Phase Margin and Gain Margin
versus Differential Source Resistance
Figure 33. Inverting Amplifier Slew Rate
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VO , OUTPUT VOLTAGE (5.0 V/DIV)
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 k
CL = 100 pF
TA = 25°C
CL = 100 pF
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 k
TA = 25°C
t, TIME (2.0 s/DIV)
CL = 0 pF
t, TIME (200 ns/DIV)
Figure 34. Non−inverting Amplifier Slew Rate
e n , INPUT NOISE VOLTAGE (100nV/DIV)
VO , OUTPUT VOLTAGE (5.0 V/DIV)
MC33077
Figure 35. Non−inverting Amplifier Overshoot
VCC = +15 V
VEE = −15 V
BW = 0.1 Hz to 10 Hz
TA = 25°C
See Noise Circuit
(Figure 36)
t, TIME (1.0 sec/DIV)
Figure 36. Low Frequency Noise Voltage
versus Time
http://onsemi.com
10
MC33077
APPLICATIONS INFORMATION
relation independent of its output voltage swing). Output
phase symmetry degradation in the more conventional PNP
and NPN transistor output stage was primarily due to the
inherent cut−off frequency mismatch of the PNP and NPN
transistors used (typically 10 MHz and 300 MHz,
respectively), causing considerable phase change to occur as
the output voltage changes. By eliminating the PNP in the
output, such phase change has been avoided and a very
significant improvement in output phase symmetry as well
as output swing has been accomplished.
The output swing improvement is most noticeable when
operation is with lower supply voltages (typically 30% with
± 5.0 V supplies). With a 10 k load, the output of the
amplifier can typically swing to within 1.0 V of the positive
rail (VCC), and to within 0.3 V of the negative rail (VEE),
producing a 28.7 Vpp signal from ±15 V supplies. Output
voltage swing can be further improved by using an output
pull−up resistor referenced to the VCC. Where output signals
are referenced to the positive supply rail, the pull−up resistor
will pull the output to VCC during the positive swing, and
during the negative swing, the NPN output transistor
collector will pull the output very near VEE. This
configuration will produce the maximum attainable output
signal from given supply voltages. The value of load
resistance used should be much less than any feedback
resistance to avoid excess loading and allow easy pull−up of
the output.
Output impedance of the amplifier is typically less than
50 at frequencies less than the unity gain crossover
frequency (see Figure 19). The amplifier is unity gain stable
with output capacitance loads up to 500 pF at full output
swing over the −55° to +125°C temperature range. Output
phase symmetry is excellent with typically 4°C total phase
change over a 20 V output excursion at 25°C with a 2.0 k
and 100 pF load. With a 2.0 k resistive load and no
capacitance loading, the total phase change is approximately
one degree for the same 20 V output excursion. With a
2.0 k and 500 pF load at 125°C, the total phase change is
typically only 10°C for a 20 V output excursion (see
Figure 28).
As with all amplifiers, care should be exercised to insure
that one does not create a pole at the input of the amplifier
which is near the closed loop corner frequency. This becomes
a greater concern when using high frequency amplifiers since
it is very easy to create such a pole with relatively small values
of resistance on the inputs. If this does occur, the amplifier’s
phase will degrade severely causing the amplifier to become
unstable. Effective source resistances, acting in conjunction
with the input capacitance of the amplifier, should be kept to
a minimum to avoid creating such a pole at the input (see
Figure 32). There is minimal effect on stability where the
created input pole is much greater than the closed loop corner
frequency. Where amplifier stability is affected as a result of
a negative feedback resistor in conjunction with the
The MC33077 is designed primarily for its low noise, low
offset voltage, high gain bandwidth product and large output
swing characteristics. Its outstanding high frequency
gain/phase performance make it a very attractive amplifier for
high quality preamps, instrumentation amps, active filters and
other applications requiring precision quality characteristics.
The MC33077 utilizes high frequency lateral PNP input
transistors in a low noise bipolar differential stage driving a
compensated Miller integration amplifier. Dual−doublet
frequency compensation techniques are used to enhance the
gain bandwidth product. The output stage uses an all NPN
transistor design which provides greater output voltage
swing and improved frequency performance over more
conventional stages by using both PNP and NPN transistors
(Class AB). This combination produces an amplifier with
superior characteristics.
Through precision component matching and innovative
current mirror design, a lower than normal temperature
coefficient of input offset voltage (2.0 V/°C as opposed to
10 V/°C), as well as low input offset voltage, is accomplished.
The minimum common mode input range is from 1.5 V
below the positive rail (VCC) to 1.5 V above the negative rail
(VEE). The inputs will typically common mode to within
1.0 V of both negative and positive rails though degradation
in offset voltage and gain will be experienced as the common
mode voltage nears either supply rail. In practice, though not
recommended, the input voltage may exceed VCC by
approximately 3.0 V and decrease below the VEE by
approximately 0.6 V without causing permanent damage to
the device. If the input voltage on either or both inputs is less
than approximately 0.6 V, excessive current may flow, if not
limited, causing permanent damage to the device.
The amplifier will not latch with input source currents up
to 20 mA, though in practice, source currents should be
limited to 5.0 mA to avoid any parametric damage to the
device. If both inputs exceed VCC, the output will be in the
high state and phase reversal may occur. No phase reversal
will occur if the voltage on one input is within the common
mode range and the voltage on the other input exceeds VCC.
Phase reversal may occur if the input voltage on either or
both inputs is less than 1.0 V above the negative rail. Phase
reversal will be experienced if the voltage on either or both
inputs is less than VEE.
Through the use of dual−doublet frequency compensation
techniques, the gain bandwidth product has been greatly
enhanced over other amplifiers using the conventional
single pole compensation. The phase and gain error of the
amplifier remains low to higher frequencies for fixed
amplifier gain configurations.
With the all NPN output stage, there is minimal swing loss
to the supply rails, producing superior output swing, no
crossover distortion and improved output phase symmetry
with output voltage excursions (output phase symmetry
being the amplifiers ability to maintain a constant phase
http://onsemi.com
11
MC33077
of the low noise characteristics of the amplifier. Thermal
noise (Johnson Noise) of a resistor is generated by
thermally−charged carriers randomly moving within the
resistor creating a voltage. The RMS thermal noise voltage
in a resistor can be calculated from:
amplifier’s input capacitance, creating a pole near the closed
loop corner frequency, lead capacitor compensation
techniques (lead capacitor in parallel with the feedback
resistor) can be employed to improve stability. The feedback
resistor and lead capacitor RC time constant should be larger
than that of the uncompensated input pole frequency. Having
a high resistance connected to the noninverting input of the
amplifier can create a like instability problem. Compensation
for this condition can be accomplished by adding a lead
capacitor in parallel with the noninverting input resistor of
such a value as to make the RC time constant larger than the
RC time constant of the uncompensated input resistor acting
in conjunction with the amplifiers input capacitance.
For optimum frequency performance and stability, careful
component placement and printed circuit board layout
should be exercised. For example, long unshielded input or
output leads may result in unwanted input output coupling.
In order to reduce the input capacitance, the body of resistors
connected to the input pins should be physically close to the
input pins. This not only minimizes the input pole creation
for optimum frequency response, but also minimizes
extraneous signal “pickup” at this node. Power supplies
should be decoupled with adequate capacitance as close as
possible to the device supply pin.
In addition to amplifier stability considerations, input
source resistance values should be low to take full advantage
Enr = / 4k TR × BW
where:
k = Boltzmann’s Constant (1.38 × 10−23 joules/k)
T = Kelvin temperature
R = Resistance in ohms
BW = Upper and lower frequency limit in Hertz.
By way of reference, a 1.0 k resistor at 25°C will
produce a 4.0 nV/ √ Hz of RMS noise voltage. If this resistor
is connected to the input of the amplifier, the noise voltage
will be gained−up in accordance to the amplifier’s gain
configuration. For this reason, the selection of input source
resistance for low noise circuit applications warrants serious
consideration. The total noise of the amplifier, as referred to
its inputs, is typically only 4.4 nV/ √ Hz at 1.0 kHz.
The output of any one amplifier is current limited and thus
protected from a direct short to ground, However, under such
conditions, it is important not to allow the amplifier to exceed
the maximum junction temperature rating. Typically for
±15 V supplies, any one output can be shorted continuously
to ground without exceeding the temperature rating.
0.1 F
10
100 k
−
D.U.T.
+
2.0 k
+
1/2
4.7 F
4.3 k
MC33077
−
100 k
Voltage Gain = 50,000
22 F
Scope × 1
Rin = 1.0 M
2.2 F
110 k
24.3 k
0.1 F
Note: All capacitors are non−polarized.
Figure 37. Voltage Noise Test Circuit
(0.1 Hz to 10 Hzp−p)
http://onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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