MC33102
Two-State,
Micropower Operational
Amplifier
The MC33102 dual operational amplifier is an innovative design
concept that has two separate states, a sleep mode and an awake mode.
In sleep mode, the amplifier is active and waiting for an input signal.
When a signal is applied causing the amplifier to source or sink
160 mA (typically) to the load, it will automatically switch to the
awake mode which offers higher slew rate, gain bandwidth, and drive
capability.
• Two States: “sleep mode” (Micropower) and “awake mode”
(High Performance)
• Switches from Sleep Mode to Awake Mode in 4.0 ms when Output
Current Exceeds the Threshold Current (RL = 600 W)
• Independent Sleep Mode Function for Each Op Amp
• Standard Pinouts − No Additional Pins or Components Required
• Sleep Mode State − Can Be Used in the Low Current Idle State as a
Fully Functional Micropower Amplifier
• Automatic Return to Sleep Mode when Output Current Drops Below
Threshold
• No Deadband/Crossover Distortion; as Low as 1.0 Hz in the Awake
Mode
• Drop−in Replacement for Many Other Dual Op Amps
• ESD Clamps on Inputs Increase Reliability without Affecting Device
Operation
http://onsemi.com
MARKING
DIAGRAMS
8
MC33102P
AWL
YYWW
PDIP−8
P SUFFIX
CASE 626
8
1
1
8
SO−8
D SUFFIX
CASE 751
8
1
33102
ALYW
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
TYPICAL SLEEP MODE/AWAKE MODE PERFORMANCE
Characteristic
Output 1
Sleep
Mode
(Typical)
Awake Mode
(Typical)
Unit
45
750
mA
Low Current Drain
2
Low Input Offset Voltage
0.15
0.15
mV
High Output Current Capability
0.15
50
mA
Low T.C. of Input Offset Voltage
1.0
1.0
mV/°C
High Gain Bandwidth (@ 20 kHz)
0.33
4.6
MHz
High Slew Rate
0.16
1.7
V/ms
28
9.0
nV/ √Hz
Low Noise (@ 1.0 kHz)
Inputs 1
VEE
August, 2011 − Rev. 3
1
3
7 Output 2
1
6
2
4
5
Inputs 2
(Dual, Top View)
ORDERING INFORMATION
Device
Package
Shipping
MC33102D
SO−8
98 Units/Rail
MC33102DR2
SO−8
2500 Tape & Reel
PDIP−8
50 Units/Rail
MC33102P
© Semiconductor Components Industries, LLC, 2011
8 VCC
1
Publication Order Number:
MC33102/D
MC33102
Simplified Block Diagram
Current
Threshold
Detector
Fractional
Load Current
Detector
Awake to
Sleep Mode
Delay Circuit
IHysteresis
% of IL
Buffer
IL
Vin
Op Amp
IBias
Sleep Mode
Current
Regulator
Buffer
CStorage
Iref
IEnable
Vout
RL
Enable
Awake Mode
Current
Regulator
Isleep
Iawake
MAXIMUM RATINGS
Ratings
Symbol
Value
Unit
VS
+ 36
V
VIDR
VIR
Note 1
V
Output Short Circuit Duration (Note 2)
tSC
Note 2
sec
Maximum Junction Temperature
Storage Temperature
TJ
Tstg
+150
−65 to +150
°C
Maximum Power Dissipation
PD
Note 2
mW
Supply Voltage (VCC to VEE)
Input Differential Voltage Range
Input Voltage Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (refer to Figure 1).
http://onsemi.com
2
MC33102
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V)
Sleep Mode
TA = +25°C
TA = −40° to +85°C
Awake Mode
TA = +25°C
TA = −40° to +85°C
2
⎪VIO⎪
Input Offset Voltage Temperature Coefficient
(RS = 50 W, VCM = 0 V, VO = 0 V)
TA = −40° to +85°C (Sleep Mode and Awake Mode)
3
Input Bias Current (VCM = 0 V, VO = 0 V)
Sleep Mode
TA = +25°C
TA = −40° to +85°C
Awake Mode
TA = +25°C
TA = −40° to +85°C
4, 6
−
Common Mode Input Voltage Range
(ΔVIO = 5.0 mV, VO = 0 V)
Sleep Mode and Awake Mode
5
Large Signal Voltage Gain
Sleep Mode (RL = 1.0 MW)
TA = +25°C
TA = −40° to +85°C
Awake Mode (VO = ±10 V, RL = 600 W)
TA = +25°C
TA = −40° to +85°C
7
Typ
Max
−
−
0.15
−
2.0
3.0
−
−
0.15
−
2.0
3.0
ΔVIO/ΔT
mV/°C
1.0
−
IIB
nA
−
−
8.0
−
50
60
−
−
100
−
500
600
nA
⎪IIO⎪
−
−
0.5
−
5.0
6.0
−
−
5.0
−
50
60
VICR
V
−13
−
−14.8
+14.2
−
+13
AVOL
kV/V
25
15
200
−
−
−
50
25
700
−
−
−
8, 9, 10
Common Mode Rejection (VCM = ±13 V)
Sleep Mode and Awake Mode
11
Power Supply Rejection (VCC/VEE = +15 V/−15 V,
5.0 V/−15 V, +15 V/−5.0 V)
Sleep Mode and Awake Mode
12
V
VO +
VO −
+13.5
−
+14.2
−14.2
−
−13.5
VO +
VO −
VO +
VO −
+12.5
−
+13.3
−
+13.6
−13.6
+14
−14
−
−12.5
−
−13.3
VO +
VO −
+1.1
−
+1.6
−1.6
−
−1.1
80
90
−
V
CMR
dB
PSR
dB
80
http://onsemi.com
3
Unit
mV
−
Input Offset Current (VCM = 0 V, VO = 0 V)
Sleep Mode
TA = +25°C
TA = −40° to +85°C
Awake Mode
TA = +25°C
TA = −40° to +85°C
Output Voltage Swing (VID = ±1.0 V)
Sleep Mode (VCC = +15 V, VEE = −15 V)
RL = 1.0 MW
RL = 1.0 MW
Awake Mode (VCC = +15 V, VEE = −15 V)
RL = 600 W
RL = 600 W
RL = 2.0 kW
RL = 2.0 kW
Awake Mode (VCC = +2.5 V, VEE = −2.5 V)
RL = 600 W
RL = 600 W
Min
100
−
MC33102
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Output Transition Current
Sleep Mode to Awake Mode (Source/Sink)
(VS = ±15 V)
(VS = ± 2.5 V)
Awake Mode to Sleep Mode (Source/Sink)
(VS = ±15 V)
(VS = ± 2.5 V)
13, 14
Output Short Circuit Current (Awake Mode)
(VID = ±1.0 V, Output to Ground)
Source
Sink
15, 16
Power Supply Current (per Amplifier) (ACL = 1, VO = 0V)
Sleep Mode (VS = ±15 V)
TA = +25°C
TA = − 40° to +85°C
Sleep Mode (VS = ± 2.5 V)
TA = +25°C
TA = − 40° to +85°C
Awake Mode (VS = ±15 V)
TA = +25°C
TA = − 40° to +85°C
Symbol
⎪ITH1⎪
⎪ITH2⎪
Min
http://onsemi.com
4
Max
Unit
mA
200
250
160
200
−
−
−
−
142
180
90
140
mA
⎪ISC⎪
50
50
17
Typ
110
110
−
−
ID
mA
−
−
45
48
65
70
−
−
38
42
65
−
−
−
750
800
800
900
MC33102
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Slew Rate (Vin = −5.0 V to +5.0 V, CL = 50 pF, AV = 1.0)
Sleep mode (RL = 1.0 MW)
Awake mode (RL = 600 W)
18
SR
Gain Bandwidth Product
Sleep mode (f = 10 kHz)
Awake mode (f = 20 kHz)
19
Sleep mode to Awake mode Transition Time
(ACL = 0.1, Vin = 0 V to +5.0 V)
RL = 600 W
RL = 10 kW
20, 21
Awake mode to Sleep mode Transition Time
22
Phase Margin
Sleep mode (RL = 100 kW, CL = 0 pF)
Awake mode (RL = 600 W, CL = 0 pF)
24, 26
Channel Separation (f = 100 Hz to 20 kHz)
Sleep mode and Awake mode
29
Power Bandwidth (Awake mode)
(VO = 10 Vpp, RL = 100 kW, THD ≤ 1%)
ttr2
AM
∅M
30
DC Output Impedance (VO = 0 V, AV = 10, IQ = 10 mA)
Sleep mode
Awake mode
31
RO
Rin
Differential Input Capacitance (VCM = 0 V)
Sleep mode
Awake mode
Cin
32
Equivalent Input Noise Current (f = 1.0 kHz)
Sleep mode
Awake mode
33
http://onsemi.com
5
0.16
1.7
−
−
0.25
3.5
0.33
4.6
−
−
en
in
Unit
V/ms
MHz
ms
−
−
4.0
15
−
−
−
1.5
−
−
−
200
2500
−
−
−
−
13
12
−
−
−
−
60
60
−
−
−
120
−
−
20
−
sec
kHz
dB
Degree
s
dB
kHz
THD
Differential Input Resistance (VCM = 0 V)
Sleep mode
Awake mode
Equivalent Input Noise Voltage (f = 1.0 kHz, RS = 100 W)
Sleep mode
Awake mode
0.10
1.0
CS
BWP
Total Harmonic Distortion (VO = 2.0 Vpp, AV = 1.0)
Awake mode (RL = 600 W)
f = 1.0 kHz
f = 10 kHz
f = 20 kHz
Max
ttr1
fU
23, 25
Typ
GBW
Unity Gain Frequency (Open Loop)
Sleep mode (RL = 100 kW, CL = 0 pF)
Awake mode (RL = 600 W, CL = 0 pF)
Gain Margin
Sleep mode (RL = 100 kW, CL = 0 pF)
Awake mode (RL = 600 W, CL = 0 pF)
Min
%
−
−
−
0.005
0.016
0.031
−
−
−
−
−
1.0 k
96
−
−
−
−
1.3
0.17
−
−
−
−
0.4
4.0
−
−
−
−
28
9.0
−
−
−
−
0.01
0.05
−
−
W
MW
pF
nV/ √Hz
pA/ √Hz
50
PERCENT OF AMPLIFIERS (%)
2500
2000
MC33102P
1500
MC33102D
500
0
-55 -40 -25
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
30
20
10
0
-1.0 -0.8
125
PERCENT OF AMPLIFIERS (%)
30
10.5
204 Amplifiers tested
from 3 wafer lots.
VCC = +15 V
VEE = -15 V
TA = - 40°C to 85°C
Percent Sleep mode
Percent Awake mode
25
20
15
10
5.0
-3.0 -2.0
-1.0
0
1.0
2.0
3.0
4.0
5.0
80
Awake mode
70
7.5
6.5
-15
-10
-5.0
0
5.0
10
VCM, COMMON MODE INPUT VOLTAGE (V)
Figure 3. Input Offset Voltage Temperature
Coefficient Distribution (MC33102D Package)
Figure 4. Input Bias Current versus
Common Mode Input Voltage
VCC
VCC-0.5
Awake mode
VEE+1.0
VEE+0.5
VCC = +15 V
VEE = -15 V
ΔVIO = 5.0 mV
Awake mode
Sleep mode
VEE
-55 -40 -25
0
25
50
85
125
60
15
100
10.0
Sleep mode
90
Sleep mode
8.5
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/°C)
VCC-1.0
0.8
100
VCC = +15 V
VEE = -15 V
TA = 25°C
9.5
I IB, SLEEPMODE INPUT BIAS CURRENT (nA)
VICR, INPUT COMMON MODE VOLTAGE RANGE (V)
0
-5.0 -4.0
-0.6 -0.4 -0.2
0 0.2
0.4 0.6
VIO, INPUT OFFSET VOLTAGE (mV)
1.0
Figure 2. Distribution of Input Offset Voltage
(MC33102D Package)
I IB, SLEEPMODE INPUT BIAS CURRENT (nA)
Figure 1. Maximum Power Dissipation
versus Temperature
35
204 Amplifiers tested
from 3 wafer lots.
VCC = +15 V
VEE = -15 V
TA = 25°C
Sleep mode
80
8.0
Awake mode
60
6.0
40
4.0
VCC = +15 V
VEE = -15 V
VCM = 0 V
2.0
0
-55 -40 -25
TA, AMBIENT TEMPERATURE (°C)
0
20
25
50
85
0
125
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Input Common Mode Voltage Range
versus Temperature
Figure 6. Input Bias Current versus Temperature
http://onsemi.com
6
I IB, AWAKEMODE INPUT BIAS CURRENT (nA)
1000
40
Percent Sleep mode
Percent Awake mode
I IB, AWAKEMODE INPUT BIAS CURRENT (nA)
PD(max), MAXIMUM POWER DISSIPATION (mW)
MC33102
130
35
TA = 25°C
VO, OUTPUT VOLTAGE (Vpp )
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
MC33102
120
Awake mode (RL = 1.0 MW)
110
Sleep mode (RL = 1.0 MW)
100
90
30
Sleep mode (RL = 1.0 MW)
25
20
Awake mode (RL = 600 W)
15
10
5
80
-55 -40 -25
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
0
125
0
VO, OUTPUT VOLTAGE SWING (Vpp)
VO, OUTPUT VOLTAGE (Vpp )
12
15
18
30
25
20
Sleep mode
(RL = 1.0 MW)
15
10
Awake mode
(RL = 600 W)
VCC = +15 V
VEE = -15 V
AV = +1.0
TA = 25°C
5.0
0
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
25
20
Awake mode
15
5.0
10
500 k
PSR, POWER SUPPLY REJECTION (dB)
80
Awake mode
60
Sleep mode
40
VCC = +15 V
VEE = -15 V
VCM = 0 V
ΔVCM = ± 1.5 V
TA = 25°C
1.0 k
10 k
100 k
100
1.0 k
RL, LOAD RESISTANCE TO GROUND (W)
10 k
Figure 10. Maximum Peak−to−Peak Output
Voltage Swing versus Load Resistance
100
100
VCC = +15 V
VEE = -15 V
f = 1.0 kHz
TA = 25°C
10
Figure 9. Output Voltage versus Frequency
CMR, COMMON MODE REJECTION (dB)
9.0
Figure 8. Output Voltage Swing
versus Supply Voltage
30
0
10
6.0
VCC, ⎜VEE⎪, SUPPLY VOLTAGE (V)
Figure 7. Open Loop Voltage Gain
versus Temperature
20
3.0
120
100
+PSR
Awake mode
80
-PSR
Awake mode
60
40
20
0
10
1.0 M
+PSR
Sleep mode
VCC = +15 V
VEE = -15 V
ΔVCC = ± 1.5 V
TA = 25°C
100
-PSR
Sleep mode
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 11. Common Mode Rejection
versus Frequency
Figure 12. Power Supply Rejection
versus Frequency
http://onsemi.com
7
1.0 M
MC33102
190
180
TA = 25°C
170
TA = - 55°C
160
150
TA = 125°C
3.0
6.0
9.0
12
15
TA = - 55°C
150
TA = 125°C
140
130
3.0
9.0
12
15
18
Figure 13. Sleep Mode to Awake Mode
Current Threshold versus Supply Voltage
Figure 14. Awake Mode to Sleep Mode
Current Threshold versus Supply Voltage
Sink
Source
60
VCC = +15 V
VEE = -15 V
VID = ± 1.0 V
RL < 10 W
Awake mode
0
3.0
6.0
9.0
⎜VO⎪, OUTPUT VOLTAGE (V)
12
15
150
140
Source
130
120
Sink
100
90
80
70
-55 -40 -25
50
0.8
Awake mode (mA)
0.6
Sleep mode (mA)
0.4
40
VCC = +15 V
VEE = -15 V
No Load
35
30
-55 -40 -25
0.2
0
125
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
125
2.0
0.20
SR, SLEW RATE (V/μ s)
1.0
I D , SUPPLY CURRENT PER AMPLIFIER (mA)
55
45
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
Figure 16. Output Short Circuit Current
versus Temperature
1.2
60
VCC = +15 V
VEE = -15 V
VID = ± 1.0 V
RL < 10 W
Awake mode
110
Figure 15. Output Short Circuit Current
versus Output Voltage
I D , SUPPLY CURRENT PER AMPLIFIER (μ A)
6.0
VCC, ⎜VEE⎪, SUPPLY VOLTAGE (V)
80
0
TA = 25°C
160
VCC, ⎜VEE⎪, SUPPLY VOLTAGE (V)
100
20
170
120
18
120
40
180
0.18
VCC = +15 V
VEE = -15 V
ΔVin = - 5.0 V to + 5.0 V
Awake mode (RL = 600 W)
1.8
0.16
1.6
0.14
1.4
0.12
1.2
Sleep mode (RL = 1.0 MW)
0.10
-55 -40 -25
Figure 17. Power Supply Current Per
Amplifier versus Temperature
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
1.0
125
Figure 18. Slew Rate versus Temperature
http://onsemi.com
8
SR, SLEW RATE (V/μ s)
140
⎮I SC⎮, OUTPUT SHORT CIRCUIT CURRENT (mA)
I TH2, CURRENT THRESHOLD ( μA)
190
⎮I SC⎮, OUTPUT SHORT CIRCUIT CURRENT (mA)
I TH1, CURRENT THRESHOLD ( μA)
200
MC33102
4.5
4.0
3.5
350
Sleep mode (kHz)
300
250
VCC = +15 V
VEE = -15 V
f = 20 kHz
200
-55 -40 -25
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
125
V P , PEAK VOLTAGE (1.0 V/DIV)
Awake mode (MHz)
GBW, GAIN BANDWIDTH PRODUCT (KHz)
GBW, GAIN BANDWIDTH PRODUCT (KHz)
5.0
RL = 10 k
t, TIME (5.0 ms/DIV)
Figure 19. Gain Bandwidth Product
versus Temperature
Figure 20. Sleep Mode to Awake Mode
Transition Time
t tr2 , TRANSITION TIME (SEC)
V P , PEAK VOLTAGE (1.0 V/DIV)
2.0
RL = 600 W
1.5
TA = 25°C
1.0
TA = - 55°C
0.5
TA = 125°C
0
3.0
6.0
t, TIME (2.0 ms/DIV)
Figure 21. Sleep Mode to Awake Mode
Transition Time
70
∅ m, PHASE MARGIN (DEG)
A m , GAIN MARGIN (dB)
11
5.0
10
Sleep mode
Sleep mode
13
7.0
18
Figure 22. Awake Mode to Sleep Mode
Transition Time versus Supply Voltage
15
9.0
9.0
12
15
VCC, ⎜VEE⎮, SUPPLY VOLTAGE (V)
Awake mode
VCC = +15 V
VEE = -15 V
RT = R1 + R2
VO = 0 V
TA = 25°C
R1
60
VCC = +15 V
VEE = -15 V
RT = R1 + R2
VO = 0 V
TA = 25°C
50
40
20
R1
10
VO
R2
VO
R2
0
100
1.0 k
10 k
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Awake mode
30
10
Figure 23. Gain Margin versus Differential
Source Resistance
100
1.0 k
10 k
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
100 k
Figure 24. Phase Margin versus Differential
Source Resistance
http://onsemi.com
9
MC33102
70
∅ m, PHASE MARGIN (DEGREES)
12
Sleep mode
10
8.0
Awake mode
6.0
VCC = +15 V
VEE = -15 V
VO = 0 V
4.0
2.0
0
10
100
CL, OUTPUT LOAD CAPACITANCE (pF)
VCC = +15 V
VEE = -15 V
VO = 0 V
60
50
40
Awake mode
30
20
Sleep mode
10
0
1.0 k
10
100
1.0 k
CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 25. Open Loop Gain Margin versus
Output Load Capacitance
120
2A
10
160
1B
TA = 25°C
RL = 1.0 MW
CL < 10 pF
Sleep mode
-10
-30
10 k
2B
200
100 k
1.0 M
f, FREQUENCY (Hz)
AV, VOLTAGE GAIN (dB)
80
1A
30
70
40
1A) Phase, VS = ±18 V
2A) Phase, VS = ± 2.5 V
1B) Gain, VS = ±18 V
2B) Gain, VS = ± 2.5 V
50
Figure 26. Phase Margin versus
Output Load Capacitance
θ , EXCESS PHASE (DEGREES)
AV, VOLTAGE GAIN (dB)
70
50
1A
30
10
2B
-30
30 k
120
100
80
60
VCC = +15 V
VEE = -15 V
RL = 600 W
Awake mode
20
0
100
1.0 k
10 k
160
1B
100 k
200
240
10 M
1.0 M
f, FREQUENCY (Hz)
Figure 28. Awake Mode Voltage Gain and
Phase versus Frequency
THD, TOTAL HARMONIC DISTORTION (%)
CS, CHANNEL SEPARATION (dB)
140
120
1A) Phase, VS = ±18 V
2A) Phase, VS = ± 2.5 V
1B) Gain, VS = ±18 V
2B) Gain, VS = ± 2.5 V
-10
240
10 M
40
TA = 25°C
RL = 600 W
CL < 10 pF
80
Awake mode
2A
Figure 27. Sleep Mode Voltage Gain and
Phase versus Frequency
40
10 k
θ , EXCESS PHASE (DEGREES)
Am, OPEN LOOP GAIN MARGIN (dB)
14
100
VCC = +15 V
VEE = -15 V
10 RL = 600 W
AV = +1000
1.0
AV = +100
0.1
AV = +10
AV = +1.0
0.01
0.001
100 k
VO = 2.0 Vpp
TA = 25°C
Awake mode
100
1.0 k
10 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 29. Channel Separation versus Frequency
Figure 30. Total Harmonic Distortion
versus Frequency
http://onsemi.com
10
100 k
ZO , OUTPUT IMPEDANCE ()
Ω
250
200
150
VCC = +15 V
VEE = -15 V
VCM = 0 V
VO = 0 V
TA = 25°C
Awake mode
AV = 100
100
50
AV = 10
AV = 1000
AV = 1.0
0
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
10 M
en, INPUT REFERRED NOISE VOLTAGE (nV/ Hz)
MC33102
100
VCC = +15 V
VEE = -15 V
TA = 25°C
50
Sleep mode
Awake mode
10
5.0
10
Figure 31. Awake Mode Output Impedance
versus Frequency
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
70
VO
RS
os, PERCENT OVERSHOOT (%)
VCC = +15 V
0.8 VEE = -15 V
TA = 25°C
0.6 (RS = 10 k)
0.4
Awake mode
0.2
Sleep mode
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
VCC = +15 V
60 VEE = -15 V
TA = 25°C
50
40
Sleep mode
(RL = 1.0 MW)
30
20
Awake mode
(RL = 600 W)
10
0
10
100
CL, LOAD CAPACITANCE (pF)
1.0 k
Figure 34. Percent Overshoot
versus Load Capacitance
RL = 600 W
V P , PEAK VOLTAGE (5.0 V/DIV)
Figure 33. Current Noise versus Frequency
V P , PEAK VOLTAGE (5.0 V/DIV)
i n, INPUT NOISE CURRENT (pA/ Hz)
100
Figure 32. Input Referred Noise Voltage
versus Frequency
1.0
0.1
10
VO
RL = R
t, TIME (50 ms/DIV)
t, TIME (5.0 ms/DIV)
Figure 35. Sleep Mode Large Signal
Transient Response
Figure 36. Awake Mode Large Signal
Transient Response
http://onsemi.com
11
MC33102
RL = 600 W
CL = 0 pF
V P , PEAK VOLTAGE (50 mV/DIV)
V P , PEAK VOLTAGE (50 mV/DIV)
RL = R
CL = 0 pF
t, TIME (50 ms/DIV)
t, TIME (50 ms/DIV)
Figure 37. Sleep Mode Small Signal
Transient Response
Figure 38. Awake Mode Small Signal
Transient Response
CIRCUIT INFORMATION
The awake mode uses higher drain current to provide a
The MC33102 was designed primarily for applications
high slew rate, gain bandwidth, and output current
where high performance (which requires higher current
capability. In the awake mode, this amplifier can drive 27
drain) is required only part of the time. The two−state feature
of this op amp enables it to conserve power during idle times,
Vpp into a 600 W load with VS = ±15 V.
yet be powered up and ready for an input signal. Possible
An internal delay circuit is used to prevent the amplifier
applications include laptop computers, automotive, cordless
from returning to the sleep mode at every zero crossing. This
phones, baby monitors, and battery operated test equipment.
delay circuit also eliminates the crossover distortion
Although most applications will require low power
commonly found in micropower amplifiers. This amplifier
consumption, this device can be used in any application
can process frequencies as low as 1.0 Hz without the
where better efficiency and higher performance is needed.
amplifier returning to sleep mode, depending on the load.
The sleep mode amplifier has two states; a sleep mode and
The first stage PNP differential amplifier provides low
an awake mode. In the sleep mode state, the amplifier is
noise performance in both the sleep and awake modes, and
active and functions as a typical micropower op amp. When
an all NPN output stage provides symmetrical source and
a signal is applied to the amplifier causing it to source or sink
sink AC frequency response.
sufficient current (see Figure 13), the amplifier will
automatically switch to the awake mode. See Figures 20 and
21 for transition times with 600 W and 10 kW loads.
APPLICATIONS INFORMATION
The MC33102 will begin to function at power supply
The amplifier is designed to switch from sleep mode to
voltages as low as VS = ±1.0 V at room temperature. (At this
awake mode whenever the output current exceeds a preset
voltage, the output voltage swing will be limited to a few
current threshold (ITH) of approximately 160 mA. As a result,
hundred millivolts.) The input voltages must range between
the output switching threshold voltage (VST) is controlled by
VCC and VEE supply voltages as shown in the maximum
the output loading resistance (RL). This loading can be a load
rating table. Specifically, allowing the input to go more
resistor, feedback resistors, or both. Then:
negative than 0.3 V below VEE may cause product
VST = (160 mA) × RL
damage. Also, exceeding the input common mode voltage
Large valued load resistors require a large output voltage
range on either input may cause phase reversal, even if the
to switch, but reduce unwanted transitions to the awake
inputs are between VCC and VEE.
mode. For instance, in cases where the amplifier is
When power is initially applied, the part may start to
connected with a large closed loop gain (ACL), the input
operate in the awake mode. This is because of the currents
offset voltage (VIO) is multiplied by the gain at the output
generated due to charging of internal capacitors. When this
and could produce an output voltage exceeding VST with no
occurs and the sleep mode state is desired, the user will have
input signal applied.
to wait approximately 1.5 seconds before the device will
Small values of RL allow rapid transition to the awake
switch back to the sleep mode. To prevent this from
mode because most of the transition time is consumed
occurring, ramp the power supplies from 1.0 V to full
slewing in the sleep mode until VST is reached (see
supply. Notice that the device is more prone to switch into
Figures 20, 21). The output switching threshold voltage VST
the awake mode when VEE is adjusted than with a similar
is higher for larger values of RL, requiring the amplifier to
change in VCC.
http://onsemi.com
12
MC33102
To minimize this problem, a resistor may be added in series
with the output of the device (inserted as close to the device
as possible) to isolate the op amp from both parasitic and
load capacitance.
The awake mode to sleep mode transition time is
controlled by an internal delay circuit, which is necessary to
prevent the amplifier from going to sleep during every zero
crossing. This time is a function of supply voltage and
temperature as shown in Figure 22.
Gain bandwidth product (GBW) in both modes is an
important system design consideration when using a sleep
mode amplifier. The amplifier has been designed to obtain
the maximum GBW in both modes. “Smooth” AC
transitions between modes with no noticeable change in the
amplitude of the output voltage waveform will occur as long
as the closed loop gains (ACL) in both modes are
substantially equal at the frequency of operation. For
smooth AC transitions:
slew longer in the slower sleep mode state before switching
to the awake mode.
The transition time (ttr1) required to switch from sleep to
awake mode is:
t tr1 + t D + I TH(R LńSR sleepmode)
Where:
tD = Amplifier delay (t1.0 ms)
ITH = Output threshold current for more transition
(160 mA)
RL = Load resistance
Srsleep mode = Sleep mode slew rate (0.16 V/ms)
Although typically 160 mA, ITH varies with supply
voltage and temperature. In general, any current loading on
the output which causes a current greater than ITH to flow
will switch the amplifier into the awake mode. This includes
transition currents such as those generated by charging load
capacitances. In fact, the maximum capacitance that can be
driven while attempting to remain in the sleep mode is
approximately 1000 pF.
(ACLsleep mode) (BW) < GBWsleep mode
Where:
ACLsleep mode = Closed loop gain in the sleep mode
BW = The required system bandwidth or operating
frequency
CL(max) = ITH/Srsleep mode
= 160 mA/(0.16 V/ms)
= 1000 pF
Any electrical noise seen at the output of the MC33102
may also cause the device to transition to the awake mode.
TESTING INFORMATION
To determine if the MC33102 is in the awake mode or the
sleep mode, the power supply currents (ID+ and ID−) must
be measured. When the magnitude of either power supply
current exceeds 400 mA, the device is in the awake mode.
When the magnitudes of both supply currents are less than
400 mA, the device is in the sleep mode. Since the total
supply current is typically ten times higher in the awake
mode than the sleep mode, the two states are easily
distinguishable.
The measured value of ID+ equals the ID of both devices
(for a dual op amp) plus the output source current of device
A and the output source current of device B. Similarly, the
measured value of ID− is equal to the ID− of both devices plus
the output sink current of each device. Iout is the sum of the
currents caused by both the feedback loop and load
resistance. The total Iout needs to be subtracted from the
measured ID to obtain the correct ID of the dual op amp.
An accurate way to measure the awake mode Iout current
on automatic test equipment is to remove the Iout current on
both Channel A and B. Then measure the ID values before
the device goes back to the sleep mode state. The transition
will take typically 1.5 seconds with ±15 V power supplies.
The large signal sleep mode testing in the characterization
was accomplished with a 1.0 MW load resistor which
ensured the device would remain in sleep mode despite large
voltage swings.
http://onsemi.com
13
MC33102
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE M
D
A
D1
E
8
5
E1
1
4
NOTE 5
F
c
E2
END VIEW
TOP VIEW
NOTE 3
e/2
A
L
A1
C
SEATING
PLANE
E3
e
8X
SIDE VIEW
b
0.010
M
C A
END VIEW
http://onsemi.com
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RESTRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
A1
b
C
D
D1
E
E1
E2
E3
e
L
INCHES
NOM
MAX
−−−− 0.210
−−−− −−−−
0.018 0.022
0.010 0.014
0.365 0.400
−−−− −−−−
0.310 0.325
0.250 0.280
0.300 BSC
−−−−
−−−− 0.430
0.100 BSC
0.115 0.130 0.150
MIN
−−−−
0.015
0.014
0.008
0.355
0.005
0.300
0.240
MILLIMETERS
MIN
NOM
MAX
−−−−
−−−−
5.33
0.38
−−−− −−−−
0.35
0.46
0.56
0.20
0.25
0.36
9.02
9.27 10.02
0.13
−−−− −−−−
7.62
7.87
8.26
6.10
6.35
7.11
7.62 BSC
−−−−
−−−− 10.92
2.54 BSC
2.92
3.30
3.81
MC33102
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
15
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC33102/D
工商网监
湘ICP备2023018690号
