MC33171, 2, 4,
NCV33172, 4
Operational Amplifiers,
Single Supply 3.0 V to 44 V,
Low Power
Quality bipolar fabrication with innovative design concepts are
employed for the MC33171/72/74, NCV33172/74 series of
monolithic operational amplifiers. These devices operate at 180 mA
per amplifier and offer 1.8 MHz of gain bandwidth product and
2.1 V/ms slew rate without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common
mode input voltage includes ground potential (VEE). With a
Darlington input stage, these devices exhibit high input resistance, low
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output
voltage swing, provides high capacitance drive capability, excellent
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33171/72/74, NCV33172/74 are specified over the
industrial/automotive temperature ranges. The complete series of
single, dual and quad operational amplifiers are available in plastic as
well as the surface mount packages.
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PDIP−8
P SUFFIX
CASE 626
8
1
SO−8
D, VD SUFFIX
CASE 751
8
1
PDIP−14
P, VP SUFFIX
CASE 646
14
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Supply Current: 180 mA (Per Amplifier)
Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V
Wide Input Common Mode Range, Including Ground (VEE)
Wide Bandwidth: 1.8 MHz
High Slew Rate: 2.1 V/ms
Low Input Offset Voltage: 2.0 mV
Large Output Voltage Swing: −14.2 V to +14.2 V
(with ±15 V Supplies)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.03%
Excellent Phase Margin: 60°
Excellent Gain Margin: 15 dB
Output Short Circuit Protection
ESD Diodes Provide Input Protection for Dual and Quad
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 13
1
SO−14
D, VD SUFFIX
CASE 751A
14
1
14
1
TSSOP−14
DTB SUFFIX
CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 10 of this data sheet.
Publication Order Number:
MC33171/D
MC33171, 2, 4, NCV33172, 4
PIN CONNECTIONS
SINGLE
QUAD
Output 1
Offset Null
1
8
NC
Inv. Input
2
7
VCC
Noninv. Input
3
6
Output
VEE
4
5
Offset Null
+
Inputs 1
1
14
2
13
3
VCC
Inputs 2
6
Output 2
DUAL
1
4
+
4
5
(Single, Top View)
+
Inputs 4
12
11
+
2
-
3
7
+
-
Output 4
VEE
10
9
8
Inputs 3
Output 3
(Top View)
Output 1
Inputs 1
1
2
3
VEE
+
4
1
2 +
8
VCC
7
Output 2
6
Inputs 2
5
(Top View)
VCC
Q3
Q4
Q5
Q6
Q7
Q1
Q17
Q2
R1
R2
C1
D2
Bias
-
Q8
Q9
Q10
Q18
R6
Q11
Inputs
R7
Output
R8
+
C2
D3
Q19
Q13
Q14
Q15
Q12
Q16
Current
Limit
D1
R5
R3
R4
VEE/GND
Offset Null
(MC33171)
Figure 1. Representative Schematic Diagram
(Each Amplifier)
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2
MC33171, 2, 4, NCV33172, 4
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC/VEE
±22
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Input Voltage Range
VIR
(Note 1)
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Operating Ambient Temperature Range
TA
(Note 3)
°C
Supply Voltage
Operating Junction Temperature
TJ
+150
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Symbol
Characteristics
Input Offset Voltage (VCM = 0 V)
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)
Min
Typ
Max
−
−
−
2.0
2.5
−
4.5
5.0
6.5
−
10
−
−
−
20
−
100
200
−
−
5.0
−
20
40
50
25
500
−
−
−
3.5
13.6
13.3
4.3
14.2
−
−
−
−
−
−
−
0.05
−14.2
−
0.15
−13.6
−13.3
VIO
DVIO/DT
Average Temperature Coefficient of Offset Voltage
Input Bias Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh (Note 3)
IIB
Input Offset Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh (Note 3)
IIO
Large Signal Voltage Gain (VO = ±10 V, RL = 10 k)
TA = +25°C
TA = Tlow to Thigh (Note 3)
AVOL
Output Voltage Swing
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
VOH
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
VOL
Output Short Circuit (TA = +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
mV
mV/°C
nA
nA
V/mV
V
ISC
mA
3.0
15
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh (Note 3)
Unit
5.0
27
−
−
VICR
V
VEE to (VCC −1.8)
VEE to (VCC −2.2)
Common Mode Rejection Ratio (RS ≤ 10 k), TA = +25°C
CMRR
80
90
−
dB
Power Supply Rejection Ratio (RS = 100 W), TA = +25°C
PSRR
80
100
−
dB
Power Supply Current (Per Amplifier)
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)
ID
−
−
−
180
220
−
250
250
300
mA
1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
Thigh = +85°C
3. MC3317x
Tlow = −40°C
Thigh = +125°C
MC3317xV, NCV3317x
Tlow = −40°C
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3
MC33171, 2, 4, NCV33172, 4
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Symbol
Characteristics
Slew Rate (Vin = −10 V to +10 V, RL = 10 k, CL = 100 pF)
AV +1
AV −1
Min
Typ
Max
SR
Unit
V/ms
Gain Bandwidth Product (f = 100 kHz)
GBW
Power Bandwidth
AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%
BWp
1.6
−
2.1
2.1
−
−
1.4
1.8
−
−
35
−
−
−
60
45
−
−
−
−
15
5.0
−
−
MHz
kHz
Phase Margin
RL = 10 k
RL = 10 k, CL = 100 pF
fm
Gain Margin
RL = 10 k
RL = 10 k, CL = 100 pF
Am
Equivalent Input Noise Voltage
RS = 100 W, f = 1.0 kHz
en
−
32
−
nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz)
In
−
0.2
−
pA/ √ Hz
−
300
−
−
0.8
−
−
0.03
−
Differential Input Resistance
Vcm = 0 V
Rin
Input Capacitance
Cin
Total Harmonic Distortion
AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
Deg
dB
MW
THD
pF
%
Channel Separation (f = 10 kHz)
CS
−
120
−
dB
Open Loop Output Impedance (f = 1.0 MHz)
zo
−
100
−
W
0
VCC/VEE = ±1.5 V to ± 22 V
DVIO = 5.0 mV
VCC
V,
sat OUTPUT SATURATION VOLTAGE (V)
V
ICR , INPUT COMMON MODE VOLTAGE RANGE (V)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
-0.8
-1.6
-2.4
0.1
VEE
0
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0
VCC/VEE = ± 5.0 V to ± 22 V
TA = 25°C
VCC
-1.0
Source
1.0
Sink
VEE
0
0
Figure 2. Input Common Mode Voltage Range
versus Temperature
1.0
2.0
3.0
IL, LOAD CURRENT (±mA)
Figure 3. Split Supply Output Saturation
versus Load Current
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4
4.0
70
20
Phase
Margin
= 58°
10
VCC/VEE = ±15 V
RL = 10 k
Vout = 0 V
TA = 25°C
1 - Phase
2 - Phase, CL = 100 pF
3 - Gain
4 - Gain, CL = 100 pF
0
-10
-20
-30
100 k
Gain
1 Margin
= 15 dB
2
4
140
160
180
3
200
70
φ m, PHASE MARGIN (DEGREES)
120
60
60
VCC/VEE = ±15 V
AVOL = +1.0
RL = 10 k
DVO = 20 mVpp
TA = 25°C
fm
50
40
30
%
20
20
10
10
220
1.0 M
f, FREQUENCY (Hz)
0
10 M
10
20
50
100
200
CL, LOAD CAPACITANCE (pF)
500
0
1.0 k
Figure 5. Phase Margin and Percent
Overshoot versus Load Capacitance
5.0 ms/DIV
GBW
1.1
50 mV/DIV
VCC/VEE = ±15 V
RL = 10 k
1.2
0
10 V/DIV
1.3
GBW AND SR (NORMALIZED)
40
30
Figure 4. Open Loop Voltage Gain and
Phase versus Frequency
0
VCC/VEE = ±15 V
VCM = 0 V
VO = 0 V
DIO = ±0.5 mA
TA = 25°C
1.0
SR
0.9
0.8
0.7
-55
-25
0
25
50
75
100
125
5.0 ms/DIV
TA, AMBIENT TEMPERATURE (°C)
140
120
100
VCC/VEE = ±15 V
AV = +1.0
RL = 10 k
CL = 100 pF
TA = 25°C
80
Figure 7. Small and Large Signal
Transient Response
I,
D I,
CC POWER SUPPLY CURRENT (mA)
Figure 6. Normalized Gain Bandwidth Product
and Slew Rate versus Temperature
zo , OUTPUT IMPEDANCE ()
Ω
50
%, PERCENT OVERSHOOT
3
0
φ , EXCESS PAHSE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
MC33171, 2, 4, NCV33172, 4
AV = 1000
AV = 100
60
40
AV = 10
AV = 1.0
20
0
200
2.0 k
20 k
f, FREQUENCY (Hz)
200 k
2.0 M
1.1
1. TA = -55°C
2. TA = 25°C
0.9 3. TA = 125°C
2
3
0.7
Dual
1
2
3
Single
1
2
3
0.5
0.3
0.1
0
Figure 8. Output Impedance and Frequency
1
Quad
5.0
10
15
VCC/VEE, SUPPLY VOLTAGE (±V)
20
Figure 9. Supply Current versus Supply Voltage
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5
25
MC33171, 2, 4, NCV33172, 4
APPLICATIONS INFORMATION − CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
0.8 V of the positive rail (VCC) and negative rail (VEE),
providing a 28.4 Vpp swing from ±15 V supplies. This large
output swing becomes most noticeable at lower supply
voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, the VBE of the NPN pull−up
transistor Q17, and the voltage drop associated with the
short circuit resistance, R5. For sink currents less than
0.4 mA, the negative swing is limited by the saturation
voltage of the pull−down transistor Q15, and the voltage
drop across R4 and R5. For small valued sink currents, the
above voltage drops are negligible, allowing the negative
swing voltage to approach within millivolts of VEE. For sink
currents (> 0.4 mA), diode D3 clamps the voltage across R4.
Thus the negative swing is limited by the saturation voltage
of Q15, plus the forward diode drop of D3 (≈VEE +1.0 V).
Therefore an unprecedented peak−to−peak output voltage
swing is possible for a given supply voltage as indicated by
the output swing specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to VCC during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull−up
capability.
Because the PNP output emitter−follower transistor has
been eliminated, the MC33171/72/74 family offers a 15 mA
minimum current sink capability, typically to an output
voltage of (VEE +1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for current switching
applications.
In addition, the all NPN transistor output stage is
inherently faster than PNP types, contributing to the bipolar
amplifier’s improved gain bandwidth product. The
associated high frequency low output impedance (200 W typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
400 pF without oscillation in the noninverting unity gain
configuration. The 60° phase margin and 15 dB gain margin,
as well as the general gain and phase characteristics, are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The AC
characteristics of the MC33171/72/74 family also allow
excellent active filter capability, especially for low voltage
single supply applications.
Although the single supply specification is defined at
5.0 V, these amplifiers are functional to at least 3.0 V @
25°C. However slight changes in parametrics such as
bandwidth, slew rate, and DC gain may occur.
Although the bandwidth, slew rate, and settling time of the
MC33171/72/74 amplifier family is similar to low power op
amp products utilizing JFET input devices, these amplifiers
offer additional advantages as a result of the PNP transistor
differential inputs and an all NPN transistor output stage.
Because the input common mode voltage range of this
input stage includes the VEE potential, single supply
operation is feasible to as low as 3.0 V with the common
mode input voltage at ground potential.
The input stage also allows differential input voltages up
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VCC and VEE supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to 5.0 mA of current from VEE through either inputs’
clamping diode without damage or latching, but phase
reversal may again occur. If at least one input is within the
common mode input voltage range and the other input is
within the maximum input voltage range, no phase reversal
will occur. If both inputs exceed the upper common mode
input voltage limit, the output will be forced to its lowest
voltage state.
Since the input capacitance associated with the small
geometry input device is substantially lower (0.8 pF) than
that of a typical JFET (3.0 pF), the frequency response for
a given input source resistance is greatly enhanced. This
becomes evident in D−to−A current to voltage conversion
applications where the feedback resistance can form a pole
with the input capacitance of the op amp. This input pole
creates a 2nd Order system with the single pole op amp and
is therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 10 kW of feedback
resistance, the MC33171/72/74 family can typically settle to
within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12
bits in 4.8 ms for a 10 V step. In a standard inverting unity
gain fast settling configuration, the symmetrical slew rate is
typically ± 2.1 V/ms. In the classic noninverting unity gain
configuration the typical output positive slew rate is also
2.1 V/ms, and the corresponding negative slew rate will
usually exceed the positive slew rate as a function of the fall
time of the input waveform.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kW load resistance can typically swing within
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6
MC33171, 2, 4, NCV33172, 4
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for ±15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
If power to this integrated circuit is applied in reverse
polarity, or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
As usual with most high frequency amplifiers, proper lead
dress, component placement and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input/output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
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7
MC33171, 2, 4, NCV33172, 4
2.2 k
VCC
510 k
VCC
3.8 Vpp
VO 0
CO
+
100 k
VO
RL
CO
+
10 k
100 k
Vin
100 k
3.6 Vpp
VO 0
100 k
Cin
VO
-
100 k
10 k
Cin
RL
1.0 k
100 k
Vin
AV = 101
BW ( -3.0 dB) = 20 kHz
AV = 10
BW ( -3.0 dB) = 200 kHz
Figure 10. AC Coupled Noninverting Amplifier
with Single +5.0 V Supply
VCC
100 k
4.7 k
Figure 11. AC Coupled Inverting Amplifier
with Single +5.0 V Supply
VCC
50 k
RL
+
3
2
VO
-
7
+
6
5
-
1
4
10 k
1.0 M
100 k
VEE
4.2 Vpp
V 2.5 V
Vin O
Offset Nulling range is approximately ±80 mV with
a 10 k potentiometer, MC33171 only.
AV = 10
BW ( -3.0 dB) = 200 kHz
Figure 12. DC Coupled Inverting Amplifier
Maximum Output Swing with Single
+5.0 V Supply
Figure 13. Offset Nulling Circuit
VCC
fo = 30 kHz
Q = 10
HO = 1.0
Vin ≥ 0.2 Vdc
16 k
Vin
R
0.01
16 k
+
C
0.047
R1
1.1 k
VO
R
-
Vin
C
R2
5.6 k
2C
0.02
2R
32 k
2C
0.02
R3
2.2 k
fo = 1.0 kHz
C
0.047
0.4
VCC
1
fo =
4 p RC
VO
+
Then: R1 =
R3
2 HO
R2 =
R1 R3
4Q2R1 -R3
Qo fo
Q
Given fo = center frequency
R3 =
< 0.1
Ao = Gain at center frequency
GBW
p foC
Choose Value fo, Q, Ao, C
For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.
Figure 14. Active High−Q Notch Filter
Figure 15. Active Bandpass Filter
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8
MC33171, 2, 4, NCV33172, 4
ORDERING INFORMATION
Op Amp
Function
Operating
Package
Shipping†
SO−8
(Pb−Free)
98 Units/Rail
SO−8
(Pb−Free)
2500 / Tape & Reel
MC33171PG
PDIP
(Pb−Free)
50 Units/Rail
MC33172DG
SO−8
(Pb−Free)
98 Units/Rail
SO−8
(Pb−Free)
2500 / Tape & Reel
MC33172PG
PDIP
(Pb−Free)
50 Units/Rail
MC33172VDG
SO−8
(Pb−Free)
98 Units/Rail
SO−8
(Pb−Free)
2500 / Tape & Reel
SO−8
(Pb−Free)
2500 / Tape & Reel
MC33174DG
SO−14
(Pb−Free)
55 Units/Rail
MC33174DR2G
SO−14
(Pb−Free)
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
96 Units/Rail
MC33174DTBR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
MC33174PG
PDIP
(Pb−Free)
25 Units/Rail
MC33174VDG
SO−14
(Pb−Free)
55 Units/Rail
MC33174VDR2G
SO−14
(Pb−Free)
2500 / Tape & Reel
PDIP
(Pb−Free)
25 Units/Rail
Device
Temperature Range
MC33171DG
Single
MC33171DR2G
MC33172DR2G
Dual
MC33172VDR2G
TA = −40° to +85°C
TA = −40° to +85°C
TA = −40° to +125°C
NCV33172DR2G*
MC33174DTBG
Quad
MC33174VPG
TA = −40° to +85°C
TA = −40° to +125°C
NCV33174DTBR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring site and change controls.
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9
MC33171, 2, 4, NCV33172, 4
MARKING DIAGRAMS
PDIP−8
P SUFFIX
CASE 626
8
8
MC3317xP
AWL
YYWWG
3172V
ALYW
1
PDIP−14
P SUFFIX
CASE 646
1
PDIP−14
VP SUFFIX
CASE 646
SO−14
D SUFFIX
CASE 751A
14
MC33174P
AWLYYWWG
1
8
3317x
ALYW
1
14
SO−8
MC33172VD
NCV33172D
CASE 751
SO−8
D SUFFIX
CASE 751
14
14
MC33174DG
AWLYWW
MC33174VP
AWLYYWWG
1
1
TSSOP−14
NCV33174
CASE 948G
14
14
NCV3
3174
ALYW
MC33
174
ALYW
1
1
= 1 or 2
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
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10
MC33174VDG
AWLYWW
1
TSSOP−14
MC33174
CASE 948G
x
A
WL, L
YY, Y
WW, W
G or
SO−14
VD SUFFIX
CASE 751A
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
1
SCALE 1:1
D
A
14
8
E
H
E1
1
NOTE 8
7
b2
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
NOTE 3
L
SEATING
PLANE
A1
C
D1
e
M
eB
END VIEW
14X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO
CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO
CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. DRAIN
2. SOURCE
3. GATE
4. NO
CONNECTION
5. GATE
6. SOURCE
7. DRAIN
8. DRAIN
9. SOURCE
10. GATE
11. NO
CONNECTION
12. GATE
13. SOURCE
14. DRAIN
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. NO CONNECTION
5. SOURCE
6. DRAIN
7. GATE
8. GATE
9. DRAIN
10. SOURCE
11. NO CONNECTION
12. SOURCE
13. DRAIN
14. GATE
STYLE 6:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 7:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON
CATHODE
STYLE 8:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 9:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 10:
PIN 1. COMMON
CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON
CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 12:
PIN 1. COMMON CATHODE
2. COMMON ANODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. COMMON ANODE
7. COMMON CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. ANODE/CATHODE
14. ANODE/CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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