MC33178, MC33179
Low Power, Low Noise
Operational Amplifiers
The MC33178/9 series is a family of high quality monolithic
amplifiers employing Bipolar technology with innovative high
performance concepts for quality audio and data signal processing
applications. This device family incorporates the use of high
frequency PNP input transistors to produce amplifiers exhibiting low
input offset voltage, noise and distortion. In addition, the amplifier
provides high output current drive capability while consuming only
420 mA of drain current per amplifier. The NPN output stage used,
exhibits no deadband crossover distortion, large output voltage swing,
excellent phase and gain margins, low open−loop high frequency
output impedance, symmetrical source and sink AC frequency
performance.
The MC33178/9 family offers both dual and quad amplifier
versions in several package options.
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DUAL
PDIP−8
P SUFFIX
CASE 626
8
1
1
Features
•
•
•
•
•
•
•
•
•
•
SOIC−8
D SUFFIX
CASE 751
8
600 W Output Drive Capability
Large Output Voltage Swing
Low Offset Voltage: 0.15 mV (Mean)
Low T.C. of Input Offset Voltage: 2.0 mV/°C
Low Total Harmonic Distortion: 0.0024%
(@ 1.0 kHz w/600 W Load)
High Gain Bandwidth: 5.0 MHz
High Slew Rate: 2.0 V/ms
Dual Supply Operation: ±2.0 V to ±18 V
ESD Clamps on the Inputs Increase Ruggedness without Affecting
Device Performance
Pb−Free Packages are Available
8
1
QUAD
PDIP−14
P SUFFIX
CASE 646
14
1
14
1
VCC
14
Iref
1
Iref
Vin +
Vin −
Micro8
DM SUFFIX
CASE 846A
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DTB SUFFIX
CASE 948G
CC
ORDERING INFORMATION
VO
CM
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 4 of this data sheet.
VEE
Figure 1. Representative Schematic Diagram
(Each Amplifier)
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1
Publication Order Number:
MC33178/D
MC33178, MC33179
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+36
V
Input Differential Voltage Range
VIDR
Note 1
V
Input Voltage Range
VIR
Note 1
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature Range
Tstg
−60 to +150
°C
Maximum Power Dissipation
PD
Note 2
mW
Operating Temperature Range
TA
−40 to +85
°C
Supply Voltage (VCC to VEE)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation performance
characteristic, Figure 2.)
ORDERING INFORMATION
Device
Package
MC33178D
Shipping †
SOIC−8
MC33178DG
SOIC−8
(Pb−Free)
MC33178DR2
SOIC−8
MC33178DR2G
SOIC−8
(Pb−Free)
MC33178P
98 Units / Rail
2500 / Tape & Reel
PDIP−8
MC33178PG
PDIP−8
(Pb−Free)
MC33178DMR2
50 Units / Rail
Micro8
MC33178DMR2G
Micro8
(Pb−Free)
MC33179D
SOIC−14
MC33179DG
SOIC−14
(Pb−Free)
MC33179DR2
SOIC−14
MC33179DR2G
SOIC−14
(Pb−Free)
MC33179P
PDIP−14
MC33179PG
PDIP−14
(Pb−Free)
MC33179DTBR2G
TSSOP−14
(Pb−Free)
4000 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
25 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC33178, MC33179
MARKING DIAGRAMS
DUAL
QUAD
PDIP−8
CASE 626
PDIP−14
CASE 646
SOIC−8
CASE 751
8
14
8
MC33178P
AWL
YYWWG
1
1
SOIC−14
CASE 751A
33178
ALYW
G
14
MC33179DG
AWLYWW
MC33179P
AWLYYWWG
1
1
Micro8
CASE 846A
TSSOP−14
CASE 948G
8
14
MC33
179
ALYWG
G
3178
AYWG
G
1
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
DUAL
CASE 626/751/846A
Output 1
Inputs 1
VEE
1
8
2
7
3
4
−
+
6
−
+ 5
QUAD
CASE 646/751A/948G
VCC
Output 2
Output 1
Inputs 1
Inputs 2
VCC
(Top View)
Inputs 2
Output 2
1
14
2
13
3
−
+
1
4
3
+
12
4
11
5
10
6
+
−
2
7
3
+
−
9
8
(Top View)
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−
Output 4
Inputs 4
VEE
Inputs 3
Output 3
MC33178, MC33179
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V)
(VCC = +2.5 V, VEE = −2.5 V to VCC = +15 V, VEE = −15 V)
TA = +25°C
TA = −40° to +85°C
3
|VIO|
Average Temperature Coefficient of Input Offset Voltage
(RS = 50 W, VCM = 0 V, VO = 0 V)
TA = −40° to +85°C
3
Min
4, 5
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
Large Signal Voltage Gain (VO = −10 V to +10 V, RL = 600 W)
TA = +25°C
TA = −40° to +85°C
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = −15 V)
RL = 300 W
RL = 300 W
RL = 600 W
RL = 600 W
RL = 2.0 kW
RL = 2.0 kW
(VCC = +2.5 V, VEE = −2.5 V)
RL = 600 W
RL = 600 W
0.15
−
IIB
6
VICR
7, 8
AVOL
mV/°C
−
2.0
−
−
−
100
−
500
600
−
−
5.0
−
50
60
−13
−
−14
+14
−
+13
50
25
200
−
−
−
nA
nA
V
VO+
VO−
VO+
VO−
VO+
VO−
−
−
+12
−
+13
−
+12
−12
+13.6
−13
+14
−13.8
−
−
−
−12
−
−13
VO+
VO−
1.1
−
1.6
−1.6
−
−1.1
80
110
−
80
110
−
+50
−50
+80
−100
−
−
Common Mode Rejection (Vin = ±13 V)
12
CMR
Power Supply Rejection
VCC/VEE = +15 V/ −15 V, +5.0 V/ −15 V, +15 V/ −5.0 V
13
PSR
14, 15
Power Supply Current (VO = 0 V)
(VCC = 2.5 V, VEE = −2.5 V to VCC = +15 V, VEE = −15 V)
MC33178 (Dual)
TA = +25°C
TA = −40° to +85°C
MC33179 (Quad)
TA = +25°C
TA = −40° to +85°C
16
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4
V
kV/V
9, 10, 11
Output Short Circuit Current (VID = ±1.0 V, Output to Ground)
Source (VCC = 2.5 V to 15 V)
Sink (VEE = −2.5 V to −15 V)
Unit
3.0
4.0
DVIO/DT
|IIO|
Common Mode Input Voltage Range
(DVIO = 5.0 mV, VO = 0 V)
Max
mV
−
−
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
Typ
ISC
dB
dB
mA
ID
mA
−
−
−
−
1.4
1.6
−
−
1.7
−
2.4
2.6
MC33178, MC33179
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Slew Rate
(Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V)
Gain Bandwidth Product (f = 100 kHz)
AC Voltage Gain (RL = 600 W, VO = 0 V, f = 20 kHz)
Figure
Symbol
17, 32
SR
Min
Typ
Max
Unit
V/ms
1.2
2.0
−
18
GBW
2.5
5.0
−
MHz
19, 20
AVO
−
50
−
dB
BW
−
3.0
−
MHz
Gain Margin (RL = 600 W, CL = 0 pF)
21, 23, 24
Am
−
15
−
dB
Phase Margin (RL = 600 W, CL = 0 pF)
22, 23, 24
fm
−
60
−
Deg
25
CS
−
−120
−
dB
BWp
−
32
−
kHz
−
−
−
0.0024
0.014
0.024
−
−
−
−
150
−
Unity Gain Bandwidth (Open−Loop) (RL = 600 W, CL = 0 pF)
Channel Separation (f = 100 Hz to 20 kHz)
Power Bandwidth (VO = 20 Vpp, RL = 600 W, THD ≤ 1.0%)
Total Harmonic Distortion (RL = 600 W,, VO = 2.0 Vpp, AV = +1.0 V)
(f = 1.0 kHz)
(f = 10 kHz)
(f = 20 kHz)
26
Open Loop Output Impedance
(VO = 0 V, f = 3.0 MHz, AV = 10 V)
27
THD
%
|ZO|
W
Differential Input Resistance (VCM = 0 V)
Rin
−
200
−
kW
Differential Input Capacitance (VCM = 0 V)
Cin
−
10
−
pF
−
−
8.0
7.5
−
−
−
−
0.33
0.15
−
−
28
Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
29
2400
2000
MC33178P/9P
1600
MC33179D
1200
800
en
in
nV/ √ Hz
pA/ √ Hz
4.0
V,
IO INPUT OFFSET VOLTAGE (mV)
P(MAX),
MAXIMUM POWER DISSIPATION (mW)
D
Equivalent Input Noise Voltage (RS = 100 W,)
f = 10 Hz
f = 1.0 kHz
MC33178D
400
0
−60 −40 −20
0
20
40
60
2.0
Unit 1
1.0
Unit 2
0
Unit 3
−1.0
−2.0
−3.0
−4.0
−55
80 100 120 140 160 180
VCC = +15 V
VEE = −15 V
RS = 10 W
VCM = 0 V
3.0
−25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Offset Voltage versus
Temperature for 3 Typical Units
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5
125
MC33178, MC33179
120
140
I,
IB INPUT BIAS CURRENT (nA)
I,
IB INPUT BIAS CURRENT (nA)
160
120
100
80
60
40
VCC = +15 V
VEE = −15 V
TA = 25°C
20
0
−15
−10
−5.0
0
5.0
VCM, COMMON MODE VOLTAGE (V)
10
VCC = +15 V
VEE = −15 V
VCM = 0 V
110
100
90
80
70
60
−55
15
−25
AVOL, OPEN LOOP VOLTAGE GAIN (kV/V)
VCC
VCC −0.5 V
VCC = +5.0 V to +18 V
VEE = −5.0 V to −18 V
DVIO = 5.0 mV
VCC −1.0 V
VCC −1.5 V
VCC −2.0 V
VEE +1.0 V
VEE +0.5 V
VEE
−55
−25
0
25
50
75
100
150
VCC = +15 V
VEE = −15 V
f = 10 Hz
DVO = 10 V to +10 V
RL = 600 W
100
50
0
−55
−25
0
25
50
75
Figure 7. Open Loop Voltage Gain
versus Temperature
40
80
100
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
120
140
160
0
180
−20
125
200
Figure 6. Input Common Mode Voltage
Range versus Temperature
10
−10
100
250
TA, AMBIENT TEMPERATURE (°C)
1A
200
1B
1A) Phase (RL = 600 W)
2B
−30 2A) Phase (RL = 600 W, CL = 300 pF)
2A
−40 1B) Gain (RL = 600 W)
2B) Gain (RL = 600 W, CL = 300 pF)
−50
2
3 4
5
6 7 8 9 10
f, FREQUENCY (Hz)
220
240
260
20
35
VO , OUTPUT VOLTAGE (Vpp )
20
125
, EXCESS PHASE (DEGREES)
30
125
TA, AMBIENT TEMPERATURE (°C)
50
40
100
Figure 5. Input Bias Current
versus Temperature
φ
A
VOL, OPEN LOOP VOLTAGE GAIN (dB)
V ICR, INPUT COMMON MODE VOLTAGE RANGE (V)
Figure 4. Input Bias Current
versus Common Mode Voltage
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
RL = 10 kW
25
RL = 600 W
20
15
10
5.0
0
280
TA = 25°C
30
0
Figure 8. Voltage Gain and Phase
versus Frequency
5.0
10
15
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 9. Output Voltage Swing
versus Supply Voltage
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6
20
VCC
VO , OUTPUT VOLTAGE (Vpp )
VCC −1.0 V
28
Source
TA = +125°C
TA = −55°C
VCC −2.0 V
VEE +2.0 V
Sink
TA = −55°C
VEE +1.0 V
VCC = +5.0 V to +18 V
VEE = −5.0 V to −18 V
TA = +125°C
VEE
0
5.0
10
15
16
VCC = +15 V
VEE = −15 V
RL = 600 W
AV = +1.0 V
THD = ≤1.0%
TA = 25°C
12
8.0
4.0
1.0 M
Figure 11. Output Voltage
versus Frequency
VCC = +15 V
VEE = −15 V
VCM = 0 V
DVCM = ±1.5 V
TA = −55° to +125°C
60
−
ADM
+
DVCM
20
CMR = 20 Log
100
DVO
DVCM
DVO
x ADM
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
120
80
−PSR
−
ADM
+
60
40
I,
SC OUTPUT SHORT CIRCUIT CURRENT (mA)
Source
80
Sink
60
VCC = +15 V
VEE = −15 V
VID = ±1.0 V
20
−9.0
−3.0
0
3.0
VO, OUTPUT VOLTAGE (V)
DVO
20
PSR = 20 Log
DVO/ADM
DVCC
100
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
1.0 M
Figure 13. Power Supply Rejection
versus Frequency Over Temperature
100
40
VCC
VEE
0
10
1.0 M
TA = −55° to +125°C
VCC = +15 V
VEE = −15 V
DVCC = ±1.5 V
+PSR
100
Figure 12. Common Mode Rejection
versus Frequency Over Temperature
I,
SC OUTPUT SHORT CIRCUIT CURRENT (mA)
100 k
Figure 10. Output Saturation Voltage
versus Load Current
80
0
−15
10 k
f, FREQUENCY (Hz)
100
0
10
20
IL, LOAD CURRENT (±mA)
120
40
24
0
1.0 k
20
PSR, POWER SUPPLY REJECTION (dB)
CMR, COMMON MODE REJECTION (dB)
V sat , OUTPUT SATURATION VOLTAGE (V)
MC33178, MC33179
9.0
15
100
90
VCC = +15 V
VEE = −15 V
VID = ±1.0 V
RL < 10 W
Sink
80
Source
70
60
50
−55
−25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
Figure 14. Output Short Circuit Current
versus Output Voltage
Figure 15. Output Short Circuit Current
versus Temperature
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7
125
1.15
625
SR, SLEW RATE (NORMALIZED)
TA = +125°C
500
375
TA = +25°C
250
TA = −55°C
125
0
0
2.0
4.0
6.0
8.0
10
12
14
VCC, |VEE| , SUPPLY VOLTAGE (V)
16
1.10
1.05
1.00
0.95
0.90
−
DVin
0.75
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
8.0
6.0
0
−55
VCC = +15 V
VEE = −15 V
f = 100 kHz
RL = 600 W
CL = 0 pF
−25
100
30
140
10
180
0
VCC = +15 V
VEE = −15 V
RL = 600 W
TA = 25°C
CL = 0 pF
−20
−30
30
20
0
−10
1A
1B
2A
−20 1A) Phase V =18 V, V = −18 V
CC
EE
−30 2A) Phase VCC 1.5 V, VEE = −1.5 V
1B) Gain V = 18 V, V = −18 V
−40 2B) Gain VCC = 1.5 V, VEE = −1.5 V
CC
EE
−50
100 k
1.0 M
100
120
140
160
180
2B
200
220
240
260
10 M
220
240
260
280
100 M
1.0 M
10 M
f, FREQUENCY (Hz)
15
Am, OPEN LOOP GAIN MARGIN (dB)
40
200
Figure 19. Voltage Gain and Phase
versus Frequency
φ , PHASE (DEGREES)
TA = 25°C
RL = ∞
CL = 0 pF
160
Gain
−10
80
50
120
20
−50
100 k
125
100
Phase
−40
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
125
80
Figure 18. Gain Bandwidth Product
versus Temperature
10
100
50
40
2.0
600 W
100 pF
Figure 17. Normalized Slew Rate
versus Temperature
10
4.0
+
0.80
18
AV , VOLTAGE GAIN (dB)
GBW, GAIN BANDWIDTH PRODUCT (MHz)
VO
0.85
Figure 16. Supply Current versus Supply
Voltage with No Load
A,
V VOLTAGE GAIN (dB)
VCC = +15 V
VEE = −15 V
DVin = 20 Vpp
φ , EXCESS PHASE (DEGREES)
μ A)
I
CC , SUPPLY CURRENT/AMPLIFIER (
MC33178, MC33179
280
100 M
CL = 10 pF
12
CL = 100 pF
9.0
CL = 300 pF
6.0
3.0
0
−55
VCC = +15 V
VEE = −15 V
RL = 600 W
−25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
f, FREQUENCY (Hz)
Figure 20. Voltage Gain and Phase
versus Frequency
Figure 21. Open Loop Gain Margin
versus Temperature
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8
125
MC33178, MC33179
12
10
CL = 100 pF
40
30
CL = 300 pF
20
VCC = +15 V
VEE = −15 V
RL = 600 W
10
0
−55
−25
60
50
VCC = +15 V
VEE = −15 V
RT = R1+R2
VO = 0 V
TA = 25°C
8.0
6.0
4.0
25
50
75
100
1.0 k
30
9.0
−
20
VO
+
600 W
CL
10
0
1.0 k
0
100
Drive Channel
VCC = +15 V
CEE = −15 V
RL = 600 W
TA = 25°C
140
130
120
110
100
100
1.0 k
10 k
100 k
CL, OUTPUT LOAD CAPACITANCE (pF)
f, FREQUENCY (Hz)
Figure 24. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance
Figure 25. Channel Separation
versus Frequency
10
AV = 1000
1.0
AV = 100
0.1
0.01
10
1.0 M
500
VCC = +15 V VO = 2.0 Vpp
VEE = −15 V TA = 25°C
RL = 600 W
|Z|,
Ω
O OUTPUT IMPEDANCE ()
THD, TOTAL HARMONIC DISTORTION (%)
10
CS, CHANNEL SEPARATION (dB)
40
Gain Margin
m, PHASE MARGIN (DEGREES)
50
φ
A,
m OPEN LOOP GAIN MARGIN (dB)
VCC = +15 V
VEE = −15 V
VO = 0 V
12
3.0
0
100 k
10 k
150
60
Vin
10
Figure 23. Phase Margin and Gain Margin
versus Differential Source Resistance
18
6.0
VO
+
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 22. Phase Margin
versus Temperature
15
Phase Margin
−
R2
TA, AMBIENT TEMPERATURE (°C)
Phase Margin
30
Vin
0
100
125
40
20
R1
2.0
0
Gain Margin
φ m, PHASE MARGIN (DEGREES)
CL = 10 pF
50
A,
m GAIN MARGIN (dB)
φ m , PHASE MARGIN (DEGREES)
60
AV = 10
AV = 1.0
400
300
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
1. AV = 1.0
2. AV = 10
3. AV = 100
4. AV = 1000
200
100
3
2
1
4
100
1.0 k
10 k
0
1.0 k
100 k
f, FREQUENCY (Hz)
Figure 26. Total Harmonic Distortion
versus Frequency
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
Figure 27. Output Impedance
versus Frequency
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9
10 M
20
√ Hz
i,
()
n INPUT REFERRED NOISE CURRENT pA/
e,
nV/ √ Hz
n INPUT REFERRED NOISE VOLTAGE ()
MC33178, MC33179
Input Noise Voltage Test
Circuit
+
VO
−
18
16
14
12
10
8.0
6.0
4.0
2.0
0
10
VCC = +15 V
VEE = −15 V
TA = 25°C
100
1.0 k
f, FREQUENCY (Hz)
10 k
10 k
0.5
Input Noise Current Test Circuit
0.4
+
RS
−
VO
0.3
(RS = 10 kW)
0.2
0.1
0
10
Figure 28. Input Referred Noise Voltage
versus Frequency
VCC = +15 V
VEE = −15 V
TA = 25°C
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
Figure 29. Input Referred Noise Current
versus Frequency
100
70
V O, OUTPUT VOLTAGE (5.0 V/DIV)
80
VCC = +15 V
VEE = −15 V
TA = 25°C
60
50
RL = 600 W
RL = 2.0 kW
40
30
20
10
0
10
100
1.0 k
CL, LOAD CAPACITANCE (pF)
10 k
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 600 W
CL = 100 pF
TA = 25°C
t, TIME (2.0 ms/DIV)
Figure 30. Percent Overshoot versus
Load Capacitance
Figure 31. Non−inverting Amplifier Slew Rate
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 600 W
CL = 100 pF
TA = 25°C
V O, OUTPUT VOLTAGE (5.0 V/DIV)
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 600 W
CL = 100 pF
TA = 25°C
V O, OUTPUT VOLTAGE (50 mV/DIV)
PERCENT OVERSHOOT (%)
90
t, TIME (5.0 ms/DIV)
t, TIME (2.0 ns/DIV)
Figure 32. Small Signal Transient Response
Figure 33. Large Signal Transient Response
http://onsemi.com
10
MC33178, MC33179
10 k
A1
To
Receiver
−
10 k
+
10 k
1.0 mF
200 k
120 k
From
Microphone
2.0 k
−
+
0.05 mF
300
A2
820
Tip
VR
1N4678
Phone Line
10 k
Ring
10 k
−
+
A3
VR
Figure 34. Telephone Line Interface Circuit
APPLICATION INFORMATION
MC33179 (quad op amp). Shorting more than one amplifier
could easily exceed the junction temperature to the extent of
causing permanent damage.
This unique device uses a boosted output stage to combine
a high output current with a drain current lower than similar
bipolar input op amps. Its 60° phase margin and 15 dB gain
margin ensure stability with up to 1000 pF of load
capacitance (see Figure 24). The ability to drive a minimum
600 W load makes it particularly suitable for telecom
applications. Note that in the sample circuit in Figure 34
both A2 and A3 are driving equivalent loads of
approximately 600 W .
The low input offset voltage and moderately high slew
rate and gain bandwidth product make it attractive for a
variety of other applications. For example, although it is not
single supply (the common mode input range does not
include ground), it is specified at +5.0 V with a typical
common mode rejection of 110 dB. This makes it an
excellent choice for use with digital circuits. The high
common mode rejection, which is stable over temperature,
coupled with a low noise figure and low distortion, is an
ideal op amp for audio circuits.
The output stage of the op amp is current limited and
therefore has a certain amount of protection in the event of
a short circuit. However, because of its high current output,
it is especially important not to allow the device to exceed
the maximum junction temperature, particularly with the
Stability
As usual with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input/output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole frequency for optimum frequency response, but also
minimizes extraneous “pick up” at this node. Supplying
decoupling with adequate capacitance immediately adjacent
to the supply pin is also important, particularly over
temperature, since many types of decoupling capacitors
exhibit great impedance changes over temperature.
Additional stability problems can be caused by high load
capacitances and/or a high source resistance. Simple
compensation schemes can be used to alleviate these
effects.
http://onsemi.com
11
MC33178, MC33179
For moderately high capacitive loads (500 pF < CL
< 1500 pF) the addition of a compensation resistor on the
order of 20 W between the output and the feedback loop will
help to decrease miller loop oscillation (see Figure 36). For
high capacitive loads (CL > 1500 pF), a combined
compensation scheme should be used (see Figure 37). Both
the compensation resistor and the compensation capacitor
affect the transient response and can be calculated for
optimum performance. The value of CC can be calculated
using Equation 1. The Equation to calculate RC is as follows:
If a high source of resistance is used (R1 > 1.0 kW), a
compensation capacitor equal to or greater than the input
capacitance of the op amp (10 pF) placed across the
feedback resistor (see Figure 35) can be used to neutralize
that pole and prevent outer loop oscillation. Since the closed
loop transient response will be a function of that
capacitance, it is important to choose the optimum value for
that capacitor. This can be determined by the following
Equation:
CC + (1 ) [R1ńR2])2
CL (ZOńR2)
(1)
RC + ZO
where: ZO is the output impedance of the op amp.
(2)
R1ńR2
R2
R2
CC
−
−
+
R1
+
R1
ZL
CL
Figure 35. Compensation for
High Source Impedance
Figure 36. Compensation Circuit for
Moderate Capacitive Loads
R2
CC
−
R1
RC
RC
+
CL
Figure 37. Compensation Circuit for
High Capacitive Loads
http://onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
1
SCALE 1:1
D
A
14
8
E
H
E1
1
NOTE 8
7
b2
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
NOTE 3
L
SEATING
PLANE
A1
C
D1
e
M
eB
END VIEW
14X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO
CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO
CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. DRAIN
2. SOURCE
3. GATE
4. NO
CONNECTION
5. GATE
6. SOURCE
7. DRAIN
8. DRAIN
9. SOURCE
10. GATE
11. NO
CONNECTION
12. GATE
13. SOURCE
14. DRAIN
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. NO CONNECTION
5. SOURCE
6. DRAIN
7. GATE
8. GATE
9. DRAIN
10. SOURCE
11. NO CONNECTION
12. SOURCE
13. DRAIN
14. GATE
STYLE 6:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 7:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON
CATHODE
STYLE 8:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 9:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 10:
PIN 1. COMMON
CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON
CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 12:
PIN 1. COMMON CATHODE
2. COMMON ANODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. COMMON ANODE
7. COMMON CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. ANODE/CATHODE
14. ANODE/CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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