DATA SHEET
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Voltage Regulator - Low
Dropout
LOW DROPOUT
MICROPOWER VOLTAGE
REGULATOR
300 mA
MARKING DIAGRAMS
MC33275, NCV33275
The MC33275 series are micropower low dropout voltage
regulators available in a wide variety of output voltages as well as
packages, SOT−223, SOP−8, DPAK, and DFN 4x4 surface mount
packages. These devices feature a very low quiescent current and are
capable of supplying output currents up to 300 mA. Internal current
and thermal limiting protection are provided by the presence of a short
circuit at the output and an internal thermal shutdown circuit.
Due to the low input−to−output voltage differential and bias current
specifications, these devices are ideally suited for battery powered
computer, consumer, and industrial equipment where an extension of
useful battery life is desirable.
4
1
3
1
8
1
4
• Low Input−to−Output Voltage Differential of 25 mV at IO = 10 mA,
•
•
•
•
•
Applications
• Battery Powered Consumer Products
• Hand−Held Instruments
• Camcorders and Cameras
Vin
Vout
SOIC−8
D SUFFIX
CASE 751
8
Features
and 260 mV at IO = 300 mA
Extremely Tight Line and Load Regulation
Stable with Output Capacitance of only 0.33 F for 2.5 V Output
Voltage
Internal Current and Thermal Limiting
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
AYW
275xxG
G
SOT−223
ST SUFFIX
CASE 318E
1 2
3
1
275xx
ALYWG G
1
275xxG
ALYWW
DPAK
DT SUFFIX
CASE 369C
DFN−8, 4x4
MN SUFFIX
CASE 488AF
1
275xx
ALYWG
G
xx
= Voltage Version
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W, WW = Work Week
G or G = Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 10
of this data sheet.
Thermal &
Anti−sat
Protection
Rint
1.23 V
V. Ref.
54 K
GND
This device contains 41 active transistors
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2015
January, 2022 − Rev. 21
1
Publication Order Number:
MC33275/D
MC33275, NCV33275
PIN CONNECTIONS
GND
GND
4
4
Input
GND
1
2
3
Vin GND Vout
MC33275ST
GND
1
2
3
VinGND Vout
MC33275DT
N/C
1
ÇÇ
ÇÇ
ÇÇ
8
Output
7
GND
6
GND
5
N/C
2
3
4
Input
Input
Input
N/C
Pins 4 and 5 Not Connected
MC33275D
1
2
3
4
Ç
Ç
Ç
8
7
6
5
Output
N/C
GND
N/C
MC33275MN
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
13
Vdc
PD
Internally Limited
W
RJA
RJC
160
25
°C/W
°C/W
RJA
RJC
245
15
°C/W
°C/W
RJA
RJC
92
6.0
°C/W
°C/W
RJA
RJA
psi−JC*
183
93
9.0
°C/W
°C/W
°C/W
Output Current
IO
300
mA
Maximum Junction Temperature
TJ
150
°C
Operating Ambient Temperature Range
TA
− 40 to +125
°C
Storage Temperature Range
Tstg
− 65 to +150
°C
Electrostatic Discharge Sensitivity (ESD)
Human Body Model (HBM)
Machine Model (MM)
ESD
Input Voltage
Power Dissipation and Thermal Characteristics
TA = 25°C
Maximum Power Dissipation
Case 751 (SOIC−8) D Suffix
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Case 318E (SOT−223) ST Suffix
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
Case 369A (DPAK−3) DT Suffix
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
Case 488AF (DFN−8, 4x4) MN Suffix
Thermal Resistance, Junction−to−Air (with 1.0 oz PCB cu area)
Thermal Resistance, Junction−to−Air (with 1.8 oz PCB cu area)
Thermal Resistance, Junction−to−Case
4000
400
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*“C’’ (“case’’) is defined as the solder−attach interface between the center of the exposed pad on the bottom of the package, and the board to
which it is attached.
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2
MC33275, NCV33275
ELECTRICAL CHARACTERISTICS (CL = 1.0F, TA = 25°C, for min/max values TJ = −40°C to +125°C, Note 1)
Symbol
Characteristic
Output Voltage
2.5 V Suffix
3.0 V Suffix
3.3 V Suffix
5.0 V Suffix
IO = 0 mA to 250 mA
TA = 25°C, Vin = [VO + 1] V
VO
Min
Typ
Max
2.475
2.970
3.267
4.950
2.50
3.00
3.30
5.00
2.525
3.030
3.333
5.05
2.450
2.940
3.234
4.900
−
−
−
−
2.550
3.060
3.366
5.100
Unit
Vdc
2.5 V Suffix
3.0 V Suffix
3.3 V Suffix
5.0 V Suffix
Vin = [VO + 1] V, 0 < IO < 100 mA
2% Tolerance from TJ = −40 to +125°C
Line Regulation
Vin = [VO + 1] V to 12 V, IO = 250 mA,
All Suffixes TA = 25°C
Regline
−
2.0
10
mV
Load Regulation
Vin = [VO + 1] V, IO = 0 mA to 250 mA,
All Suffixes TA = 25°C
Regload
−
5.0
25
mV
−
−
−
−
25
115
220
260
100
200
400
500
65
75
−
−
−
160
46
−
−
−
125
200
−
−
−
1500
1500
1500
2000
2000
2000
Dropout Voltage
IO = 10 mA
IO = 100 mA
IO = 250 mA
IO = 300 mA
Vin − VO
TJ = −40°C to +125°C
Ripple Rejection (120 Hz)
Vin(peak−peak) = [VO + 1.5] V to [VO + 5.5] V
Output Noise Voltage
CL = 1.0 F
IO = 50 mA (10 Hz to 100 kHz)
CL = 200 F
−
Vn
mV
dB
Vrms
CURRENT PARAMETERS
Quiescent Current ON Mode
Vin = [VO + 1] V, IO = 0 mA
IQOn
Quiescent Current ON Mode SAT
3.0 V Suffix
3.3 V Suffix
5.0 V Suffix
Vin = [VO − 0.5] V, IO = 0 mA (Notes 2, 3)
IQSAT
Current Limit
Vin = [VO + 1] V, VO Shorted
ILIMIT
−
450
−
mA
−
−
150
−
°C
A
A
THERMAL SHUTDOWN
Thermal Shutdown
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
2. Quiescent Current is measured where the PNP pass transistor is in saturation. Vin = [VO − 0.5] V guarantees this condition.
3. For 2.5 V version, IQSAT is constrained by the minimum input voltage of 2.5 V.
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3
MC33275, NCV33275
DEFINITIONS
Load Regulation − The change in output voltage for a
change in load current at constant chip temperature.
Dropout Voltage − The input/output differential at which
the regulator output no longer maintains regulation against
further reductions in input voltage. Measured when the
output drops 100 mV below its nominal value (which is
measured at 1.0 V differential), dropout voltage is affected
by junction temperature, load current and minimum input
supply requirements.
Output Noise Voltage − The RMS AC voltage at the
output with a constant load and no input ripple, measured
over a specified frequency range.
Maximum Power Dissipation − The maximum total
dissipation for which the regulator will operate within
specifications.
Quiescent Current − Current which is used to operate the
regulator chip and is not delivered to the load.
Line Regulation − The change in output voltage for a
change in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Maximum Package Power Dissipation − The maximum
package power dissipation is the power dissipation level at
which the junction temperature reaches its maximum value
i.e. 150°C. The junction temperature is rising while the
difference between the input power (VCC X ICC) and the
output power (Vout X Iout) is increasing.
Depending on ambient temperature, it is possible to
calculate the maximum power dissipation and so the
maximum current as following:
T * T
A
Pd + J
R
JA
The maximum operating junction temperature TJ is
specified at 150°C, if TA = 25°C, then PD can be found. By
neglecting the quiescent current, the maximum power
dissipation can be expressed as:
I out +
P
D
V
* Vout
CC
The thermal resistance of the whole circuit can be
evaluated by deliberately activating the thermal shutdown
of the circuit (by increasing the output current or raising the
input voltage for example).
Then you can calculate the power dissipation by
subtracting the output power from the input power. All
variables are then well known: power dissipation, thermal
shutdown temperature and ambient temperature.
R
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4
JA
T * T
A
+ J
P
D
MC33275, NCV33275
7
150
TA = 25° C
6 CL = 33 F
IL = 10 mA
5 Vout = 3.3 V
100
4
50
3
0
2
Vout
-50
1
0
0
20
40
60
80
100
120
140
160
70
60
Vin
Vin , INPUT VOLTAGE (V)
Vin
200
40
4
30
3
20
10
2
0
Vout
1
0
50
100
Figure 3. Line Transient Response
1.0
300
0
-300
Vout
CHANGE
-400 CL = 1.0 F
Vout = 3.3 V
-500 TA = 25° C
-600 Vin = 4.3 V
0
50
-0.2
-0.4
-0.6
-0.8
100
150
200
300
250
350
LOAD CURRENT (mA)
LOAD CURRENT (mA)
0.2
LOAD CURRENT
150
-50
0.04
-150
-0.01
-250
-350
CL = 33.0 F
Vout = 3.3 V
TA = 25° C
Vin = 4.3 V
Vout
CHANGE
-450
-550
-0.06
-0.11
-650
-750
-1.0
400
-0.16
0
50
TIME (S)
100
150
200
250
300
TIME (S)
Figure 5. Load Transient Response
Figure 4. Load Transient Response
300
3.5
3.0
IL = 1 mA
2.5
DROPOUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
0.09
50
OUTPUT VOLTAGE CHANGE (V)
0.4
-200
0.14
250
0.6
OUTPUT VOLTAGE CHANGE (V)
LOAD
CURRENT
-100
-700
350
0.8
0
-20
200
150
TIME (S)
Figure 2. Line Transient Response
100
-10
0
-100
180 200
TIME (S)
200
50
OUTPUT VOLTAGE CHANGE (mV)
TA = 25° C
6 CL = 0.47 F
IL = 10 mA
5 Vout = 3.3 V
OUTPUT VOLTAGE CHANGE (mV)
Vin , INPUT VOLTAGE (V)
7
IL = 250 mA
2.0
1.5
1.0
250
200
150
100
50
0.5
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1
4.5 5.0
10
100
1000
INPUT VOLTAGE (V)
IO, OUTPUT CURRENT (mA)
Figure 6. Output Voltage versus Input Voltage
Figure 7. Dropout Voltage versus Output Current
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5
MC33275, NCV33275
12
250
10
IL = 300 mA
8
200
Ignd (mA)
DROPOUT VOLTAGE (mV)
300
IL = 250 mA
150
IL = 100 mA
100
50
4
0
IL = 100 mA
2
IL = 10 mA
0
-40
IL = 300 mA
6
IL = 50 mA
25
0
85
0
1
2
3
TEMPERATURE (°C)
4
5
6
7
8
Vin (VOLTS)
Figure 9. Ground Pin Current versus
Input Voltage
Figure 8. Dropout Voltage versus Temperature
2.5
8
7
IL = 250 mA
IO = 0
2.495
Vout (VOLTS)
Ignd (mA)
6
5
4
3
IL = 100 mA
2.49
IO = 250 mA
2.485
2.48
2
IL = 50 mA
1
0
-40
-20
0
20
40
60
80
100
120
2.475
2.47
-40
140
0
25
TA (°C)
TEMPERATURE (°C)
Figure 10. Ground Pin Current versus
Ambient Temperature
Figure 11. Output Voltage versus Ambient
Temperature (Vin = Vout + 1V)
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6
85
MC33275, NCV33275
2.5
IO = 0
2.495
Vout (VOLTS)
2.49
IO = 250 mA
2.485
2.48
2.475
2.47
2.465
-40
0
25
85
TEMPERATURE (°C)
Figure 12. Output Voltage versus Ambient
Temperature (Vin = 12 V)
70
60
IL = 10 mA
dB
50
IL = 1 mA
40
30
20
10
0
0.1
1
10
100
FREQUENCY (kHz)
Figure 13. Ripple Rejection
70
60
IL = 100 mA
dB
50
IL = 250 mA
40
30
20
10
0
0.1
1
10
FREQUENCY (kHz)
Figure 14. Ripple Rejection
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7
100
MC33275, NCV33275
APPLICATIONS INFORMATION
Vout
Vin
Cin
Cout
LOAD
GND
Figure 15. Typical Application Circuit
The MC33275 regulators are designed with internal
current limiting and thermal shutdown making them
user−friendly. Figure 15 is a typical application circuit. The
output capability of the regulator is in excess of 300 mA,
with a typical dropout voltage of less than 260 mV. Internal
protective features include current and thermal limiting.
ESR (ohm)
100
EXTERNAL CAPACITORS
Vout = 3.0 V
Cout = 1.0 F
Cin = 1.0 F
10
Stable Region
1.0
These regulators require only a 0.33 F (or greater)
capacitance between the output and ground for stability for
1.8 V, 2.5 V, 3.0 V, and 3.3 V output voltage options. Output
voltage options of 5.0 V require only 0.22 F for stability.
The output capacitor must be mounted as close as possible
to the MC33275. If the output capacitor must be mounted
further than two centimeters away, then a larger value of
output capacitor may be required for stability. A value of
0.68 F or larger is recommended. Most type of aluminum,
tantalum, or multilayer ceramic will perform adequately.
Solid tantalums or appropriate multilayer ceramic
capacitors are recommended for operation below 25°C. An
input bypass capacitor is recommended to improve transient
response or if the regulator is connected to the supply input
filter with long wire lengths, more than 4 inches. This will
reduce the circuit’s sensitivity to the input line impedance at
high frequencies. A 0.33 F or larger tantalum, mylar,
ceramic, or other capacitor having low internal impedance
at high frequencies should be chosen. The bypass capacitor
should be mounted with shortest possible lead or track
length directly across the regulator’s input terminals.
Figure 16 shows the ESR that allows the LDO to remain
stable for various load currents.
0.1
0
50
100
150
200
250
300
LOAD CURRENT (mA)
Figure 16. ESR for Vout = 3.0V
Applications should be tested over all operating
conditions to insure stability.
THERMAL PROTECTION
Internal thermal limiting circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated, typically at
150°C, the output is disabled. There is no hysteresis built
into the thermal protection. As a result the output will appear
to be oscillating during thermal limit. The output will turn
off until the temperature drops below the 150°C then the
output turns on again. The process will repeat if the junction
increases above the threshold. This will continue until the
existing conditions allow the junction to operate below the
temperature threshold.
Thermal limit is not a substitute for proper
heatsinking.
The internal current limit will typically limit current to
450 mA. If during current limit the junction exceeds 150°C,
the thermal protection will protect the device also. Current
limit is not a substitute for proper heatsinking.
OUTPUT NOISE
In many applications it is desirable to reduce the noise
present at the output. Reducing the regulator bandwidth by
increasing the size of the output capacitor will reduce the noise.
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8
RJA, THERMAL RESISTANCE,
JUNCTION−TO−AIR (°CW)
180
1.6
160
1.4
PD(max) for TA = 50°C
140
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0 oz. Copper
L
Minimum
Size Pad
120
L
100
80
60
RJA
0
5.0
10
15
20
25
L, LENGTH OF COPPER (mm)
1.2
1.0
0.8
0.6
0.4
30
PD, MAXIMUM POWER DISSIPATION (W)
MC33275, NCV33275
RJA, THERMAL RESISTANCE,
JUNCTION−TO−AIR (°CW)
100
1.6
PD(max) for TA = 50°C
1.4
90
2.0 oz. Copper
L
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
80
Minimum
Size Pad
70
1.0
L
60
0.8
50
0.6
RJA
40
1.2
0
5.0
10
15
20
0.4
30
25
PD, MAXIMUM POWER DISSIPATION (W)
Figure 17. SOT−223 Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
L, LENGTH OF COPPER (mm)
3.2
170
150
PD(max) for TA = 50°C
2.8
130
2.4
110
Graph Represents Symmetrical Layout 2.0
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
90
70
30
0
10
3.0
mm
L
RJA
50
1.6
2.0 oz.
Copper
L
20
30
40
1.2
0.8
0.4
50
L, LENGTH OF COPPER (mm)
Figure 19. SOP−8 Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
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9
PD, MAXIMUM POWER DISSIPATION (W)
RJA, THERMAL RESISTANCE,
JUNCTION−TO−AIR (°CW)
Figure 18. DPAK Thermal Resistance and Maximum
Power Dissipation versus P.C.B. Copper Length
MC33275, NCV33275
ORDERING INFORMATION
VO Typ (V)
Operating Temperature
Range, Tolerance
MC33275DT−2.5RKG
2.5 V
(Fixed Voltage)
1% Tolerance
at TA = 25°C
MC33275D−3.0R2G
3.0 V
(Fixed Voltage)
Device
MC33275MN−3.0R2G
MC33275D−3.3R2G
2% Tolerance at
TJ from −40°C to +125°C
3.3 V
(Fixed Voltage)
1% Tolerance
at TA = 25°C
MC33275DT−3.3RKG
MC33275ST−3.3T3G
2% Tolerance at
TJ from −40°C to +125°C
1% Tolerance
at TA = 25°C
NCV33275ST3.3T3G*
MC33275D−5.0R2G
5.0 V
(Fixed Voltage)
1% Tolerance
at TA = 25°C
MC33275DT−5.0RKG
MC33275ST−5.0T3G
2% Tolerance at
TJ from −40°C to +125°C
1% Tolerance
at TA = 25°C
NCV33275ST−5.0T3G*
Case
Package
Marking
Shipping†
369A
DPAK
(Pb−Free)
27525G
2500/Tape & Reel
751
SOIC−8
(Pb−Free)
27530
2500/Tape & Reel
488AF
DFN8
(Pb−Free)
27530
3000/Tape & Reel
751
SOIC−8
(Pb−Free)
27533
2500/Tape & Reel
369A
DPAK
(Pb−Free)
27533G
2500/Tape & Reel
318E
SOT−223
(Pb−Free)
27533
4000/Tape & Reel
318E
SOT−223
(Pb−Free)
27533
4000/Tape & Reel
751
SOIC−8
(Pb−Free)
27550
2500/Tape & Reel
369A
DPAK
(Pb−Free)
27550G
2500/Tape & Reel
318E
SOT−223
(Pb−Free)
27550
4000/Tape & Reel
318E
SOT−223
(Pb−Free)
27550
4000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
(A3)
A
A1
C
D2
ÇÇÇÇ
e
8X
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
E2
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
L
4
ÇÇÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
TOP VIEW
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS.
L
L
L1
NOTE 4
DETAIL A
DATE 15 JAN 2009
b
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.21
8X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.63
4.30 2.39
PACKAGE
OUTLINE
8X
0.35
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15232D
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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