MC33363A
High Voltage Switching
Regulator
The MC33363A is a monolithic high voltage switching regulator
that is specifically designed to operate from a rectified 240 Vac line
source. This integrated circuit features an on−chip 700 V / 1.5 A
SENSEFET® power switch, 500 V active off−line startup FET, duty
cycle controlled oscillator, current limiting comparator with a
programmable threshold and leading edge blanking, latching pulse
width modulator for double pulse suppression, high gain error
amplifier, and a trimmed internal bandgap reference. Protective
features include cycle−by−cycle current limiting, input undervoltage
lockout with hysteresis, output overvoltage protection, and thermal
shutdown. This device is available in a 16−lead dual−in−line and
wide body surface mount packages.
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MARKING
DIAGRAMS
SO−16W
DW SUFFIX
CASE 751N
16
MC33363ADW
AWLYYWWG
1
Features
•
•
•
•
•
•
•
•
•
•
•
Enhanced Power Capability Over MC33363
On−Chip 700 V, 1.5 A SENSEFET Power Switch
Rectified 240 Vac Line Source Operation
On−Chip 500 V Active Off−Line Startup FET
Latching PWM for Double Pulse Suppression
Cycle−By−Cycle Current Limiting
Input Undervoltage Lockout with Hysteresis
Output Overvoltage Protection Comparator
Trimmed Internal Bandgap Reference
Internal Thermal Shutdown
These are Pb−Free Devices*
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Startup Input
1
VCC
3
16
4
13
5
12
RT
6
11
CT
7
10
Regulator Output
8
GND
GND
AC Input
Startup Input
Regulator
Output
1
Startup
Mirror
VCC
Reg
8
UVLO
6
OVP
RT
CT
PWM Latch
OSC
7
Driver
S
Q
Power Switch
Drain
9
Overvoltage
Protection Input
Voltage Feedback
Input
Compensation
(Top View)
3
Overvoltage
Protection
Input
DC Output
ORDERING INFORMATION
11
16
See detailed ordering and shipping information on page 7 of
this data sheet.
Power Switch
Drain
R
PWM
Ipk
LEB
Compensation
Thermal
9
EA
GND
10
Voltage
Feedback
4, 5, 12, 13
Input
This device contains 221 active transistors.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Figure 1. Simplified Application
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 10
1
Publication Order Number:
MC33363A/D
MC33363A
MAXIMUM RATINGS (Note 1)
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Rating
Symbol
Value
Unit
Power Switch (Pin 16)
Drain Voltage
Drain Current
VDS
IDS
700
1.5
V
A
Startup Input Voltage (Pin 1)
Vin
500
V
Power Supply Voltage (Pin 3)
VCC
40
V
Input Voltage Range
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Overvoltage Protection Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
VIR
−1.0 to Vreg
V
°C/W
Thermal Characteristics − P Suffix, Dual−In−Line Case 648E
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
(Pins 4, 5, 12, 13)
RqJA
RqJC
80
15
RqJA
RqJC
95
15
Operating Junction Temperature
TJ
−25 to +150
°C
Storage Temperature
Tstg
−55 to +150
°C
DW Suffix, Surface Mount Case 751N
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
(Pins 4, 5, 12, 13)
Refer to Figures 17 and 18 for additional thermal information.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22, Method A114E.
Machine Model Method 150 V per JEDEC Standard JESD22, Method A115A.
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin8 = 1.0 mF, for typical values TJ = 25°C, for min/max
values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted)
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ÁÁÁÁÁÁÁ
ÁÁÁ
Symbol
Min
Typ
Max
Unit
Vreg
5.5
6.5
7.5
V
Line Regulation (VCC = 20 V to 40 V)
Regline
−
30
500
mV
Load Regulation (IO = 0 mA to 10 mA)
Regload
−
44
200
mV
Vreg
5.3
−
8.0
V
Characteristic
REGULATOR (Pin 8)
Output Voltage (IO = 0 mA, TJ = 25°C)
Total Output Variation over Line, Load, and Temperature
OSCILLATOR (Pin 7)
Frequency
CT = 390 pF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
CT = 2.0 nF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
fOSC
Frequency Change with Voltage (VCC = 20 V to 40 V)
kHz
260
255
285
−
310
315
60
59
67.5
−
75
76
DfOSC/DV
−
0.1
2.0
kHz
VFB
2.52
2.6
2.68
V
Regline
−
0.6
5.0
mV
IIB
−
20
500
nA
AVOL
−
82
−
dB
ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
Input Bias Current (VFB = 2.6 V)
Open Loop Voltage Gain (TJ = 25°C)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Tested junction temperature range for the MC33363A:
Thigh = +125°C
Tlow = −25°C
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2
MC33363A
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin8 = 1.0 mF, for typical values TJ = 25°C, for min/max
values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted)
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Characteristic
Symbol
Min
Typ
Max
Unit
Gain Bandwidth Product (f = 100 kHz, TJ = 25°C)
GBW
−
1.0
−
MHz
Output Voltage Swing
High State (ISource = 100 mA, VFB < 2.0 V)
Low State (ISink = 100 mA, VFB > 3.0 V)
VOH
VOL
4.0
−
5.3
0.2
−
0.35
Input Threshold Voltage
Vth
2.47
2.6
2.73
V
Input Bias Current (Vin = 2.6 V)
IIB
−
100
500
nA
DC(max)
DC(min)
48
−
50
0
52
0
−
−
7.5
−
9.0
20
−
−
0.25
−
1.0
50
ERROR AMPLIFIER (Pins 9, 10)
V
OVERVOLTAGE DETECTION (Pin 11)
PWM COMPARATOR (Pins 7, 9)
Duty Cycle
Maximum (VFB = 0 V)
Minimum (VFB = 2.7 V)
%
POWER SWITCH (Pin 16)
Drain−Source On−State Resistance (ID = 200 mA)
TJ = 25°C
TJ = Tlow to Thigh
RDS(on)
Drain−Source Off−State Leakage Current (VDS = 650 V)
TJ = 25°C
TJ = Tlow to Thigh
ID(off)
W
mA
Rise Time
tr
−
50
−
ns
Fall Time
tf
−
50
−
ns
Ilim
0.7
0.9
1.1
A
2.0
2.0
5.0
5.0
8.0
8.0
OVERCURRENT COMPARATOR (Pin 16)
Current Limit Threshold (RT = 13 k)
STARTUP CONTROL (Pin 1)
Peak Startup Current (Vin = 50 V) (TJ = −25°C to 100°C)
VCC = 0 V
VCC = (Vth(on) − 0.2 V)
Istart
mA
Off−State Leakage Current (Vin = 50 V, VCC = 20 V)
ID(off)
−
40
200
mA
Vth(on)
11
14.9
18
V
VCC(min)
7.5
9.5
11.5
V
−
−
0.27
3.4
0.5
5.0
UNDERVOLTAGE LOCKOUT (Pin 3)
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On
TOTAL DEVICE (Pin 3)
Power Supply Current
Startup (VCC = 10 V, Pin 1 Open)
Operating
ICC
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Tested junction temperature range for the MC33363A:
Thigh = +125°C
Tlow = −25°C
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3
f OSC , OSCILLATOR FREQUENCY (Hz)
1.0 M
CT = 100 pF
I PK, POWER SWITCH PEAK DRAIN CURRENT (A)
MC33363A
VCC = 20 V
TA = 25°C
500 k C = 200 pF
T
200 k CT = 500 pF
100 k
50 k
20 k
CT = 1.0 nF
CT = 2.0 nF
CT = 5.0 nF
CT = 10 nF
10 k
7.0
10
15
20
30
70
50
RT, TIMING RESISTOR (kW)
1.5
VCC = 20 V
CT = 1.0 mF
TA = 25°C
1.0
0.8
0.6
0.4
0.3
Inductor supply voltage and inductance value are
adjusted so that Ipk turn-off is achieved at 5.0 ms.
0.2
0.15
7.0
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
0.3
0.2
0.15
0.1
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
15
20
30
70
50
40
50
70
60
50
40
RC/RT Ratio
Charge Resistor
Pin 7 to Vreg
30
1.0
2.0
3.0
5.0
7.0
Figure 4. Oscillator Charge/Discharge
Current versus Timing Resistor
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor Ratio
VCC = 20 V
VO = 1.0 to 4.0 V
RL = 5.0 MW
CL = 2.0 pF
TA = 25°C
80
Gain
60
0
30
60
Phase
90
40
0
150
1.0
180
10 M
0
100 k
1.0 M
Vref
-2.0
2.0
10 k
Source Saturation
(Load to Ground)
-1.0
120
1.0 k
10
0
20
100
70
VCC = 20 V
CT = 2.0 nF
TA = 25°C
RD/RT Ratio
Discharge Resistor
Pin 7 to GND
TIMING RESISTOR RATIO
100
-20
10
30
RT, TIMING RESISTOR (kW)
θ, EXCESS PHASE (DEGREES)
Vsat , OUTPUT SATURATION VOLTAGE (V)
I chg /I dscg , OSCILLATOR
CHARGE/DISCHARGE CURRENT (mA)
VCC = 20 V
TA = 25°C
10
20
Figure 3. Power Switch Peak Drain Current
versus Timing Resistor
0.8
0.08
7.0
15
RT, TIMING RESISTOR (kW)
Figure 2. Oscillator Frequency
versus Timing Resistor
0.5
10
Sink Saturation
(Load to Vref)
VCC = 20 V
TA = 25°C
GND
0
f, FREQUENCY (Hz)
0.2
0.4
0.6
0.8
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Error Amp Output Saturation
Voltage versus Load Current
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4
1.0
MC33363A
VCC = 20 V
AV = -1.0
CL = 10 pF
TA = 25°C
1.75 V
1.75 V
0.50 V
1.70 V
1.0 ms/DIV
1.0 ms/DIV
Figure 8. Error Amplifier Small Signal
Transient Response
Figure 9. Error Amplifier Large Signal
Transient Response
8
0
-20
Istart, STARTUP CURRENT (mA)
VCC = 20 V
RT = 10 k
TA = 25°C
-40
-60
-80
0
4.0
8.0
12
16
20
VPin1 = 50 V
TA = 25°C
7
6
5
4
3
2
1
0
Ireg, REGULATOR SOURCE CURRENT (mA)
4
6
8
10
VCC, SUPPLY VOLTAGE (V)
Figure 10. Regulator Output Voltage
Change versus Source Current
Figure 11. Peak Startup Current
versus Power Supply Voltage
0
2
8
Istart, STARTUP CURRENT (mA)
Δ V reg, REGULATOR VOLTAGE CHANGE (mV)
0.5 V/DIV
3.00 V
20 mV/DIV
1.80 V
VCC = 20 V
AV = -1.0
CL = 10 pF
TA = 25°C
7
VCC = 0 V
TA = 25°C
6
5
4
VCC = 14 V
TA = 25°C
3
2
1
0
0
10
20
30
40
50
VPin1, STARTUP PIN VOLTAGE (V)
Figure 12. Peak Startup Current versus Startup
Input Voltage
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5
12
14
32
ID = 200 mA
24
16
8.0
0
-50
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible.
-25
0
50
75
100
125
80
40
0
1.0
COSS measured at 1.0 MHz with 50 mVpp.
10
100
1000
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 13. Power Switch Drain−Source
On−Resistance versus Temperature
Figure 14. Power Switch
Drain−Source Capacitance versus Voltage
100
Rθ JA , THERMAL RESISTANCE
JUNCTION-TO-AIR (° C/W)
CT = 390 pF
CT = 2.0 nF
2.4
1.6
RT = 10 k
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = GND
TA = 25°C
0.8
0
10
20
30
L = 12.7 mm of 2.0 oz.
copper. Refer to Figures
17 and 18.
10
1.0
0.01
40
0.1
1.0
10
100
VCC, SUPPLY VOLTAGE (V)
t, TIME (s)
Figure 15. Supply Current versus Supply Voltage
Figure 16. DW and P Suffix Transient
Thermal Resistance
2.8
PD(max) for TA = 50°C
90
2.4
ÎÎÎÎÎ
ÎÎÎÎÎ
80
Printed circuit board heatsink example
70
2.0 oz
Copper
L
60
L
3.0 mm
Graphs represent symmetrical layout
50
2.0
1.6
1.2
0.8
RqJA
0.4
40
0
10
20
30
40
100
R θ JA, THERMAL RESISTANCE
JUNCTION-TO-AIR (° C/W)
100
30
120
TA, AMBIENT TEMPERATURE (°C)
3.2
0
VCC = 20 V
TA = 25°C
150
PD, MAXIMUM POWER DISSIPATION (W)
I CC, SUPPLY CURRENT (mA)
25
160
0
50
ÎÎ
ÎÎÎ
ÎÎÎÎÎ
Printed circuit board heatsink example
80
L
RqJA
60
2.0 oz
Copper
L
3.0 mm
Graphs represent symmetrical layout
4.0
3.0
2.0
40
PD(max) for TA = 70°C
20
0
5.0
0
L, LENGTH OF COPPER (mm)
10
20
1.0
30
40
0
50
P D , MAXIMUM POWER DISSIPATION (W)
4.0
3.6
Rθ JA , THERMAL RESISTANCE
JUNCTION-TO-AIR (° C/W)
COSS, DRAIN-SOURCE CAPACITANCE (pF)
R DS(on), DRAIN-SOURCE ON-RESISTANCE ( Ω )
MC33363A
L, LENGTH OF COPPER (mm)
Figure 17. DW Suffix (SOP−16L) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
Figure 18. P Suffix (DIP−16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
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6
MC33363A
PIN FUNCTION DESCRIPTION
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Pin
Function
Description
1
Startup Input
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain
of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and
charges an external capacitor that connects from the VCC pin to ground.
2
−
This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1 and
the VCC potential on Pin 3.
3
VCCCC
This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1.
When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is
supplied from an auxiliary transformer winding.
4, 5, 12, 13
GND
6
RT
Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
7
CT
Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT,
programs the Oscillator frequency.
8
Regulator Output
This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor
of at least 1.0 mF for stability.
9
Compensation
This pin is the Error Amplifier output and is made available for loop compensation. It can be used
as an input to directly control the PWM Comparator.
10
Voltage Feedback
Input
11
Overvoltage
Protection Input
This input provides runaway output voltage protection due to an external component or
connection failure in the control loop feedback signal path. It has a 2.6 V threshold and normally
connects through a resistor divider to the converter output, or to a voltage that represents the
converter output.
14, 15
−
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
16
Power Switch
Drain
These pins are the control circuit grounds. They are part of the IC lead frame and provide a
thermal path from the die to the printed circuit board.
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 700 V and 1.0 A.
ORDERING INFORMATION
Package
Shipping†
MC33363ADWG
SOIC−16WB
(Pb−Free)
47 Units / Rail
MC33363ADWR2G
SOIC−16WB
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MC33363A
AC Input
Startup Input
Startup
Control
Current
Mirror
Regulator Output
6.5 V
8
Band Gap
Regulator
I
VCC
2.25 I
CT
Overvoltage
Protection
Input
14.5 V/
9.5 V
4I
11
OVP
2.6 V
Oscillator
7
DC
Output
3
UVLO
6
RT
1
16
PWM Latch
Power Switch
Drain
Driver
S
Q
R
PWM
Comparator
Leading Edge
Blanking
6.0
Thermal
Shutdown
Current Limit
Comparator
Compensation
450
9
270 μA
Gnd
Error
Amplifier
2.6 V
10
Voltage
Feedback Input
4, 5, 12, 13
Figure 19. Representative Block Diagram
2.6 V
Capacitor CT
0.6 V
Compensation
Oscillator Output
PWM
Comparator
Output
PWM Latch
Q Output
Current Limit
Propagation
Delay
Power Switch
Gate Drive
Current
Limit
Threshold
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range
Figure 20. Timing Diagram
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8
Output Overload
MC33363A
OPERATING DESCRIPTION
Introduction
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for CT
values greater than 500 pF. For smaller values of CT, refer to
Figure 2. Note that resistor RT also programs the Current
Limit Comparator threshold.
The MC33363A represents a new higher level of
integration by providing all the active high voltage power,
control, and protection circuitry required for
implementation of a flyback or forward converter on a single
monolithic chip. This device is designed for direct operation
from a rectified 240 Vac line source and requires a minimum
number of external components to implement a complete
converter. A description of each of the functional blocks is
given below, and the representative block and timing
diagrams are shown in Figures 19 and 20.
I
Current Limit Comparator and Power Switch
The MC33363A uses cycle−by−cycle current limiting as
a means of protecting the output switch transistor from
overstress. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp−up period.
The Power Switch is constructed as a SENSEFET
allowing a virtually lossless method of monitoring the drain
current. It consists of a total of 2819 cells, of which 65 are
connected to a 6.0 W ground−referenced sense resistor. The
Current Sense Comparator detects if the voltage across the
sense resistor exceeds the reference level that is present at
the inverting input. If exceeded, the comparator quickly
resets the PWM Latch, thus protecting the Power Switch.
The current limit reference level is generated by the 2.25 I
output of the Current Mirror. This current causes a reference
voltage to appear across the 450 W resistor. This voltage
level, as well as the Oscillator charge/discharge current are
both set by resistor RT. Therefore when selecting the values
for RT and CT, RT must be chosen first to set the Power
Switch peak drain current, while CT is chosen second to set
the desired Oscillator frequency. A graph of the Power
Switch peak drain current versus RT is shown in Figure 3
with the related formula below.
Current
Mirror
8
2.25 I
I
RC
Current
Limit
Reference
6
RT
4I
RD
CT
7
Oscillator
chgńdscg
4C
T
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non−inverting
input, while the error amplifier output is applied into the
inverting input. The Oscillator applies a set pulse to the
PWM Latch while CT is discharging, and upon reaching the
valley voltage, Power Switch conduction is initiated. When
CT charges to a voltage that exceeds the error amplifier
output, the PWM Latch is reset, thus terminating Power
Switch conduction for the duration of the oscillator ramp−up
period. This PWM Comparator/Latch combination
prevents multiple output pulses during a given oscillator
clock cycle. The timing diagram shown in Figure 20
illustrates the Power Switch duty cycle behavior versus the
Compensation voltage.
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 4. Capacitor CT is charged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50%
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate
driver high. This causes the Power Switch gate drive to be
held in a low state, thus producing a well controlled amount
of output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
path to CT, Figure 21. In order to increase the maximum duty
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor RC is connected from Pin 7 to the
Regulator Output. Figure 5 shows an obtainable range of
maximum output duty cycle versus the ratio of either RC or
RD with respect to RT.
1.0
f [
PWM Comparator and Latch
Oscillator and Current Mirror
Regulator Output
I
5.4
+ R
chgńdscg
T
Blanking
Pulse
I
PWM
Comparator
pk
+ 15.95
ǒ Ǔ
R
T − 1.14
1000
The Power Switch is designed to directly drive the
converter transformer and is capable of switching a
Figure 21. Maximum Duty Cycle Modification
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9
MC33363A
Startup Control
maximum of 700 V and 1.0 A. Proper device voltage
snubbing and heatsinking are required for reliable operation.
A Leading Edge Blanking circuit was placed in the current
sensing signal path. This circuit prevents a premature reset
of the PWM Latch. The premature reset is generated each
time the Power Switch is driven into conduction. It appears
as a narrow voltage spike across the current sense resistor,
and is due to the MOSFET gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. The Leading Edge Blanking circuit has a
dynamic behavior in that it masks the current signal until the
Power Switch turn−on transition is completed. The current
limit propagation delay time is typically 300 ns. This time is
measured from when an overcurrent appears at the Power
Switch drain, to the beginning of turn−off.
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33363A. This circuitry allows for increased converter
efficiency by eliminating the external startup resistor, and its
associated power dissipation, commonly used in most
off−line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input,
Pin 1. This causes the MOSFET to enhance and supply
internal bias as well as charge current to the VCC bypass
capacitor that connects from Pin 3 to ground. When VCC
reaches the UVLO upper threshold of 15.2 V, the IC
commences operation and the startup MOSFET is turned
off. Operating bias is now derived from the auxiliary
transformer winding, and all of the device power is
efficiently converted down from the rectified ac line.
Error Amplifier
Regulator
An fully compensated Error Amplifier with access to the
inverting input and output is provided for primary side
voltage sensing, Figure 19. It features a typical dc voltage
gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with
78 degrees of phase margin, Figure 6. The noninverting
input is internally biased at 2.6 V ±3.1% and is not pinned
out. The Error Amplifier output is pinned out for external
loop compensation and as a means for directly driving the
PWM Comparator. The output was designed with a limited
sink current capability of 270 mA, allowing it to be easily
overridden with a pull−up resistor. This is desirable in
applications that require secondary side voltage sensing,
Figure 22. In this application, the Voltage Feedback Input is
connected to the Regulator Output. This disables the Error
Amplifier by placing its output into the sink state, allowing
the optocoupler transistor to directly control the PWM
Comparator.
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control
system circuitry. It is capable of up to 10 mA and has
short−circuit protection. This output requires an external
bypass capacitor of at least 1.0 mF for stability.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature
is exceeded. When activated, typically at 155°C, the Latch
is forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed to ‘set’ when the Power Switch temperature
falls below 145°C. This feature is provided to prevent
catastrophic failures from accidental device overheating. It
is not intended to be used as a substitute for proper
heatsinking.
The MC33363A is contained in a heatsinkable plastic
dual−in−line package in which the die is mounted on a special
heat tab copper alloy lead frame. This tab consists of the four
center ground pins that are specifically designed to improve
thermal conduction from the die to the circuit board.
Figures 17 and 18 show a simple and effective method of
utilizing the printed circuit board medium as a heat dissipater
by soldering these pins to an adequate area of copper foil. This
permits the use of standard layout and mounting practices
while having the ability to halve the junction to air thermal
resistance. The examples are for a symmetrical layout on a
single−sided board with two ounce per square foot of copper.
Figure 23 shows a practical example of a printed circuit board
layout that utilizes the copper foil as a heat dissipater. Note
that a jumper was added to the layout from Pins 8 to 10 in
order to enhance the copper area near the device for improved
thermal conductivity. The application circuit requires two
ounce copper foil in order to obtain 8.0 W of continuous
output power at room temperature.
Overvoltage Protection
An Overvoltage Protection Comparator is included to
eliminate the possibility of runaway output voltage. This
condition can occur if the control loop feedback signal path
is broken due to an external component or connection
failure. The comparator is normally used to monitor the
primary side VCC voltage. When the 2.6 V threshold is
exceeded, it will immediately turn off the Power Switch, and
protect the load from a severe overvoltage condition. This
input can also be driven from external circuitry to inhibit
converter operation.
Undervoltage Lockout
An Undervoltage Lockout (UVLO) comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output
stage is enabled. The UVLO comparator monitors the VCC
voltage at Pin 3 and when it exceeds 14.5 V, the reset signal
is removed from the PWM Latch allowing operation of the
Power Switch. To prevent erratic switching as the threshold
is crossed, 5.0 V of hysteresis is provided.
www.onsemi.com
10
MC33363A
F1
1.0 A D4
C1
47
D3
1N4006
92 to 276
Vac Input
D2
C5
4.0 nF
D1
D6
R5 MUR
39 120
Startup
C4
1.0
3
Reg
8
UVLO
14.5 V/
9.5 V
6
R1
13 k
C3
1200 pF
Osc
7
11
D7
T1 MBR
1635
C2
10
R4
5.1 k
C8
330
1
2
L1
5.0 μH 5.05 V/3.0 A
DC Output
+
R8
220
R9
2.80 k
C7
100 nF
IC2
3
MOC
8103 IC3
TL431B 2
16
Driver
S
C9 C10
330 330
R3
1.0 k
OVP
2.6 V
PWM Latch
R7
2.2 k
1.0 W
D5
MUR
1100E
1
Mirror
C6
47 pF
R6
180 k
1.0 W
Q
ILimit
4
Thermal
9
R2
2.7 k
2.6 V
10
EA
IC1 MC33363A
4, 5, 12, 13
Figure 22. 15 W Off−Line Converter
Table 1. CONVERTER TEST DATA
Test
Conditions
Results
Line Regulation
Vin = 92 Vac to 276 Vac, IO 3.0 A
D = 1.0 mV
Load Regulation
Vin = 115 Vac, IO = 0.75 A to 3.0 A
D = 5.0 mV
Vin = 230 Vac, IO = 0.75 A to 3.0 A
D = 5.0 mV
Vin = 115 Vac, IO = 3.0 A
Triangular = 2.0 mVpp, Spike = 32 mVpp
Vin = 230 Vac, IO = 3.0 A
Triangular = 2.0 mVpp, Spike = 34 mVpp
Vin = 115 Vac, IO = 3.0 A
76.8%*
Vin = 230 Vac, IO = 3.0 A
76.8%
Output Ripple
Efficiency
C12
1.0
R10
2.74 k
5
LEB
270 μA
220
−
R
PWM
1
C11
This data was taken with the components listed below mounted on the printed circuit board shown in Figure 23.
*With MBR2535CTL, 78.8% efficiency. PCB layout modification is required to use this rectifier.
For high efficiency and small circuit board size, the Sanyo Os−Con capacitors are recommended for C8, C9, C10
and C11.
C8, C9, C10 = Sanyo Os−Con #6SA330M, 330 mF 6.3 V.
C11 = Sanyo Os−Con #10SA220M, 220 mF 10 V.
L1 = Coilcraft S5088−A, 5.0 mH, 0.11 W.
T1 = Coilcraft U6875−A
Primary: 77 turns of # 28 AWG, Pin 1 = start, Pin 8 = finish.
Two layers 0.002″ Mylar tape.
Secondary: 5 turns of # 22 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish.
Two layers 0.002″ Mylar tape.
Auxiliary: 13 turns of # 28 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish.
Two layers 0.002″ Mylar tape.
Gap: 0.011″ total for a primary inductance (LP) of 620 mH.
Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.
www.onsemi.com
11
MC33363A
Caution!
High
Voltages
DC Output
C4
R3
R3
R2
R9
J1
R1
D1
IC2
D2
R10
IC3
C3
C7
C12
C11
IC1
F1
AC
Line
Input
R8
R4
C2
L1
R5
D6
C10
D3
D4
D5
C9
R7
T1
C1
R6
D7
C5
C8
C6
1
(Top View)
2.75"
2.25”
MC33363A
(Bottom View)
Figure 23. Printed Circuit Board and Component Layout (Circuit of Figure 22)
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 MINUS PINS, 2, 14, 15
CASE 751N−01
ISSUE O
16
1
SCALE 1:1
DATE 02/28/95
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
T
16
9
−B−
1
P
0.010 (0.25)
M
B
M
8
13X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
−T−
S
K
9X
DOCUMENT NUMBER:
DESCRIPTION:
SEATING
PLANE
M
G
98ASH70300A
DIM
A
B
C
D
F
G
J
K
M
P
R
S
T
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
2.54 BSC
3.81 BSC
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
0.100 BSC
0.150 BSC
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SOIC−16 MINUS PINS, 2, 14, 15
PAGE 1 OF 1
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