MC33502
1.0 V, Rail−to−Rail, Dual
Operational Amplifier
The MC33502 operational amplifier provides rail−to−rail operation
on both the input and output. The output can swing within 50 mV of
each rail. This rail−to−rail operation enables the user to make full use
of the entire supply voltage range available. It is designed to work at
very low supply voltages (1.0 V and ground), yet can operate with a
supply of up to 7.0 V and ground. Output current boosting techniques
provide high output current capability while keeping the drain current
of the amplifier to a minimum.
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MARKING
DIAGRAMS
8
Features
• Low Voltage, Single Supply Operation
•
•
•
•
•
•
•
•
•
•
•
•
(1.0 V and Ground to 7.0 V and Ground)
High Input Impedance: Typically 40 fA Input Current
Typical Unity Gain Bandwidth @ 5.0 V = 5.0 MHz,
@ 1.0 V = 4.0 MHz
High Output Current (ISC = 40 mA @ 5.0 V, 13 mA @ 1.0 V)
Output Voltage Swings within 50 mV of Both Rails @ 1.0 V
Input Voltage Range Includes Both Supply Rails
High Voltage Gain: 100 dB Typical @ 1.0 V
No Phase Reversal on the Output for Over−Driven Input Signals
Input Offset Trimmed to 0.5 mV Typical
Low Supply Current (ID = 1.2 mA/per Amplifier, Typical)
600 W Drive Capability
Extended Operating Temperature Range (−40 to 105°C)
Pb−Free Packages are Available
8
1
8
SOIC−8
D SUFFIX
CASE 751
8
1
33502
ALYW
G
1
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Output 1 1
Inputs 1
Single Cell NiCd/Ni MH Powered Systems
Interface to DSP
Portable Communication Devices
Low Voltage Active Filters
Telephone Circuits
Instrumentation Amplifiers
Audio Applications
Power Supply Monitor and Control
Compatible with VCX Logic
MC33502P
AWL
YYWWG
1
8 VCC
2
Applications
•
•
•
•
•
•
•
•
•
PDIP−8
P SUFFIX
CASE 626
3
7 Output 2
1
2
VEE 4
6
5
Inputs 2
(Dual, Top View)
ORDERING INFORMATION
Device
Package
Shipping
PDIP−8
50 Units/Rail
PDIP−8
(Pb−Free)
50 Units/Rail
SOIC−8
98 Units/Rail
MC33502DG
SOIC−8
(Pb−Free)
98 Units/Rail
MC33502DR2
SOIC−8
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
MC33502P
MC33502PG
MC33502D
MC33502DR2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 8
1
Publication Order Number:
MC33502/D
MC33502
Base
Current
Boost
Input
Stage
Inputs
Offset
Voltage
Trim
Buffer with 0 V
Level Shift
Saturation
Detector
Output
Stage
Outputs
Base
Current
Boost
This device contains 98 active transistors per amplifier.
Figure 1. Simplified Block Diagram
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rating
Symbol
Value
Unit
VS
7.0
V
ESD Protection Voltage at any Pin
Human Body Model
VESD
2000
V
Voltage at Any Device Pin
VDP
VS ±0.3
V
Input Differential Voltage Range
VIDR
VCC to VEE
V
Common Mode Input Voltage Range
VCM
VCC to VEE
V
tS
Note 1
s
Supply Voltage (VCC to VEE)
Output Short Circuit Duration
Maximum Junction Temperature
TJ
150
°C
Storage Temperature Range
Tstg
−65 to 150
°C
Maximum Power Dissipation
PD
Note 1
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
2. ESD data available upon request.
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2
MC33502
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VCM = VO = VCC/2, RL to VCC/2, TA = 25°C, unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Symbol
Characteristic
Input Offset Voltage (VCM = 0 to VCC)
VCC = 1.0 V
TA = 25°C
TA = −40° to 105°C
VCC = 3.0 V
TA = 25°C
TA = −40° to 105°C
VCC = 5.0 V
TA = 25°C
TA = −40° to 105°C
Min
Typ
Max
VIO
Unit
mV
−5.0
−7.0
0.5
−
5.0
7.0
−5.0
−7.0
0.5
−
5.0
7.0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
−5.0
−7.0
0.5
−
5.0
7.0
DVIO/DT
−
8.0
−
mV/°C
I IIB I
−
0.00004
10
nA
Common Mode Input Voltage Range
VICR
VEE
−
VCC
Large Signal Voltage Gain
VCC = 1.0 V (TA = 25°C)
RL = 10 kW
RL = 1.0 kW
VCC = 3.0 V (TA = 25°C)
RL = 10 kW
RL = 1.0 kW
VCC = 5.0 V (TA = 25°C)
RL = 10 kW
RL = 1.0 kW
AVOL
Output Voltage Swing, High (VID = ±0.2 V)
VCC = 1.0 V (TA = 25°C)
RL = 10 kW
RL = 600 W
VCC = 1.0 V (TA = −40° to 105°C)
RL = 10 kW
RL = 600 W
VCC = 3.0 V (TA = 25°C)
RL = 10 kW
RL = 600 W
VCC = 3.0 V (TA = −40° to 105°C)
RL = 10 kW
RL = 600 W
VCC = 5.0 V (TA = 25°C)
RL = 10 kW
RL = 600 W
VCC = 5.0 V (TA = −40° to 105°C)
RL = 10 kW
RL = 600 W
VOH
Input Offset Voltage Temperature Coefficient (RS = 50 W)
TA = −40° to 105°C
Input Bias Current (VCC = 1.0 to 5.0 V)
V
kV/V
25
5.0
100
50
−
−
50
25
500
100
−
−
50
25
500
200
−
−
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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3
V
0.9
0.85
0.95
0.88
−
−
0.85
0.8
−
−
−
−
2.9
2.8
2.93
2.84
−
−
2.85
2.75
−
−
−
−
4.9
4.75
4.92
4.81
−
−
4.85
4.7
−
−
−
−
MC33502
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VCM = VO = VCC/2, RL to VCC/2, TA = 25°C, unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Characteristic
Symbol
Output Voltage Swing, Low (VID = ±0.2 V)
VCC = 1.0 V (TA = 25°C)
RL = 10 kW
RL = 600 W
VCC = 1.0 V (TA = −40° to 105°C)
RL = 10 kW
RL = 600 W
VCC = 3.0 V (TA = 25°C)
RL = 10 kW
RL = 600 W
VCC = 3.0 V (TA = −40° to 105°C)
RL = 10 kW
RL = 600 W
VCC = 5.0 V (TA = 25°C)
RL = 10 kW
RL = 600 W
VCC = 5.0 V (TA = −40° to 105°C)
RL = 10 kW
RL = 600 W
VOL
Common Mode Rejection (Vin = 0 to 5.0 V)
Power Supply Rejection
VCC/VEE = 5.0 V/Ground to 3.0 V/Ground
Min
Typ
Max
Unit
V
0.05
0.1
0.02
0.05
−
−
0.1
0.15
−
−
−
−
0.05
0.1
0.02
0.08
−
−
0.1
0.15
−
−
−
−
0.05
0.15
0.02
0.1
−
−
0.1
0.2
−
−
−
−
CMR
60
75
−
dB
PSR
60
75
−
dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Short Circuit Current (Vin Diff = ±1.0 V)
VCC = 1.0 V
Source
Sink
VCC = 3.0 V
Source
Sink
VCC = 5.0 V
Source
Sink
ISC
Power Supply Current (Per Amplifier, VO = 0 V)
VCC = 1.0 V
VCC = 3.0 V
VCC = 5.0 V
VCC = 1.0 V (TA = −40 to 105°C)
VCC = 3.0 V (TA = −40 to 105°C)
VCC = 5.0 V (TA = −40 to 105°C)
ID
mA
6.0
10
13
13
26
26
15
40
32
64
60
140
20
40
40
70
140
140
−
−
−
−
−
−
1.2
1.5
1.65
−
−
−
1.75
2.0
2.25
2.0
2.25
2.5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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4
mA
MC33502
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = 0 V, VCM = VO = VCC/2, TA = 25°C, unless otherwise noted.)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Symbol
Characteristic
Slew Rate (VS = ±2.5 V, VO = −2.0 to 2.0 V, RL = 2.0 kW, AV = 1.0)
Positive Slope
Negative Slope
Min
Typ
Max
2.0
2.0
3.0
3.0
6.0
6.0
3.0
3.5
4.0
4.0
4.5
5.0
6.0
7.0
8.0
SR
Gain Bandwidth Product (f = 100 kHz)
VCC = 0.5 V, VEE = −0.5 V
VCC = 1.5 V, VEE = −1.5 V
VCC = 2.5 V, VEE = −2.5 V
Unit
V/ms
GBW
MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Gain Margin (RL =10 kW, CL = 0 pF)
Am
−
6.5
−
dB
Phase Margin (RL = 10 kW, CL = 0 pF)
φm
−
60
−
Deg
Channel Separation (f = 1.0 Hz to 20 kHz, RL = 600 W)
CS
−
120
−
dB
Power Bandwidth (VO = 4.0 Vpp, RL = 1.0 kW, THD ≤1.0%)
BWP
−
200
−
kHz
Total Harmonic Distortion (VO = 4.5 Vpp, RL = 600 W, AV = 1.0)
f = 1.0 kHz
f = 10 kHz
THD
−
−
0.004
0.01
−
−
%
Differential Input Resistance (VCM = 0 V)
Rin
−
>1.0
−
terraW
Differential Input Capacitance (VCM = 0 V)
Cin
−
2.0
−
pF
Equivalent Input Noise Voltage (VCC = 1.0 V, VCM = 0 V, VEE = Gnd,
RS = 100 W)
f = 1.0 kHz
en
nV/√Hz
−
30
−
VCC
IN−
IN+
Offset
Voltage
Trim
VCC
VCC
VCC
Output
Voltage
Saturation
Detector
Body
Bias
Figure 2. Representative Block Diagram
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5
Clamp
Out
MC33502
Output Stage
General Information
The MC33502 dual operational amplifier is unique in its
ability to provide 1.0 V rail−to−rail performance on both the
input and output by using a SMARTMOSt process. The
amplifier output swings within 50 mV of both rails and is
able to provide 50 mA of output drive current with a 5.0 V
supply, and 10 mA with a 1.0 V supply. A 5.0 MHz
bandwidth and a slew rate of 3.0 V/ms is achieved with high
speed depletion mode NMOS (DNMOS) and vertical PNP
transistors. This device is characterized over a temperature
range of −40°C to 105°C.
An additional feature of this device is an “on demand”
base current cancellation amplifier. This feature provides
base drive to the output power devices by making use of a
buffer amplifier to perform a voltage−to−current
conversion. This is done in direct proportion to the load
conditions. This “on demand” feature allows these
amplifiers to consume only a few micro−amps of current
when the output stage is in its quiescent mode. Yet it
provides high output current when required by the load. The
rail−to−rail output stage current boost circuit provides
50 mA of output current with a 5.0 V supply (For a 1.0 V
supply output stage will do 10 mA) enabling the operational
amplifier to drive a 600 W load. A buffer is necessary to
isolate the load current effects in the output stage from the
input stage. Because of the low voltage conditions, a
DNMOS follower is used to provide an essentially zero
voltage level shift. This buffer isolates any load current
changes on the output stage from loading the input stage. A
high speed vertical PNP transistor provides excellent
frequency performance while sourcing current. The
operational amplifier is also internally compensated to
provide a phase margin of 60 degrees. It has a unity gain of
5.0 MHz with a 5.0 V supply and 4.0 MHz with a 1.0 V
supply.
Circuit Information
Input Stage
One volt rail−to−rail performance is achieved in the
MC33502 at the input by using a single pair of depletion
mode NMOS devices (DNMOS) to form a differential
amplifier with a very low input current of 40 fA. The normal
input common mode range of a DNMOS device, with an ion
implanted negative threshold, includes ground and relies on
the body effect to dynamically shift the threshold to a
positive value as the gates are moved from ground towards
the positive supply. Because the device is manufactured in
a p−well process, the body effect coefficient is sufficiently
large to ensure that the input stage will remain substantially
saturated when the inputs are at the positive rail. This also
applies at very low supply voltages. The 1.0 V rail−to−rail
input stage consists of a DNMOS differential amplifier, a
folded cascode, and a low voltage balanced mirror. The low
voltage cascoded balanced mirror provides high 1st stage
gain and base current cancellation without sacrificing signal
integrity. Also, the input offset voltage is trimmed to less
than 1.0 mV because of the limited available supply voltage.
The body voltage of the input DNMOS differential pair is
internally trimmed to minimize the input offset voltage. A
common mode feedback path is also employed to enable the
offset voltage to track over the input common mode voltage.
The total operational amplifier quiescent current drop is
1.3 mA/amp.
Low Voltage Operation
The MC33502 will operate at supply voltages from 0.9 to
7.0 V and ground. When using the MC33502 at supply
voltages of less than 1.2 V, input offset voltage may
increase slightly as the input signal swings within
approximately 50 mV of the positive supply rail. This effect
occurs only for supply voltages below 1.2 V, due to the input
depletion mode MOSFETs starting to transition between the
saturated to linear region, and should be considered when
designing high side dc sensing applications operating at the
positive supply rail. Since the device is rail−to−rail on both
input and output, high dynamic range single battery cell
applications are now possible.
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6
MC33502
0
0
TA = −55°C
400
600
600
VCC = 5.0 V
VEE = 0 V
RL to VCC/2
400
200
1.0 k
10 k
VEE
100 k
1.0 M
Source
Saturation
−1.0
0.5
0
0
4.0
TA = 125°C
TA = −55°C
8.0
VEE
12
16
20
24
IO, OUTPUT CURRENT (mA)
Figure 4. Drive Output Source/Sink Saturation
Voltage versus Load Current
Figure 3. Output Saturation
versus Load Resistance
1000
100
0
100
Gain
80
Phase
AVOL, GAIN (dB)
10
1.0
0.1
0.01
0.001
25
50
75
100
Phase Margin = 60°
90
40
135
VCC = 2.5 V
VEE = −2.5 V
RL = 10 k
0
1.0
125
45
60
20
10
100
180
1.0 k
10 k
100 k
1.0 M
10 M
TA, AMBIENT TEMPERATURE (°C)
f, FREQUENCY (Hz)
Figure 5. Input Current versus Temperature
Figure 6. Gain and Phase versus Frequency
1.0 V/DIV (mV)
VCC = 0.5 V
VEE = −0.5 V
ACL = 1.0
CL = 10 pF
RL = 10 k
TA = 25°C
20 mV/DIV
IIB, INPUT CURRENT (pA)
TA = 25°C
VCC − VEE = 5.0 V
RL, LOAD RESISTANCE (W)
0
TA = 25°C
Sink
Saturation
1.0
10 M
TA = 125°C
VCC = 2.5 V
VEE = −2.5 V
ACL = 1.0
CL = 10 pF
RL = 600 W
TA = 25°C
t, TIME (500 ms/DIV)
t, TIME (1.0 ms/DIV)
Figure 7. Transient Response
Figure 8. Slew Rate
http://onsemi.com
7
φ m, EXCESS PHASE (DEGREES)
0
100
VCC
−0.5
VCC
Vsat, OUTPUT SATURATION VOLTAGE (V)
Vsat, OUTPUT SATURATION VOLTAGE (mV)
200
120
1600
1400
ΔAVOL , OPEN LOOP GAIN (dB)
PDmax, MAXIMUM POWER DISSIPATION (mW)
MC33502
1200
SO−8 Pkg
1000
DIP Pkg
800
600
400
200
0
−55
−25
0
25
50
75
100
110
100
90
80
70
60
VCC = 2.5 V
VEE = −2.5 V
RL = 600 W
50
40
30
20
−55
125
−25
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Maximum Power Dissipation
versus Temperature
CMR, COMMON MODE REJECTION (dB)
VO, OUTPUT VOLTAGE (Vpp)
6.0
5.0
4.0
1.0
0
10
VCC = 2.5 V
VEE = −2.5 V
AV = 1.0
RL = 600 W
TA = 25°C
100
1.0 k
10 k
100 k
40
VCC = 2.5 V
VEE = −2.5 V
TA = 25°C
20
100
IISCI, OUTPUT SHORT CIRCUIT CURRENT (mA)
PSR, POWER SUPPLY REJECTION (dB)
80
VCC = 0.5 V
VEE = −0.5 V
Either VCC or VEE
TA = 25°C
0
100
1.0 k
10 k
100 k
1.0 M
Figure 12. Common Mode Rejection
versus Frequency
VCC = 2.5 V
VEE = −2.5 V
100
1.0 k
f, FREQUENCY (Hz)
120
10
125
60
0
10
1.0 M
140
20
100
80
Figure 11. Output Voltage versus Frequency
40
75
100
f, FREQUENCY (Hz)
60
50
120
7.0
2.0
25
Figure 10. Open Loop Voltage Gain
versus Temperature
8.0
3.0
0
TA, AMBIENT TEMPERATURE (°C)
10 k
100 k
100
VCC = 2.5 V
VEE = −2.5 V
TA = 25°C
80
Sink
60
40
Source
20
0
0
f, FREQUENCY (Hz)
0.5
1.0
1.5
2.0
|VS| − |VO| (V)
Figure 13. Power Supply Rejection
versus Frequency
Figure 14. Output Short Circuit Current
versus Output Voltage
http://onsemi.com
8
2.5
ICC, SUPPLY CURRENT PER AMPLIFIER (mA)
IISCI, OUTPUT SHORT CIRCUIT CURRENT (mA)
MC33502
100
Sink
80
60
VCC = 2.5 V
VEE = −2.5 V
40
20
Source
0
−55
−25
0
25
50
75
100
2.5
2.0
1.5
TA = 125°C
1.0
TA = 25°C
0.5
0
125
0
±0.5
Figure 15. Output Short Circuit Current
versus Temperature
±2.5
PERCENTAGE OF AMPLIFIERS (%)
50
VCC = 3.0 V
VO = 1.5 V
VEE = 0 V
60 Amplifiers Tested
from 2 Wafer Lots
40
30
20
10
0
−50 −40
−30
−20
−10
0
10
20
30
40
40
30
VCC = 3.0 V
VO = 1.5 V
VEE = 0 V
TA = 25°C
60 Amplifiers Tested
from 2 Wafer Lots
20
10
0
−5.0 −4.0 −3.0 −2.0
50
Figure 17. Input Offset Voltage
Temperature Coefficient Distribution
THD, TOTAL HARMONIC DISTORTION (%)
AV = 1000
AV = 100
AV = 10
0.1
AV = 1.0
0.01
Vout = 0.5 Vpp
RL = 600 W
10
100
VCC − VEE = 1.0 V
1.0 k
10 k
0
1.0
2.0
3.0
4.0
5.0
Figure 18. Input Offset Voltage Distribution
10
1.0
−1.0
INPUT OFFSET VOLTAGE (mV)
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/°C)
THD, TOTAL HARMONIC DISTORTION (%)
±2.0
Figure 16. Supply Current per Amplifier
versus Supply Voltage with No Load
50
0.001
±1.5
VCC, |VEE|, SUPPLY VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
PERCENTAGE OF AMPLIFIERS (%)
±1.0
TA = −55°C
100 k
10
Vout = 4.0 Vpp
RL = 600 W
1.0
AV = 1000
AV = 100
0.1
AV = 10
0.01
AV = 1.0
0.001
10
100
VCC − VEE = 5.0 V
1.0 k
10 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 19. Total Harmonic Distortion
versus Frequency with 1.0 V Supply
Figure 20. Total Harmonic Distortion
versus Frequency with 5.0 V Supply
http://onsemi.com
9
100 k
MC33502
3.0
VCC − VEE = 5.0 V
− Slew Rate
2.0
VCC − VEE = 1.0 V
− Slew Rate
1.0
0
−55
−25
0
25
50
75
100
3.0
2.0
VCC − VEE = 5.0 V
f = 100 kHz
1.0
0
−55
−25
100
125
100
Φm, PHASE MARGIN (°)
VCC − VEE = 5.0 V
VCC − VEE
= 1.0 V
VCC − VEE
= 5.0 V
VCC − VEE = 1.0 V
RL = 600 W
CL = 0
TA = 25°C
100 k
1.0 M
80
100
VCC − VEE = 5.0 V
RL = 600 W
CL = 100 pF
60
Phase Margin
40
40
20
0
−55
10 M
−25
0
0
125
100
50
VCC − VEE = 5.0 V
RL = 600 W
CL = 100 pF
TA = 25°C
40
30
20
20
Gain Margin
VCC − VEE = 5.0 V
RL = 600 W
TA = 25°C
Phase Margin
50
50
40
40
30
30
20
20
Gain Margin
10
10
10
0
3.0
0
1.0 M
100 k
60
AV GAIN MARGIN (dB)
Φm, PHASE MARGIN (°)
Phase Margin
10 k
75
60
60
60
1.0 k
50
Figure 24. Gain and Phase Margin
versus Temperature
70
100
25
TA, AMBIENT TEMPERATURE (°C)
70
10
20
Gain Margin
Figure 23. Voltage Gain and Phase
versus Frequency
50
80
60
f, FREQUENCY (Hz)
Φm, PHASE MARGIN (°)
75
Figure 22. Gain Bandwidth Product
versus Temperature
−40
10 k
0
10
50
Figure 21. Slew Rate versus Temperature
0
30
25
TA, AMBIENT TEMPERATURE (°C)
20
40
0
TA, AMBIENT TEMPERATURE (°C)
40
AVOL, GAIN (dB)
4.0
125
60
−20
5.0
AV , GAIN MARGIN (dB)
VCC − VEE = 5.0 V
+ Slew Rate
10
30
100
300
1000
0
3000
CL, CAPACITIVE LOAD (pF)
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 25. Gain and Phase Margin versus
Differential Source Resistance
Figure 26. Feedback Loop Gain and Phase
versus Capacitive Load
http://onsemi.com
10
AV , GAIN MARGIN (dB)
SR, SLEW RATE (V/ μs)
VCC − VEE = 1.0 V
+ Slew Rate
GBW, GAIN BANDWIDTH PRODUCT (MHz)
4.0
MC33502
8.0
120
80
60
40
20
VCC − VEE = 5.0 V
RL = 600 W
VO = 4.0 Vpp
TA = 25°C
100
300
10 k
30 k
100 k
RL= 600 W
TA = 25°C
6.0
4.0
2.0
0
300 k
±0.5
0
±1.5
±2.0
±2.5
±3.0
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 27. Channel Separation
versus Frequency
Figure 28. Output Voltage Swing
versus Supply Voltage
±3.5
100
70
VCC − VEE = 5.0 V
TA = 25°C
60
50
40
30
20
100
RL = 600 W
CL = 0
TA = 25°C
80
80
Phase Margin
60
60
40
40
20
20
Gain Margin
10
0
10
100
10 k
1.0 k
0
100 k
0
1
0
2
f, FREQUENCY (Hz)
4
5
6
7
Figure 30. Gain and Phase Margin
versus Supply Voltage
1.6
120
AVOL, OPEN LOOP GAIN (dB)
AVOL ≥ 10 dB
RL = 600 W
1.2
0.8
0.4
0
−55
3
VCC − VEE, SUPPLY VOLTAGE (V)
Figure 29. Equivalent Input Noise Voltage
versus Frequency
VCC−VEE, USEABLE SUPPLY VOLTAGE (V)
±1.0
f, FREQUENCY (Hz)
AV, GAIN MARGIN (dB)
AV = 10
0
30
en, EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
VO, OUTPUT VOLTAGE (Vpp)
100
Φm, PHASE MARGIN (°)
CS, CHANNEL SEPARATION (dB)
AV = 100
−25
0
25
50
75
100
100
80
60
40
0
125
RL = 600 W
TA = 25°C
20
0
1.0
2.0
3.0
4.0
TA, AMBIENT TEMPERATURE (°C)
VCC − VEE, SUPPLY VOLTAGE (V)
Figure 31. Useable Supply Voltage
versus Temperature
Figure 32. Open Loop Gain
versus Supply Voltage
http://onsemi.com
11
5.0
6.0
MC33502
RT
470 k
1.0 V
CT
1.0 nF
1.0 Vpp
−
fO
1.0 kHz
+
f +
O
R1a
470 k
ƪ
R C In
T T
VCC
R2
470 k
R1b
470 k
1
2 (R 1a ) R
1b
R2
Figure 33. 1.0 V Oscillator
Af
Cf
400 pF
Rf
100 k
fL
fH
0.5 V
R2
10 k
1
f +
[ 200 Hz
L 2pR C
1 1
+
VO
−
C1
80 nF
1
[ 4.0 kHz
f +
H 2pRC
f f
R1
10 k −0.5 V
R
A + 1 ) f + 11
f
R2
Figure 34. 1.0 V Voiceband Filter
http://onsemi.com
12
)
ƫ
MC33502
5.0 V
Vref
15 V
15
13
2
16
4
3
1
FB
11
Output A
14
Output B
MC34025
22 k 5
4.7
4.7
8
12
6
0.1
10
470 pF
7
9
From
Current Sense
100 k
1.0 k
+
MC33502
−
3320
Provides current sense
amplification and eliminates
leading edge spike.
1.0 k
Figure 35. Power Supply Application
IO
1.0 V
VO
Rsense
R3
1.0 k
IO
IL
435 mA
463 mA
212 mA
492 mA
DIO/DIL
R4
R1
1.0 k
+
−
SMARTMOS is a trademark of Motorola, Inc.
1.0 k
−120 x 10−6
R5
VL
2.4 k
RL
75
IL
For best performance, use low tolerance resistors.
R2
3.3 k
Figure 36. 1.0 V Current Pump
SMARTMOS is a trademark of Motorola, Inc.
http://onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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