MC33560DW

MC33560 Power Management and Interface IC for Smartcard Readers and Couplers The MC33560 is an interface IC for smartcard reader/writer applications. It enables the management of any type of smart or memory card through a simple and flexible microcontroller interface. Moreover, several couplers can be coupled in parallel, thanks to the chip select input pin (Pin 5). The MC33560 is particularly suited to low power and portable applications because of its power saving features and the minimum of external parts required. Battery life is extended by the wide operating range and the low quiescent current in standby mode. A highly sophisticated protection system guarantees timely and controlled shutdown upon error conditions. • 100% Compatible with ISO 7816−3 Standard • Wide Battery Supply Voltage Range: 1.8 V < VBAT < 6.6 V • Programmable VCC Supply for 3.0 V or 5.0 V Card Operation • Power Management for Very Low Quiescent Current in Standby Mode (30 mA max) • Microprocessor Wakeup Signal Generated Upon Card Insertion • Self Contained DC−DC Converter to Generate VCC using a Minimum of Passive Components • Controlled Powerup/Down Sequence for High Signal Integrity on the Card I/O and Signal Lines • Programmable Card Clock Generator • Chip Select Capability for Parallel Coupler Operation • High ESD Protection on Card Pins (4.0 kV, Human Body Model) • Fault Monitoring VBATlow, VCClow and ICClim • All Card Outputs Current Limited and Short Circuit Protected • Tested Operating Temperature Range: −25°C to +85°C • Pb−Free Packages are Available http://onsemi.com MARKING DIAGRAMS 24 MC33560DW AWLYYWWG SO−24W DW SUFFIX CASE 751E 1 24 MC335 60G ALYW TSSOP−24 DTB SUFFIX CASE 948K 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device PIN CONNECTIONS PGND 1 24 ILIM PWRON 2 23 VBAT INT 3 22 L1 RDYMOD 4 21 C4 CS 5 20 C8 RESET 6 19 CRDC8 I/O 7 18 CRDCON INVOUT 8 17 CRDDET ASYCLKIN 9 16 CRDC4 SYNCLK 10 15 CRDCLK CRDIO 11 14 CRDRST CRDGND 12 13 CRDVCC (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 5 1 Publication Order Number: MC33560/D MC33560 VBAT L1 ILIM PGND DC−DC CONVERTER PWRON INT RDYMOD CS POWER MANAGER AND PROGRAMMING SYNCLK ASYCLKIN INVOUT CLOCK GENERATOR IO RESET C4 C8 CARD DETECTOR DELAY CRDDET CRDCON VBAT CRDVCC CRDIO CRDRST CRDC4 CRDC8 CRDCLK CRDGND LEVEL TRANSLATOR Figure 1. Simplified Functional Block Diagram MAXIMUM RATINGS (Note 1) Value Unit VBAT Battery Supply Voltage Rating 7.0 V IBAT Battery Supply Current ±200 mA VCC Power Supply Voltage 6.0 V ICC Power Supply Current ±150 mA VIN IIN Digital Input Pins 2, 4, 5, 6, 7, 9, 10, 17, 18, 20, 21 −0.5 to VBAT +0.5 but < 7.0 ±5.0 V mA VOUT IOUT Digital Output Pins 3, 4, 8 −0.5 to VBAT +0.5 but < 7.0 ±10 V mA VCard ICard Card Interface Pins 11, 13, 14, 15, 16, 19 −0.5 to VCC + 0.5 ±25 V mA IL Coil Driver Pin 22, ILIM (Pin 24) Power Ground (Pin 1) ±200 ±100 mA VESD ESD Capability: (Note 2) Standard Pins 2, 3, 4, 5, 6, 7, 8, 9, 10, 17, 18, 20, 21, 22, 23, 24 Card Interface Pins 11, 13, 14, 15, 16, 19 2.0 4.0 kV kV PDs RqJAs SO−24 Package: Power Dissipation @ TA = 85°C Thermal Resistance Junction−to−Air 285 140 mW °C/W PDt RqJAt TSSOP−24 Package: Power Dissipation @ TA = 85°C Thermal Resistance Junction−to−Air 220 180 mW °C/W TA Operating Ambient Temperature Range −40 to +85 °C TJ Operating Junction Temperature Range −40 to +125 °C TJmax Maximum Junction Temperature (Note 3) 150 °C Tstg Storage Temperature Range −65 to +150 °C Symbol Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum electrical ratings are those values beyond which damage to the device may occur. TA = 25°C. 2. Human body model, R = 1500 W, C = 100 pF. 3. Maximum thermal rating beyond which damage to the device may occur. http://onsemi.com 2 MC33560 ELECTRICAL CHARACTERISTICS These specifications are written in the same style as common for standard integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4.0 V, VCC = 5.0 V nom, PWRON = VBAT , Operating Mode, −ICC = 10 mA, −25°C ≤ TA ≤ 85°C, L1 = 47 mH, RLIM = 0 W, CRDVCC capacitor = 10 mF, unless otherwise noted.) Characteristic Test Conditions Symbol Min Typ Max Unit Supply Voltage Range Normal operating range extended operating range (Note 4) VBAT 2.2 1.8 − − 6.0 6.6 V MC33560 Standby Quiescent Current PWRON = GND, CRDCON = GND, ASYCLKIN = GND, VBAT = 6.0 V, All Other Logic Inputs and Outputs Open IoBAT − − 30 mA DC Operating Current −ICC = 10 mA; VCC = 5.0 V, VBAT = 6.0 V IBATop − − 12.5 mA − − − 1.6 1.4 0.2 − − − 4.75 5.0 5.25 4.60 5.0 5.40 VT5H VT5L VHYS5 4.2 120 4.5 180 BATTERY POWER SUPPLY SECTION VBAT Undervoltage Detection: Upper Threshold Lower Threshold Hysteresis − V VCC = 5.0 V NOMINAL POWER SUPPLY SECTION Output Voltage Card VCC Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis 2.2 V v VBAT v 6.0 V 1.0 mA v −ICC v 25 mA 3.0 V v VBAT v 6.0 V 1.0 mA v −ICC v 60 mA (RDYMOD Output) (See Table 4) VCC V VCC − 0.14 V mV Peak Output Current VCC = 4.0 V, Internally Limited (RDYMOD = L) −ICClim 80 − − mA Current limit time−out VCC = 4.0 V td − 160 − ms VCC = 2.0 V; 0°C to +85°C −40°C to 0°C −ICCst 80 50 − − − − mA IL = 50 mA, Pin 22 Vsat22 − 100 160 mV Rectifier on Saturation Voltage IL = 50 mA, Pin 22 to Pin 13 VFsat22 − 400 520 mV Converter Switching Frequency TA = 25°C fsw − 120 − kHz PWRON = GND, VCC = 2.0 V ISD 80 − − mA 2.75 3.0 3.25 2.60 3.0 3.40 VT3H VT3L VHYS3 2.4 80 2.7 110 −ICCst ISD 50 50 − − Startup Current Low Side Switch Saturation Voltage Shutdown Current (Card access deactivated) VCC = 3.0 V NOMINAL POWER SUPPLY SECTION (VBAT = 2.5 V, −ICC = 5.0 mA) Output Voltage Card VCC Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Startup Current Shutdown Current (Card access deactivated) 2.2 V v VBAT v 6.0 V 1.0 mA v −ICC v 10 mA 2.5 V v VBAT v 6.0 V 1.0 mA v −ICC v 50 mA (RDYMOD Output) (See Table 4) VCC = 2.0 V PWRON = GND, VCC = 2.0 V 4. 5. 6. 7. VCC V VCC − 0.1 V mV − − mA See Figures 2 and 3. The transistors T1 on lines IO, C4 and C8 (see Figure 24) have a max Rdson of 250 W. Pin loading = 30 pF, except INVOUT = 15 pF. As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. 8. In either direction. http://onsemi.com 3 MC33560 ELECTRICAL CHARACTERISTICS (continued) These specifications are written in the same style as common for standard integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4.0 V, VCC = 5.0 V nom, PWRON = VBAT , Operating Mode, −ICC = 10 mA, −25°C ≤ TA ≤ 85°C, L1 = 47 mH, RLIM = 0 W, CRDVCC capacitor = 10 mF, unless otherwise noted.) Characteristic Test Conditions Symbol Min Typ Max Unit APPLICATION INTERFACE DC SECTION (VBAT = 5.0 V) Input High Threshold Voltage (increasing) Pins 2, 4, 5, 6, 10, 17 VIH 0.55*VBAT − 0.65*VBAT V Input Low Threshold Voltage (decreasing) Pins 2, 5, 6, 10 Pin 17 Pin 4 VIL 0.3*VBAT 0.2*VBAT 0.3*VBAT − − − 0.45*VBAT 0.40*VBAT 0.5*VBAT V Pins 2, 4, 5, 6, 10, 17 VHYST 0.06*VBAT − 0.3*VBAT V Pin 9 Pin 18 VTH 0.5*VBAT 0.4*VBAT − − 0.6*VBAT 0.6*VBAT V VIN = VBAT − 1.0 V, Pins 2, 6, 7, 10 Rdown 120 240 500 kW VIN = 0.5 V, Pin 3, 4, 5 Rup 120 240 500 kW Output High Voltage IOH = −2.5 mA, Pin 3, Pin 4 for CS = H IOH = −50 mA, pins 7, 20,21 IOH = −0.2 mA, Pin 8 Pin 4 ( in Output Mode) VOH VBAT − 1 − − V Output Low Voltage IOL = 1.0 mA, Pins 7, 20, 21 IOL = 0.2 mA, Pins 3, 4, 8 VOL − − 0.4 V VIN = 2.5 V, CS = H, Pins 9, 17, 18, 20, 21 ±Ileak − − 2.0 mA Switching Hysteresis Threshold Voltage Pulldown resistance Pullup resistance Input Leakage Current CARD INTERFACE DC SECTION (VBAT = 5.0 V) Output High Voltage IOH = −20 mA, Pins 11, 16, 19 IOL = 0.2 mA, Pins 14, 15 VOH VCC − 0.9 − − V Output Low Voltage IOL = 1.0 mA, Pins 11, 16, 19 IOL = 0.2 mA, Pins 14, 15 VOL − − 0.4 V I/O Pullup Resistance, Operating Mode, CS =L , PWRON = H VOL = 0.5 V, Pins 11, 16, 19 − − 18 − kW PWRON = GND, lin = 10 mA, Pins 11, 14, 15, 16, 19 Vsecurity − − 2.0 V Card pins security voltage (Card access deactivated) DIGITAL DYNAMIC SECTION (VBAT = 5.0 V, Normal Operating Mode) (Note 6) Input Clock Frequency Pin 9, Duty Cycle = 50% fasyclk − − 20 MHz Card Clock Frequency Pin 15 fcrdclk − − 20 MHz Card Clock Duty Cycle (Note 7) Pin 15, 50% to 50% VCC, fio = 16 MHz rclk 45 − 55 % Card Clock Rise and Fall Time Pin 15, 10% ↔ 90% VCC trclk, tfclk − − 10 ns I/O Data Transfer Frequency Pin [7, 11], [21, 16], [20, 19] (Note 8) fio − 1.0 − MHz I/O Duty Cycle Pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC rio 45 − 55 % I/O Rise and Fall Time Pin [7, 11], [21, 16], [20, 19] (Note 8) 10% ↔ 90% VCC trio, tfio − − 150 ns I/O Transfer Time Pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC, L → H, H → L ttr − − 100 ns Pins 11, 14, 15, 16, 19 VCC Powerup / Powerdown tdseq − 0.2 1.0 ms Card Signal Sequence Interval 4. 5. 6. 7. See Figures 2 and 3. The transistors T1 on lines IO, C4 and C8 (see Figure 24) have a max Rdson of 250 W. Pin loading = 30 pF, except INVOUT = 15 pF. As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. 8. In either direction. http://onsemi.com 4 MC33560 ELECTRICAL CHARACTERISTICS (continued) These specifications are written in the same style as common for standard integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4.0 V, VCC = 5.0 V nom, PWRON = VBAT , Operating Mode, −ICC = 10 mA, −25°C ≤ TA ≤ 85°C, L1 = 47 mH, RLIM = 0 W, CRDVCC capacitor = 10 mF, unless otherwise noted.) Characteristic Test Conditions Symbol Min Typ Max Unit tfltin tfltout 50 50 − − 150 150 ms ms RES, VCC Powerup / Powerdown tdres − 20 − ms Pin 4 tdrdy − − 2.0 ms CS = L, Pin 2 twon 2.0 − − ms 1.0 − − 1.0 − − 2.0 − − DIGITAL DYNAMIC SECTION (VBAT = 5.0 V, Normal Operating Mode) (Note 6) Card Detection Filter Time: Card Insertion Card Extraction Internal Reset Delay Ready Delay Time PWRON low Pulse Width DIGITAL DYNAMIC SECTION (VBAT = 5.0 V, programming mode) (Note 6) Data Setup Time RDYMOD, PWRON, RESET, IO Data Hold Time RDYMOD, PWRON, RESET, IO CS low Pulse Width Pins 2, 4, 6, 7 ms tsmod ms thmod Pins 2, 4, 6, 7 Pin 5 twcs 4. 5. 6. 7. ms See Figures 2 and 3. The transistors T1 on lines IO, C4 and C8 (see Figure 24) have a max Rdson of 250 W. Pin loading = 30 pF, except INVOUT = 15 pF. As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. 8. In either direction. http://onsemi.com 5 MC33560 200 200 IBATop MAX 180 160 160 140 140 120 ICC MAX I (mA) I (mA) 180 100 80 120 ICC MAX 100 80 Mode Sync SYNCLK = 4 MHz L1 = 47 mH Rlim = 0 60 40 20 0 1.5 2.5 3.5 4.5 5.5 40 20 0 1.5 7.5 6.5 Mode Sync SYNCLK = 4 MHz L1 = 47 mH Rlim = 0 60 2.5 3.5 4.5 5.5 VBAT (V) Figure 2. Maximum Battery and Card Supply Current vs. VBAT (VCC = 5.0 V) Figure 3. Maximum Battery and Card Supply Current vs. VBAT (VCC = 3.0 V) 14 VBAT = 2.5 V L1 = 47 mH Rlim = 0 ICC = 0 10 Async VBAT = 2.5 V L1 = 47 mH Rlim = 0 ICC = 0 12 10 IBATop (mA) 12 Sync 8 6 Async/2 4 8 Async 6 Sync 4 Async/4 Async/2 2 0 2 0 2.0 4.0 6.0 8.0 10 12 14 0 16 Async/4 0 2.0 4.0 6.0 8.0 10 12 14 16 Frequency (MHz) Frequency (MHz) Figure 4. Battery Current vs. Input Clock Frequency (ICC = 0, VBAT = 4.0 V) Figure 5. Battery Current vs. Input Clock Frequency (ICC = 0, VBAT = 2.5 V) 250 250 Mode Sync SYNCLK = 4 MHz VBAT = 4 V 150 L1=47 mH 100 50 150 L1=47 mH 100 50 L1=22 mH 0 Mode Sync SYNCLK = 4 MHz VBAT = 2.5 V L1=100 mH 200 IBATop Max (mA) L1=100 mH 200 IBATop Max (mA) 7.5 6.5 VBAT (V) 14 IBATop (mA) IBATop MAX 0 L1=22 mH 1 2 3 4 0 5 0 Rlim (ohms) 1 2 3 4 Rlim (ohms) Figure 6. Maximum Battery Current vs. RLIM (VCC = 5.0 V, VBAT = 4.0 V) Figure 7. Maximum Battery Current vs. RLIM (VCC = 3.0 V, VBAT = 2.5 V) http://onsemi.com 6 5 MC33560 120 120 80 L1 = 47 mH 60 40 1 0 3 2 4 0 5 L1 = 22 mH 1 0 3 2 4 Rlim (ohms) Rlim (ohms) Figure 8. Maximum Card Supply Current vs. RLIM (VCC = 5.0 V, VBAT = 4.0 V) Figure 9. Maximum Card Supply Current vs. RLIM (VCC = 3.0 V, VBAT = 2.5 V) 5 Rectifier On Saturation Voltage (V) 0.35 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 −25 −5 15 35 55 75 0.30 0.25 0.20 0.15 0.10 0.05 0.00 −25 95 −5 15 35 55 75 TA, Ambient Temperature (°C) TA, Ambient Temperature (°C) Figure 10. Low Side Switch Saturation Voltage (IL = 50 mA) vs. Temperature Figure 11. Rectifier On Saturation Voltage (IL = 50 mA) vs. Temperature 115 115 110 110 105 105 tfltout, Filter Time (μs) Low Side Switch Saturation Voltage (V) L1 = 47 mH 60 20 L1 = 22 mH 0.08 tfltin, Filter Time (μs) L1 = 100 mH 80 40 20 0 Mode Sync SYNCLK = 4 MHz VBAT = 2.5 V 100 ICC Max (mA) ICC Max (mA) Mode Sync SYNCLK=4MHz VBAT=4V L1 = 100 mH 100 100 95 90 85 100 95 90 85 80 80 75 75 70 −25 −5 15 35 55 75 70 −25 95 95 TA, Ambient Temperature (°C) −5 15 35 55 75 95 TA, Ambient Temperature (°C) Figure 13. Card Detection (Extraction) Filter Time vs. Temperature Figure 12. Card Detection (Insertion) Filter Time vs. Temperature http://onsemi.com 7 PULLDOWN RESISTANCE (kW) MC33560 350 330 310 290 270 250 230 210 190 170 150 −25 −5 15 35 55 75 95 TA, Ambient Temperature (°C) Figure 14. Pulldown Resistance vs. Temperature Figure 16. Transition from 3.0 V to 5.0 V Card Supply Figure 15. Transition from 5.0 V to 3.0 V Card Supply Figure 17. Overcurrent Shutoff (td = 160 ms) Figure 18. Undervoltage Shutoff (VT5L = 4.6 V) http://onsemi.com 8 MC33560 VBAT VBAT VBATOK VBAT 240 k CS CS CRDCON PWRON PWRON CRDDET 240 k VBAT DELAY 50 mS t 240 k INT FAULT LOGIC S Q VBAT CARD R CS CRDVCC 240 k RDYMOD POWER MANAGEMENT LOGIC AND PROGRAMMING VBATOK CARD PINS SEQUENCER SEQ1 SEQ2 SEQ3 FAULT VBAT DC/DC CONVERTER SEQ4 SEQ1 240 k BIDIRECTIONAL I/O CARDENABLE VBATOK SEQ3 CRDIO CRDVCC BIDIRECTIONAL I/O CARDENABLE VBATOK SEQ3 CRDC4 CRDVCC VBAT C8 CRDVCC CRDVCC VBAT C4 ILIM L1 CRDVCC ON/OFF 3V/5V VBAT IO PROGRAM CARDENABLE BIDIRECTIONAL I/O CARDENABLE VBATOK CRDC8 VBAT CRDVCC DATA LATCH RESET 240 k CARDENABLE LEVEL SHIFT SEQ4 CRDRST VBAT SYNCLK CLOCK GENERATOR AND PROGRAMMING 240 k ASYCLKIN CRDVCC LEVEL SHIFT SEQ2 PROGRAM INVOUT Figure 19. Functional Block Diagram http://onsemi.com 9 CRDCLK MC33560 Table 1. PIN FUNCTION DESCRIPTION Pin Symbol Type Name/Function CONTROLLER INTERFACE 2 PWRON INPUT Pulldown This pin is used to start operation of the internal DC−DC converter. In programming mode, this pin is used to set the “Output Voltage” switch. (See Table 2). 3 INT OUTPUT Pullup This open collector pin indicates a change in the card presence circuit status. When a card is inserted or extracted, the pin goes to logic level “0”. The signal is reset to logic level “1” upon the rising edge of CS or upon the rising edge of PWRON. In the case of a multislot application, two or more INT outputs are connected together and the microcontroller has to poll all the MC33560s to identify which slot was detected. 4 RDYMOD I/O and Pullup This bidirectional pin has tri−state output and Schmitt trigger input. * When RDYMOD is forced to 0, the MC33560 can be set to programming mode by a negative transition on CS. * When RDYMOD is connected to a high impedance, the MC33560 is in normal operating mode, and RDYMOD is in output mode (See Tables 2 and 4): − With CS = L and PWRON=H, RDYMOD indicates the status of the DC−DC converter. − With CS = L and PWRON=L, RDYMOD indicates the status of the card detector. 5 CS INPUT Pullup This is the MC33560 chip select signal. Pins 2, 6, 7, 10, 20, 21 are disabled when CS = H. When RDYMOD = L, the MC33560 enters programming mode upon the falling edge of CS. (Figure 20) 6 RESET INPUT Pulldown The signal present at this input pin is translated to Pin 14 (the card reset signal) when CS = L. The signal on this pin is latched when CS = H. This pin is also used in programming mode. (See Table 2) 7 I/O I/O This pin connects to the Serial I/O port of a microcontroller. A bi−directional level translator adapts the serial I/O signal between the smartcard and the microcontroller. The level translator is enabled when CS = L. The signal on thispin is latched when CS=H. This pin is also used in programming mode. (See Table 2) 8 INVOUT CLK OUTPUT The ASYCLKIN (Pin 9) signal is buffered and inverted to generate the output signal INVOUT. This output is used for multislot applications, where the ASYCLKIN inputs and INVOUT outputs are daisy−chained. (See the multislot application example in Figure 31) 9 ASYCLKIN CLK INPUT high impedance This pin can be connected to the microcontroller master clock or any clock signal for asynchronous cards. The signal is fed to the internal clock selector circuit, and is translated to CRDCLK at the same frequency, or divided by 2 or 4, depending on programming. (See Table 3) 10 SYNCLK CLK INPUT Pulldown This function is used for communication with synchronous cards, and the pin is generally connected to the controller serial interface clock signal. The signal is fed to the internal clock selector circuit, and is translated to CRDCLK upon appropriate programming of the MC33560 (See Table 3). When selected at programming, the signal on this pin is latched when CS = H. 20 C8 I/O General purpose input/output. It has the same behavior as I/O, except for programming. It can be connected to a bidirectional port of the microcontroller. The level translator is enabled when CS = L, and the signal is latched whenCS = H. (Compare with Pin 19) 21 C4 I/O General purpose input/output. It has the same behavior as I/O, except for programming. It can be connected to a bidirectional port of the microcontroller. The level translator is enabled when CS = L, and the signal is latched when CS = H. (Compare with Pin 16) CARD INTERFACE 11 CRDIO I/O This pin connects to the serial I/O pin of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the microcontroller. (Compare with Pin 7) 14 CRDRST OUTPUT This pin connects to the RESET pin of the card connector. A level translator adapts the RESET signal driven by the microcontroller. (Compare with Pin 6) 15 CRDCLK OUTPUT This pin connects to the CLK pin of the card connector. The CRDCLK signal is the output of the clock selector circuit.The clock selection is programmed using Pins 2, 6 and 7 with RDYMOD forced to “0”. 16 CRDC4 I/O General purpose input/output. It has the same behavior as CRDIO. It can be connected to the C4 pin of the card connector. 17 CRDDET INPUT high impedance This pin connects to the card detection switch of the card connector. Card detection phase is determined with Pin 18. This pin needs an external pullup or pulldown resistor to operate properly. 18 CRDCON INPUT high impedance This pin connects to PGND or VBAT, or possibly to an output port of the microcontroller. With this pin set to a logic “0”, the presence of a card is signalled with a logic “1” on Pin 17. With this pin set to a logic “1”, the presence of a card is signalled with a logic “0” on Pin 17. http://onsemi.com 10 MC33560 Table 1. PIN FUNCTION DESCRIPTION Pin Symbol Type Name/Function CARD INTERFACE 19 CRDC8 I/O General purpose input/output. It has the same behavior as CRDIO. It can be connected to the C8 pin of the card connector. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CURRENT LIMIT AND THERMAL PROTECTION 1 PGND POWER This pin is the return path for the current flowing into Pin 22 (L1). It must be connected to CRDGND using appropriate grounding techniques. 12 CRDGND POWER This pin is the signal ground. It must be connected to the ground pin of the card connector. It is the reference level for all analog and digital signals. 13 CRDVCC POWER This pin connects to the VCC pin of the card connector. It is the reference level for a logic “1” of Pins 11, 14, 15, 16 and 19. 22 L1 POWER This pin connects to an external inductance for the DC−DC converter. Please refer to the description of the DC−DC converter functional block. 23 VBAT POWER This pin is connected to the supply voltage. Logic level “1” of Pins 2 to 10, 17, 18, 20 and 21 is referenced to VBAT. Operation of the MC33560 is inhibited when VBAT is lower than the minimum value. 24 ILIM POWER This pin can be connected to the PGND pin, or to a resistor connected to PGND, or left open, depending on the peak coil current needed to supply the card. PROGRAMMING AND STATUS FUNCTIONS The MC33560 features a programming interface and a status interface. Figure 20 shows how to enter and exit programming mode; Table 2 shows which pins are used to access the various functions. RDYMOD (in) CS PWRON PROGRAM DATA VALUE RESET PROGRAM DATA VALUE IO PROGRAM DATA VALUE ENTER PROGRAMMING MODE LATCH EXIT PROGRAM PROGRAMMING MODE VALUE Figure 20. MC33560 Programming Sequence Table 2. PIN USE FOR PROGRAMMING AND STATUS FUNCTIONS Programs CRDVTO 3 V/5 V Select VCC ON/OFF Select Clock Input Program ASYCLKIN Divide Ratio Poll Card Status Poll CRDVCC Status RDYMOD (In/Out) Force to 0 READ Force to 0 Force to 0 READ READ CS (In) rising edge 0 rising edge rising edge 0 0 0/1 0/1 Programs CRDVCC Programs CRDVCC 0 or Hi−z 1 RESET(In) Programs CLK Input/Divide Ratio NOT USED 0/1 0/1 NOT USED NOT USED I/O(In) Programs CLK Input/Divide Ratio NOT USED 0/1 0/1 NOT USED NOT USED CC PWRON http://onsemi.com 11 MC33560 CARD VCC AND CARD CLOCK PROGRAMMING The CRDVCC and ASYCLK programming options allow the system clock frequency to be matched to the card clock frequency and to select 3.0 V or 5.0 V CRDVCC supply. Table 3 shows the values of PWRON, RESET and I/O for the possible options. The default power reset condition is state 4 (synchronous clock and CRDVCC =5.0 V). All states are latched for each output variable in programming mode at the positive transition of CS (Figure 20). Table 3. CARD VCC AND CARD CLOCK TRUTH TABLE NOTE: STATE# PWRON RESET I/O CRDVCC 0 L 1 L 2 CRDCLK L L 3V SYNCLK L H 3V ASYCLKIN/4 L H H 3V ASYCLKIN/2 3 L H L 3V ASYCLKIN 4 H L L 5V SYNCLK 5 H L H 5V ASYCLKIN/4 6 H H H 5V ASYCLKIN/2 7 H H L 5V ASYCLKIN Card clock integrity is maintained during all frequency commutations (no spikes). State 4 is the default state at power on. DC−DC CONVERTER AND CARD DETECTOR STATUS The MC33560 status can be polled when CS = L. Please consult Table 2 for a description of input and output signals.The significance of the status message is described in Table 4. Table 4. RDYMOD STATUS MESSAGES PWRON (Input) RDYMOD (Output) Message LOW LOW No card LOW HIGH Card present HIGH LOW DC−DC converter overload HIGH HIGH DC−DC converter OK DETAILED OPERATING DESCRIPTION INTRODUCTION generator. The power management unit enables the DC−DC converter for card power supply, supervises the powerup/down sequence of the card’s I/O and signal lines, and keeps the power consumption very low in standby mode. All card interface pins have adequate ESD protection, and fault monitoring (VBATlow, VCClow, ICClim) guarantees hazard free card reader operation. Several MC33560s can be operated in parallel, using the same control and data bus, through the use of the chip select signal CS. The MC33560 Smartcard interface IC has been designed to provide all necessary functions for safe data transfers between a microcontroller and a smartcard or memory card. A card detector scans for the presence of a card and generates a debounced wake−up signal to the microcontroller. Communication and control signal levels are translated between the digital interface and the card interface by the voltage level translator, and the card clock is matched to the system clock frequency by the programmable card clock http://onsemi.com 12 MC33560 CS: FALLING EDGE STAND BY MODE CS = H PWRON = L ERROR CONDITION ACTIVE MODE CS = L PWRON = L CS: RISING EDGE RDYMOD: 0 AND CS: FALLING EDGE CS: 1 AND RDYMOD: RISING EDGE ISO STOP SEQUENCE CS: 0 AND PWRON: RISING EDGE PWRON: FALLING EDGE OR ERROR CONDITION ISO START SEQUENCE PROGRAMMING MODE CS = L RDYMOD = L TRANSACTION MODE CS = L PWRON = H IDLE MODE CS = H PWRON = H CS: 1 AND RDYMOD: RISING EDGE RDYMOD: 0 AND CS: FALLING EDGE PROGRAMMING MODE CS = L RDYMOD = L Figure 21. MC33560 Operating Modes OPERATING MODES TRANSACTION MODE The MC33560 has five operating modes: • Standby • Programming • Active • Transaction • Idle The transitions between these different states are shown in Figure 21 above. In transaction mode, the MC33560 maintains power and the selected clock signal applied to the card, and the levels of the I/O, RESET, C4 and C8 signals between the microcontroller and the card are translated depending on the supply voltages VBAT and VCC. The DC−DC converter status can be monitored on the RDYMOD pin. IDLE MODE Idle mode is used when maintaining a card powered up without communicating with it. When an asynchronous clock is used, the selected clock signal is applied to the card. STANDBY MODE Standby mode allows the MC33560 to detect card insertion and monitor the power supply while keeping the power consumption at a minimum. It is obtained with CS = H and PWRON = L. When the MC33560 detects a card, INT is asserted low to wake up the Microcontroller. POWERDOWN OPERATION Powerdown can be initiated by the controlling microprocessor, by stopping the DC−DC converter with PWRON = L while CS = L, or by the MC33560 itself when an error condition has been detected (CRDVCC undervoltage, overcurrent longer than 160 ms typ., overtemperature, “hot” card extraction). The communication session is terminated in a given sequence defined in ISO7816−3. The MC33560 then goes into active mode, in which its status can be polled. Standby mode is reached by deselecting the MC33560 (CS = H). FUNCTIONAL BLOCKS PROGRAMMING MODE The programming mode allows the user to configure the card VCC and the card clock signal for his specific application. The card supply, CRDVCC, can be programmed to 3 V or 5 V, and the card clock signal can be defined to be either synchronous, or asynchronous divided by 1, 2 or 4. Programming mode is obtained with RDYMOD = L followed by a negative transition on CS. The programming options are shown in Table 3. Programmed values are latched on a positive transition of CS with RDYMOD = L. CARD DETECTOR This block monitors the card contact CRDDET (during insertion and extraction), filters the incoming waveform and generates an interrupt signal INT after each change. In order to identify which coupler activated the INT line (multicoupler application) the microcontroller scans both circuits via CS and reads the RDYMOD pin. The programming input CRDCON tells the level detector which type of mechanical contact is implemented (normally open or normally closed). Special care is taken to hold the current consumption very low on this part of the circuit which is continuously powered by the VBAT supply. The CRDDET pin has high impedance input, and an external resistor must be connected to pullup or pulldown, depending on CRDCON. This resistor is chosen according to the maximum leakage current of the card connector and the PCB. ACTIVE MODE In active mode, the MC33560 is selected, the RDYMOD pin becomes an output, and the MC33560 status can be polled. Power is not applied to the card. The microcontroller polls the MC33560 by asserting CS = L and reading the RDYMOD pin. If a card is present, the microcontroller starts the DC−DC converter by asserting PWRON=H. This starts the automatic power on sequence: when CRDVCC reaches the undervoltage level (VT5H or VT3H, depending on programming), the card sequencer validates CRDIO, CRDRST, CRDCLK, CRDC4, CRDC8 pins according to the ISO7816−3 sequence (Figure 26). The MC33560 is now in transaction mode, and the system is ready for data exchange via the three I/O lines and the RESET line. http://onsemi.com 13 MC33560 The card detector has an internal 50 ms debouncing delay. The micro controller has to insert an additional delay (in the ms range) to allow the card contacts to stabilize in the card connector before setting PWRON = H. When the card detector circuit detects a card extraction, it activates the powerdown sequence and stops the converter, regardless of the PWRON signal. The 50 ms delay of the debouncer is enough to ensure that all card signals have reached a safe value before communication with the card takes place. The output voltage is programmable for 3.0 V or 5.0 V (see Table 3) to guarantee full cross compatibility of the reader for 5.0 V and 3.0 V smartcards. The wide voltage supply range, 1.8 V < VBAT < 6.6 V, accommodates a broad range of coupler applications with different battery configurations (single cell or multiple cells, serial or parallel connections). The CRDVCC is current−limited and short−circuit−proof. To avoid excessive battery loading during a card short−circuit, a current integration function forces the powerdown sequence (Figure 28). To retry the session, the microprocessor works through the power on sequence as defined in the power manager section. CARD STATUS The controlling microprocessor is informed of the MC33560 status by interrupt and by polling. When a card is extracted or inserted, the INT line is asserted low. The interrupt is cleared upon the rising edge of CS or upon the rising edge of PWRON (INT line set to high state). The microprocessor can poll the status at any time by reading the RDYMOD pin with proper PWRON setting (see Tables 2 and 4). Since INT and RDYMOD have a high value pullup resistor (240 kW typical), their rise time can be as long as 10 ms if parasitic capacitance is high and no other pullup circuitry is connected. DC−DC CONVERTER OPERATING PRINCIPLES The DC−DC converter architecture used in the MC33560 allows step−up and step−down voltage conversion to be done. The unique regulation architecture permits an automatic transition from step−up to step−down, and from zero to full load, without affecting the output characteristics. DC−DC Converter Description: The converter architecture is very similar to the boost architecture, with an active rectifier in place of the diode. The switching transistor is connected to ground through a resistor network in order to adjust the maximum peak current (Figure 22). A transistor connected to the converter output (CRDVCC) forces this pin to a low voltage when the converter is not operating. This prevents erratic voltage supply to the smartcard when not in use. The MC33560 has a built in oscillator; the DC−DC converter requires only one inductor and the output filtering capacitor to operate. Stepup Operation: When the card supply voltage is lower than the battery voltage, the converter operates like a boost converter; the active rectifier behavior is similar to that of a diode. Stepdown Operation: When the card supply voltage is higher than the battery voltage, the rectifier control circuit puts the power rectifying transistor in conduction when the L1 voltage reaches VBAT + VFSAT22. The voltage across the rectifying transistor is higher than in step−up operation. The efficiency is lower, and similar to a linear regulator. Fault Detection: The DC−DC converter has several features that help to avoid electrical overstress of the MC33560 and of the smartcard, and help to ensure that data transmission with the smartcard occurs only when its supply voltage is within predetermined limits. These functions are: • Overtemperature Detection, • Current Limitation, and • Card Supply Undervoltage Detection. The level at which current will be limited is defined by the maximum card supply current programmed with the external components L1 and RLIM. The undervoltage detection levels for 3.0 V and 5.0 V card supply are preset internally to the MC33560. POWER MANAGER The task of the power manager is to activate only those circuit functions which are needed for a determined operating mode in order to minimize power consumption (Figure 19). In standby mode (PWRON = L) the power manager keeps only the “card present” detector alive. All card interface pins are forced to ground potential. In the event of a powerup request from the microcontroller (PWRON L to H transition, CS = L) the power manager starts the DC−DC converter. As soon as the CRDVCC supply reaches the operating voltage range, the circuit activates the card signals in the following sequence: CRDVCC, CRDIO, CRDCLK, CRDC4/C8, CRDRST At the end of the transaction (PWRON reset to L, CS = L) or forced card extraction, the CRDVCC supply powers down and the card signal deactivation sequence takes place: CRDRST, CRDC4/C8, CRDCLK, CRDIO, CRDVCC When CS = L, the bi−directional signal lines (I/O, C4 and C8) are put into high impedance state to avoid signal collision with the microcontroller in transmission mode. BATTERY UNDERVOLTAGE DETECTOR The task of this block is to monitor the supply voltage, and to allow operation of the DC−DC converter only with valid voltage (typically 1.5 V). The comparator has been designed to have stability better than 20 mV in the temperature range. DC−DC CONVERTER Upon request from the power manager, the DC−DC converter generates the CRDVCC supply for the smartcard. http://onsemi.com 14 MC33560 VBAT Rectifier Switch CRDVCC L1 Active pull−down switch PWN FEED BACK CLOCK OFF RECTIFIER CONTROL Low Side Switch STOP ON /OFF CRDGND ON /OFF − + ILIMCOMP 120 mV 2W PGND ON /OFF DIGITAL FILTER ON /OFF 0.5 W Internal resistors ILIM RLIM (external) − LOGIC AND COUNTER OVER TEMP DETECTION + VBATOK CONVERTER FAULT + ERROR AMP. 3V/5V UNDER VOLTAGE DETECTOR CRDGND VREF − Figure 22. DC−DC Converter Functional Block estimated to less than 750 ms. The total time aftercard extraction detection until CRDVCC reaches 0.4 V is then estimated to 900 ms (maximum). All smartcard connector contacts will be deactivated before CRDVCC deactivation. This ensures that no electrical damage will be caused to the smartcard under abnormal extraction conditions. 3.0 V/5.0 V Programming: It is possible to set the card supply voltage to 3.0 V or 5.0 V at any time, before DC−DC converter start, or during converter operation. When switching from 3.0 V to 5.0 V, a 160 ms (typical) delay blanks the undervoltage fault detection to allow filter capacitor charging. PWM: The free−running integrated oscillator has two working modes: Variable on−state and fixed frequency (typically 120 KHz) for average to heavy loads. Variable on−state and variable frequency for light loads. The frequency can be as low as a few kHz if no load is connected to CRDVCC. The charging current of the timing capacitor is related to the VBAT supply voltage, to allow better line regulation, and to increase stability. Filtering Capacitor: A high value allows efficient filtering of card current spikes. Low values allow low startup charging current. Care must be taken not to combine low capacitor value with high current limiting, as this can generate high ripple. Usual values range from 4.7 mF to 47 mF, depending on current limiting. Selecting the External Components L1 and RLIM: The choice of inductor L1 and resistor R4 is made by using Figure 8 (5.0 V card) and/or Figure 9 (3.0 V card) on page 8: The overcurrent and undervoltage protection features are complementary, and will shut the circuit off either if the overcurrent is high enough to bring the CRDVCC output below the preset threshold, either after 160 ms (typ.) In addition, the DC−DC converter will be allowed to start only if the battery supply voltage is high enough to allow normal operation (1.8 V). The undervoltage comparator has a hysteresis and a delay of typically 20 ms to ensure stable operation. The current detector is a comparator associated with two resistors: one 2.0 W attached to PGND and usually connected to analog ground, and a 0.5 W attached to ILIM, usually connected to ground through an external resistor to adjust the maximum peak current. The voltage developed across this resistor network is then compared to a 120 mV (typical) reference voltage, and the comparator output performs a cycle−by−cycle peak current limitation by switching off the low side transistor when the voltage exceeds 120 mV. The internal ILIMCOMP signal is monitored to stop the converter if current limitation is continuously detected during 160 ms (typical). This allows normal operation with high filtering capacitance and low peak current, even at converter startup. As a result, a short circuit to ground on the card connector or a continuous overcurrent is reported by RDYMOD 160 ms (typical) after powerup. Unexpected Card Extraction: The MC33560 detects card extraction and runs a powerdown sequence if card power is still on when extraction occurs. An active pulldown switch clamps CRDVCC to GND within 150 ms (max) after extraction is detected. The external capacitors will then be discharged. With typical capacitor values of 10 mF and 47 nF as indicated in the application schematic, the time needed to discharge CRDVCC to a voltage below 0.4 V can be http://onsemi.com 15 MC33560 The INVOUT output is provided to drive other circuits without additional load to the microprocessor quartz oscillator. It can also be used to build a local RC oscillator. This driver has been optimized for low consumption; it has no hysteresis, and input levels are not symmetrical. If the ASYCLKIN pin is connected to a sine wave, the duty cycle will not always be 50% at INVOUT. First, determine the maximum current that the application requires to supply to the card (ICCmax, on the y−axis) Then, select one curve that crosses the selected ICCmax level. The curve is associated with an inductance value (22 mH, 47 mH, or 100 mH). Finally, use the intersection of the curve and the ICCmax level to find the Rlim value on the x−axis. Good starting values are : L1 = 47 mH; Rlim = 0.5 W Note also that, for a high inductance value (100 mH), the filtering capacitor is generally charged before inductance current reaches current limitation, while for alow inductance value, the current limitation is activated after a few converter cycles. Battery Requirements: Having determined the L1 and Rlim values, the maximum current drawn from the battery supply is shown by the curves in Figures 6 and 7. When the application is powered by a single 3.0 V battery, special care has to be taken to extend its lifetime. When lithium batteries approach the end−of−life, their internal resistance increases, while voltage decreases. This phenomenon can prevent the startup of the DC−DC converter if the current limiting is set too high, because of the filtering capacitor charging current. CLOCK GENERATOR OPERATING PRINCIPLES LATCH SYNCLK CARDENABLE ASYCLKIN INVOUT B2 B2 SYNCHRONISATION LOGIC CLOCK GENERATOR The primary purpose of the clock generator module is to match the smartcard operating frequency to the system frequency. The source frequency can be provided to ASYCLKIN by the microcontroller itself or from an external oscillator circuit. In programming mode (RDYMOD=L and CS asserted low) the three input variables PWRON, I/O and RESET are used to configure the two output variables CRDVCC and CRDCLK as described in Table 3. This circuit setup is latched during the positive transition of CS. Furthermore, in asynchronous mode the system clock frequency ASYCLKIN can be divided by a factor of 1, 2 or 4. The circuit controls the frequency commutation to guarantee that the card clock signal remains free from spikes and glitches. In addition, this circuit ensures that CRDCLK signal pulses will not be shorter than the shortest and/or longer than the longest of the clock signals present before and after programming changes. SELECTOR Synchronous Clock: This clock is used mainly for memory cards. It can also be used for asynchronous (microprocessor) cards, allowing the use of two different clock sources. The status of SYNCLK is latched at CRDCLK when CS goes high, so that data (the I/O pin) and clock are always consistent at the card connector, whatever the CS status is. When using the synchronous clock, the clock output becomes active only when the MC33560 is selected with CS. Asynchronous Clock: This clock is used mainly for microprocessor cards. When applied, the clock output remains active even when the MC33560 is not selected with CS, in order to keep the microprocessor running and avoid an unwanted reset. The ASYCLKIN signal is buffered at the INVOUT pin, so that several MC33560 systems can use the same clock with one load only. Depending on programming, the frequency is fed directly, or divided by 2 or by 4 to the CRDCLK pin. If the duty cycle of the applied clock signal is not exactly symmetrical, it is recommended that the clock signal be divided by two or four to guarantee 50% duty cycle. Clock Signal Synchronization and Consistency (Figure 29). The clock divider includes synchronization logic that controls the switch from synchronous clock to asynchronous (and vice−versa), from any division ratio to any other ratio, during CS changes and at powerup. The synchronization logic guarantees that each clock cycle on the CRDCLK pin is finished before changing clock selection (and has always the adequate duration), regardless of the moment the programming is changed. At powerup, when ASYCLKIN is selected, the clock signal at the CRDCLK pin has an entire length, according to the selected divide ratio, whatever the ASYCLKIN signal is versus the internal sequencer timing. CRDVCC SYNCHRO LATCH CRDCLK SEQ3 RESET IO SELECTOR LATCH PROGRAM Figure 23. Clock Generator Functional Block http://onsemi.com 16 MC33560 • Card presence detector for “clean” and fast shutdown • Consistent card signal sequencing at startup and BIDIRECTIONAL LEVEL TRANSLATOR This module (used on I/O/CRDIO, C4/CRDC4, C8/CRDC8, Figure 24) adapts the signal voltage levels of the I/O and control lines between the micro controller (supplied by VBAT) and the smartcard (supplied by CRDVCC) When CS is low, with CRDVCC on, and start sequencing completed, this module is transparent for the data, and acts as if the card was directly connected to the reader microcontroller. The core of the level shifter circuit defined for the bidirectional CRDIO, CRDC4 and CRDC8 lines consists of a NMOS switch which can be driven to the logic low state from either side (microcontroller or card). If both sides work in transmission mode with opposite phase, then signal collision on the line is not avoidable. In this case, the peak current is limited to a safe value for the integrated circuit and the smartcard. During high−to−low transitions, the NMOS transistor impedance (T1 = 250 W maximum) is low enough to charge parasitic capacitance, and have a high enough dv/dt. On low to high transition, the NMOS transistor is not active above a certain voltage, and an acceleration circuit is activated to ensure a high dv/dt. When the chip is disabled (CS = H) with the voltage supply CRDVCC still active, the I/O, C4 and C8 lines keep their last logic state. When the converter is off, a transistor forces the CRDIO, CRDC4 and CRDC8 lines to a low state, thus preventing any unwanted voltage level to be applied to the data lines when the card is not in use. VBAT powerdown, according to ISO7816, even on error conditions • Consistent clock signal, even when division ratio or synchronization clock signal are changed “on the fly” during a card session (Figure 29) • Active pulldown on all card pins, including CRDVCC, when not in normal operating mode. A current limiting function and an overtemperature detector are limiting power dissipation. ESD PROTECTION Due to the nature of smartcards, the card interface pins must absorb high Electro Static Discharge (ESD) energy during card insertion. In addition, the control circuits attached to these pins must safely withstand short circuits and voltage transients during forced card extraction. Therefore, the MC33560 features enhanced ESD protection, current limitation and short circuit protection on all smartcard interface pins, including C4 and C8. PARALLEL OPERATION For applications where two or more MC33560 are used, the digital control and data bus lines are common to all MC33560. Only the chip select signal, CS, requires a separate line for each interface. While deselected, all communication pins except CRDCLK will keep their logical state on the card side, and will go to high impedance mode on the microprocessor side. Figure 31 shows a typical application of a dual card reader. This arrangement was chosen only to illustrate the parallel operation of two card interfaces in the same module. The discrete capacitor components are necessary to provide low impedance on the supply lines VBAT and CRDVCC and to suppress the high frequency noise due to the DC−DC converter. The load resistors are external in order to adapt the sense current of the “card present” switches. CRDVCC 18 K IO (C4) (C8) CRDIO (CRDC4) (CRDC8) T1 CONTROL LOGIC SEQ1 (SEQ3) T2 MINIMUM POWER CONSUMPTION CONSIDERATIONS All analog blocks except the VBAT comparator and the card presence detector are disabled in standby mode (CS = H: DC−DC converter stopped). In order to maintain standby current at a minimum value, all pins with pullup resistance (CS, INT, RDYMOD) have to be kept in the high state or left open, and pins with pulldown resistance (RESET, SYNCLK, PWRON) have to be kept in the low state or left open. ASYCLKIN should not be connected to an active clock signal during standby to avoid dynamic currents. This is valid also for SYNCLK, except that it can be left open. CRDGND CARDENABLE Figure 24. Bidirectional Translator Functional Block SECURITY FEATURES The MC33560 has a number of unique security functions to guarantee that no electrical damage will be caused to the smartcard: • Battery supply minimum voltage threshold • Card supply undervoltage and overcurrent detection with automatic shutdown • Card pin overvoltage clamp to CRDVCC http://onsemi.com 17 MC33560 C8 C4 CRDC8 CRDDET CRDC4 CRDCLK CRDRST L1 CRDVCC VBAT ILIM PGND C10 R4 C6 C7 CRDGND CRDIO PWRON SYNCLK INT ASYCLKIN RDYMOD INVOUT CS IO RESET Figure 25. Example of Single Sided PCB Layout for MC33560 http://onsemi.com 18 MC33560 POWERUP NORMAL OPERATION POWERDOWN VTxH CRDVCC CS RDYMOD (out) twon PWRON IO CLK C4. C8 RESET CRDIO CRDCLK CRDC4, CRDC8 ttr CRDRST SEQ4 to SEQ1 SEQ1 to SEQ4 Figure 26. Card Signal Sequence During VCC Powerup/Down tfltout tfltin CRDDET INT CS RDYMOD (out) CS to INT 15 mS typ. INTERRUPT SERVICING tdrdy POLLING INTERRUPT SERVICING Figure 27. Interrupt Servicing and Polling http://onsemi.com 19 POLLING MC33560 MCU deactivates PWRON after card extraction poll with PWRON = L −> RDYMOD = H: card still present CS = L, PWRON = H CRDVCC undervoltage −> RDYMOD = L overload time smaller than tdres (glitch not to scale) card inserted tfltin tfltout VTxH VTxL CRDVCC CRDDET INT CS RDYMOD PWRON tdres tdrdy tdres poll with PWRON = L −> RDYMOD = H: card present 35 ns typ MCU polls RDYMOD = H card extraction poll with PWRON = H −> RDYMOD = L: DC−DC converter overload overload time greater than tdres −> converter stop and CRDVCC pulldown Figure 28. Card Signal Sequence During VCC Overload and Unexpected Card Extraction http://onsemi.com 20 RDYMOD CS RESET IO SYNCLK ASYCLK CRDCLK RDYMOD CS RESET IO SYNCLK ASYCLK CRDCLK MC33560 Figure 29. “On−the−Fly” Card Clock Selection Examples http://onsemi.com 21 22 VDD DO1 DI 1 DO2 DI 2 DO3 DI 3 VSS RX1 TX1 RX2 TX2 RX3 TX3 MC145407 C1− C1+ VCC C2− C2+ GND U3 C2 mC reset 10 uF C4 + 10 uF Q1: XTAL 4MHz D1: General Purpose diode R1: 47 kOhm C1, C2, C4,C5: 10 uF R2: 1 MOhm C3: 220 nF L1: MURATA LQH3C 47 uH R3: 1 MOhm C6: 200 nF C7: 10 uF C8, C9: 22 pF M1: 7805 regulator R4: Value depending on max. card current Z1: General Purpose 40 V zener diode U4: Card connector + C1 Connector 10 uF DB9 C5 10 uF + D1 http://onsemi.com MC68HC705C9 U1 RESET VDD IRQ 0SC1 C3 VPP OSC2 220 nF NC TCAP PA7 PD7 PA6 NC PA5 TCMP PA4 SS PA3 SCLK PA2 MOSI PA1 MISO PA0 RDI PB0 TDO PB1 PC0 PB2 PC1 PB3 PC2 NC PC3 PB4 PC4 PB5 PC5 PB6 PC6 PB7 PC7 VSS NC R1 47k C8 22 pF R3 1M C9 22 pF Q1 4 MHz 1 − PGND 2 − PWRON 3 − INT 4 − RDYMOD 5 − CS 6 − RESET 7 − IO 8 − INVOUT 9 − ASYCLKIN 10 − SYNCLK 11 − CRDIO 12 − CRDGND U2 MC33560 ILIM − 24 VBAT − 23 L1 − 22 C4 − 21 C8 − 20 CRDC8 − 19 CRDCON − 18 CRDDET − 17 CRDC4 − 16 CRDCLK − 15 CRDRST − 14 CRDVCC − 13 R4* R2 1M C7 C6 10 uF 200 nF L1 47 uH C10 0.1 uF U4 Card Slot M1 7805 GND I/O C4 CLK RST VCC C8 Card Detect Z1 8..40 VDC MC33560 Figure 30. Card Reader/Writer Application VBAT mC reset http://onsemi.com 23 MC68HC705 RESET VDD IRQ 0SC1 VPP OSC2 NC TCAP PA7 PD7 PA6 NC PA5 TCMP PA4 SS SCLK PA3 MOSI PA2 MISO PA1 RDI PA0 TDO PB0 PC0 PB1 PC1 PB2 PC2 PB3 PC3 NC PC4 PB4 PC5 PB5 PC6 PB6 PC7 PB7 NC VSS 1 − PGND 2 − PWRON 3 − INT 4 − RDYMOD 5 − CS 6 − RESET 7 − IO 8 − INVOUT 9 − ASYCLKIN 10 − SYNCLK 11 − CRDIO 12 − CRDGND MC33560 1 − PGND 2 − PWRON 3 − INT 4 − RDYMOD 5 − CS 6 − RESET 7 − IO 8 − INVOUT 9 − ASYCLKIN 10 − SYNCLK 11 − CRDIO 12 − CRDGND MC33560 ILIM − 24 VBAT − 23 L1 − 22 C4 − 21 C8 − 20 CRDC8 − 19 CRDCON − 18 CRDDET − 17 CRDC4 − 16 CRDCLK − 15 CRDRST − 14 CRDVCC − 13 ILIM − 24 VBAT − 23 L1 − 22 C4 − 21 C8 − 20 CRDC8 − 19 CRDCON − 18 CRDDET − 17 CRDC4 − 16 CRDCLK − 15 CRDRST − 14 CRDVCC − 13 VBAT VBAT Figure 31. Multi Slot Card Reader/Writer Application GND I/O C4 CLK RST VCC C8 Card Detect GND I/O C4 CLK RST VCC C8 Card Detect MC33560 MC33560 ORDERING INFORMATION Package Shipping† MC33560DTB TSSOP−24 62 Units / Rail MC33560DTBR2 TSSOP−24 2500 / Tape & Reel MC33560DTBR2G TSSOP−24 (Pb−Free) 2500 / Tape & Reel MC33560DW SO−24 30 Units / Rail MC33560DWR2 SO−24 1000 / Tape & Reel SO−24 (Pb−Free) 1000 / Tape & Reel Device MC33560DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 24 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−24 WB CASE 751E−04 ISSUE F DATE 03 JUL 2012 SCALE 1:1 D 24 E H A B 0.25 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD AND ARE MEASURED BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 13 E1 1 L 12 C DETAIL A 24X b PIN 1 INDICATOR 0.25 TOP VIEW M C A S B S h x 45 _ A e A1 NOTE 5 DIM A A1 b c D E E1 e h L M NOTE 3 C c SEATING PLANE NOTE 3 M DETAIL A END VIEW SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 24X 24X MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 15.25 15.54 10.30 BSC 7.40 7.60 1.27 BSC 0.25 0.75 0.41 0.90 0_ 8_ 1.62 0.52 XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX AWLYYWWG 11.00 1 1 XXXXX A WL YY WW G 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB42344B SOIC−24 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP24 WB CASE 948K ISSUE O DATE 17 FEB 2000 SCALE 2:1 24X K REF 0.10 (0.004) 0.15 (0.006) T U M T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S 2X 24 L/2 13 B −U− L PIN 1 IDENT. 1 0.15 (0.006) T U V S 12 S A −V− −W− C 0.10 (0.004) −T− SEATING PLANE G DETAIL E D H N 0.25 (0.010) DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 5.50 5.70 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 7.60 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.216 0.224 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.299 BSC 0_ 8_ ÇÇÇ ÇÇÇ ÉÉ ÇÇÇ ÉÉ K K1 M N J1 F SECTION N−N DETAIL E DOCUMENT NUMBER: 98ASH70455A DESCRIPTION: TSSOP24 WB J Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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