ON Semiconductor
MC34001, B
MC34002, B
MC34004, B
JFET Input Operational
Amplifiers
These low cost JFET input operational amplifiers combine two
state–of–the–art analog technologies on a single monolithic integrated
circuit. Each internally compensated operational amplifier has well matched
high voltage JFET input devices for low input offset voltage. The BIFET
technology provides wide bandwidths and fast slew rates with low input bias
currents, input offset currents, and supply currents.
The ON Semiconductor BIFET family offers single, dual and quad
operational amplifiers which are pin–compatible with the industry standard
MC1741, MC1458, and the MC3403/LM324 bipolar devices. The MC34001/
34002/34004 series are specified from 0° to +70°C.
• Input Offset Voltage Options of 5.0 mV and 10 mV Maximum
•
•
•
•
•
•
•
•
Low Input Bias Current: 40 pA
Low Input Offset Current: 10 pA
JFET INPUT
OPERATIONAL AMPLIFIERS
8
8
1
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
Wide Gain Bandwidth: 4.0 MHz
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
High Slew Rate: 13 V/µs
Low Supply Current: 1.4 mA per Amplifier
High Input Impedance: 1012 Ω
High Common Mode and Supply Voltage Rejection Ratios: 100 dB
Offset Null
1
Inv. Input
2
Noninv. Input
3
VEE
4
Industry Standard Pinouts
8
+
NC
7
VCC
6
Output
5
Offset Null
MC34001 (Top View)
Output A
1
2
Inputs A
3
VEE
VCC
Output B
8
7
+
6
+
4
Inputs B
5
MC34002 (Top View)
P SUFFIX
PLASTIC PACKAGE
CASE 646
14
1
PIN CONNECTIONS
Output 1
Inputs 1
ORDERING INFORMATION
Op Amp
Function
Device
Operating
Temperature Range
Package
MC34001BP, P
SO–8
TA = 0° to+ 70°C
Plastic DIP
MC34002BD, D
Dual
Quad
MC34002BP, P
MC34004BP, P
Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 2
2
3
MC34001BD, D
Single
1
VCC
Inputs 2
Output 2
14
+
1
4
6
12
11
4
5
13
+
+
-
2
3
+
-
7
Output 4
Inputs 4
VEE
10
9
8
Inputs 3
Output 3
SO–8
TA = 0° to +70°C
TA = 0° to +70°C
Plastic DIP
MC34004 (Top View)
Plastic DIP
1
Publication Order Number:
MC34001/D
MC34001, B MC34002, B MC34004, B
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC, VEE
±18
V
Differential Input Voltage (Note 1)
VID
±30
V
Input Voltage Range
VIDR
±16
V
Open Short Circuit Duration
tSC
Continuous
Operating Ambient Temperature Range
TA
0 to +70
°C
Supply Voltage
Operating Junction Temperature
TJ
150
°C
Storage Temperature Range
Tstg
–65 to +150
°C
NOTES: 1. Unless otherwise specified, the absolute maximum negative input voltage is equal to the
negative power supply.
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Symbol
Input Offset Voltage (RS ≤ 10 k)
MC3400XB
MC3400X
Min
Typ
Max
—
—
3.0
5.0
5.0
10
—
10
—
—
—
25
25
100
100
—
—
50
50
200
200
VIO
∆VIO/∆T
Average Temperature Coefficient of Input Offset Voltage
RS ≤ 10 k, TA = Tlow to Thigh (Note 2)
Unit
mV
µV/°C
Input Offset Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIO
Input Bias Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIB
Input Resistance
ri
—
1012
—
Ω
Common Mode Input Voltage Range
VICR
±11
—
+15
–12
—
—
V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k)
MC3400XB
MC3400X
AVOL
50
25
150
100
—
—
±12
±10
±14
±13
—
—
80
70
100
100
—
—
80
70
100
100
—
—
—
—
1.4
1.4
2.5
2.7
Output Voltage Swing
(RL ≥ 10 k)
(RL ≥ 2.0 k)
VO
Common Mode Rejection Ratio (RS ≤ 10 k)
MC3400XB
MC3400X
CMRR
Supply Voltage Rejection Ratio (RS ≤ 10 k) (Note 4)
MC3400XB
MC3400X
PSRR
pA
pA
V/mV
V
dB
dB
Supply Current (Each Amplifier)
MC3400XB
MC3400X
ID
Slew Rate (AV = 1.0)
SR
—
13
—
V/µs
GBW
—
4.0
—
MHz
Equivalent Input Noise Voltage
(RS = 100 Ω, f = 1000 Hz)
en
—
25
—
nV/ √ Hz
Equivalent Input Noise Current (f = 1000 Hz)
in
—
0.01
—
pA/ √ Hz
Gain–Bandwidth Product
mA
NOTES: 2. Tlow = 0°C for MC34001/34001B
Thigh = +70°C for MC34001/34001B
0°C for MC34002
+70°C for MC34002
0°C for MC34004/34004B
+70°C for MC34004/34004B
3. The input bias currents approximately double for every 10°C rise in junction temperature, TJ. Due to limited test time, the input bias currents are
correlated to junction temperature. Use of a heatsink is recommended if input bias current is to be kept to a minimum.
4. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
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MC34001, B MC34002, B MC34004, B
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh [Note 2].)
Characteristics
Symbol
Input Offset Voltage (RS ≤ 10 k)
MC3400XB
MC3400X
VIO
Input Offset Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIO
Input Bias Current (VCM = 0) (Note 3)
MC3400XB
MC3400X
IIB
Common Mode Input Voltage Range
VICR
Large Signal (VO = ±10 V, RL = 2.0 k)
MC3400XB
MC3400X
AVOL
Output Voltage Swing
(R ≥ 10 k)
(R ≥ 2.0 k)
VO
Common Mode Rejection Ratio (RS ≤ 10 k)
MC3400XB
MC3400X
CMRR
Supply Voltage Rejection Ratio (RS ≤ 10 k) (Note 4)
MC3400XB
MC3400X
PSRR
Supply Current (Each Amplifier)
MC3400XB
MC3400X
Min
Typ
Max
—
—
—
—
7.0
13
—
—
—
—
4.0
4.0
—
—
—
—
8.0
8.0
±11
—
—
25
15
—
—
—
—
±12
±10
—
—
—
—
80
70
—
—
—
—
80
70
—
—
—
—
—
—
—
—
2.8
3.0
Unit
mV
nA
nA
V
V/mV
V
dB
dB
ID
mA
NOTES: 2. Tlow = 0°C for MC34001/34001B
Thigh = +70°C for MC34001/34001B
0°C for MC34002
+70°C for MC34002
0°C for MC34004/34004B
+70°C for MC34004/34004B
3. The input bias currents approximately double for every 10°C rise in junction temperature, TJ. Due to limited test time, the input bias currents are
correlated to junction temperature. Use of a heatsink is recommended if input bias current is to be kept to a minimum.
4. Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
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3
MC34001, B MC34002, B MC34004, B
Figure 1. Input Bias Current
versus Temperature
Figure 2. Output Voltage Swing
versus Frequency
10
VO, OUTPUT VOLTAGE SWING (Vpp )
I IB , INPUT BIAS CURRENT (nA)
100
VCC/VEE = ±15 V
1.0
0.1
0.01
-75
-50
-25
0
25 50
75 100
TA, AMBIENT TEMPERATURE (°C)
35
30
VCC/VEE = ±15 V
25
20
±10 V
15
±5.0 V
10
5.0
0
100
125
1.0 k
Figure 3. Output Voltage Swing
versus Load Resistance
VO ,OUTPUT VOLTAGE SWING (V pp)
VO, OUTPUT VOLTAGE SWING (Vpp )
40
VCC/VEE = ±15 V
TA = 25°C
20
10
5.0
0
0.1
0.2
0.4
0.7
1.0
4.0
2.0
7.0
10
0
5.0
10
15
20
VCC/VEE , SUPPLY VOLTAGE (V)
Figure 5. Output Voltage Swing
versus Temperature
Figure 6. Supply Current per Amplifier
versus Temperature
I,
D SUPPLY DRAIN CURRENT (mA)
VO, OUTPUT VOLTAGE SWING (Vpp )
RL = 2.0 k
TA = 25°C
20
0
10
VCC/VEE = ±15 V
RL = 10 k
25
RL = 2.0 k
20
15
10
5.0
-50
10 M
RL, LOAD RESISTANCE (kΩ)
30
0
1.0 M
30
2.0
35
10 k
100 k
f, FREQUENCY (Hz)
Figure 4. Output Voltage Swing
versus Supply Voltage
40
30
RL = 2.0 k
TA = 25°C
-25
0
25
50
75
100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
125
VCC/VEE = ±15 V
TA, AMBIENT TEMPERATURE (°C)
-50
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
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4
100
125
MC34001, B MC34002, B MC34004, B
Figure 7. Large–Signal Voltage Gain and
Phase Shift versus Frequency
Figure 8. Large–Signal Voltage Gain
versus Temperature
106
105
104
102
45°
90°
Phase Shift
101
1
1.0
0°
Gain
103
10
100
1.0 k
A,
VOL VOLTAGE GAIN (V/mV)
VCC/VEE = ±15 V
RL = 2.0 k
TA = 25°C
PHASE SHIFT (DEGREES)
A VOL , OPEN-LOOP GAIN
1000
VCC/VEE = ±15 V
VO = ±10 V
RL = 2.0 k
100
10
135°
10 k
100 k
180°
1.0 M 1.0 M 10 M
1.0
-50
f, FREQUENCY (Hz)
en , EQUIVALENT INPUT NOISE VOLTAGE ( nV/ √ Hz )
Figure 9. Normalized Slew Rate
versus Temperature
1.10
1.05
1.00
0.95
0.90
0.85
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
0
50
100
125
30
20
10
0
0.01
0.05 0.1
0.5 1.0
VCC/VEE = ±15 Vdc
AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
0.005
0.5
1.0
5.0
f, FREQUENCY (kHz)
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5
5.0 10
f, FREQUENCY (kHz)
0.01
0.001
0.1
75
40
0.5
0.05
50
VCC/VEE = ±15 V
AV = 10
RS = 100 Ω
TA = 25°C
60
1.0
0.1
25
Figure 10. Equivalent Input Noise Voltage
versus Frequency
Figure 11. Total Harmonic Distortion
versus Frequency
THD, TOTAL HARMONIC DISTORTION (%)
NORMALIZED SLEW RATE
1.15
-50
-25
TA, AMBIENT TEMPERATURE (°C)
10
50
100
50 100
MC34001, B MC34002, B MC34004, B
Representative Circuit Schematic
(Each Amplifier)
Bias Circuitry
Common to All
Amplifiers
Output
VCC
Q4
Q3
Q2
Q5
Q1
Q6
Inputs
+
J1
J2
2.0 k
Q17
Q20
Q15
Q19
10 pF
Q14
Q13
Q23
24
Q21
Q12
J3
Q22
Q24
Q16
Q10
Q9
Q11
Q8
Q7
Q25
Q18
Offset
Null
(MC34001 only)
1.5 k
1.5 k
VEE
Figure 12. Output Current to Voltage Transformation
for a D–to–A Converter
VCC
MSB A1
A2
A3
A4
A5
A6
A7
LSB A8
Settling time to within 1/2 LSB is approximately 4.0 µs
from the time all bits are switched (C = 68 pF).
R1
Vref
R2
D-to-A
The value of C may be selected to minimize overshoot
and ringing.
VCC = 15 V
Theoretical VO
1
VO =
+
Io
15 pF
VEE
-
VO
MC34001
VEE = -15 V
RO
C
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6
Vref
R1
(RO)
A1
A2
A3 A4
A5
A6 A7 A8
+
+
+
+
+
+
+
2
4
8
16
32
64 128 256
MC34001, B MC34002, B MC34004, B
Figure 13. Positive Peak Detector
8
-
VCC
1/2
2
3 MC34002
+
Vin
4
Reset
6
D1
5
*
1 µF
1N914
VEE
Reset
Network
or Relay
VR
R4
Run
Clear
V1
R3
2
3
R2
C*
R5
+
Figure 15. Isolating Large Capacitive Loads
R2 5.1 k
+15 V
MC34001
7
-
R1 5.1 k 2
4
R6
+2.0 V
0
-2.0 V
-15 V
*Polycarbonate or
Polystyrene Capacitor
MC34001 +
3
∆VO
∆t
Figure 16. Wide BW, Low Noise,
Low Drift Amplifier
C2
Vin
R1
C1
2
7
fmax 240 kHz
10 V
8
6
3
4
-10 V
MC34001
VEE
Sr
240 kHz
Power BW: fmax =
2π Vp
Parasitic input capacitance (C1 3.0 pF plus any additional layout capacitance)
interacts with feedback elements and creates undesirable high-frequency pole.
To compensate add C2 such that: R2C2 R1C1.
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7
6
IO
R3 10
RL 5.1 k
CL 0.5 µF
I
0.02
= O =
V/µs = 0.04 V/µs (with CL shown)
0.5
CL
Design Example: 100 Second Timer
VR = 10 V C = l.0 µF R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k R1 = R2 = 1.0 k
VCC
4
CC
VEE
Overshoot 10%
ts = 10 µs
When driving large CL, the VO slew rate is determined by CL
and IO(max):
Time (t) = R4 Cn (VR/VR-VI), R3 = R4, R5 = 0.1 R6
If R1 = R2: t = 0.693 R4C
R2
7
VO
20 pF
VCC
6
+
VO
7
*Polycarbonate capacitor
D1 = Hi-speed, low-reverse leakage diode
Figure 14. Long Interval RC Timer
R1
- 1/2
MC34002
MC34001, B MC34002, B MC34004, B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
T A
M
B
M
M
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
D
A
8
5
0.25
H
E
1
M
B
M
4
h
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
X 45
e
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
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8
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.18
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
MC34001, B MC34002, B MC34004, B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
14
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
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9
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0
10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0
10
0.39
1.01
MC34001, B MC34002, B MC34004, B
NOTES
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MC34001, B MC34002, B MC34004, B
NOTES
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11
MC34001, B MC34002, B MC34004, B
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to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
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MC34001/D