MC3403_06

MC3403, MC3303 Single Supply Quad Operational Amplifiers The MC3403 is a low cost, quad operational amplifier with true differential inputs. The device has electrical characteristics similar to the popular MC1741C. However, the MC3403 has several distinct advantages over standard operational amplifier types in single supply applications. The quad amplifier can operate at supply voltages as low as 3.0 V or as high as 36 V with quiescent currents about one third of those associated with the MC1741C (on a per amplifier basis). The common mode input range includes the negative supply, thereby eliminating the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage. Features http://onsemi.com MARKING DIAGRAMS 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 MC3x03DG AWLYWW • • • • • • • • • • • • Short Circuit Protected Outputs Class AB Output Stage for Minimal Crossover Distortion True Differential Input Stage Single Supply Operation: 3.0 V to 36 V Split Supply Operation: ±1.5 V to ±18 V Low Input Bias Currents: 500 nA Max Four Amplifiers Per Package Internally Compensated Similar Performance to Popular MC1741C Industry Standard Pin−outs ESD Diodes Added for Increased Ruggedness Pb−Free Packages are Available 14 PDIP−14 P SUFFIX CASE 646 1 MC3x03P AWLYYWWG 14 1 x = 3 or 4 A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Package PIN CONNECTIONS Single Supply 3.0 V to 36 V 1 2 3 4 VEE, GND VEE VCC VCC 1 2 3 4 1.5 V to 18 V Inputs 2 6 Out 2 7 (Top View) VCC 4 5 + 2 − 4+ − 11 10 Inputs 3 9 8 Out 3 VEE/GND 1.5 V to 18 V Inputs 1 3 Split Supplies Out 1 1 2 − + − + 14 Out 4 13 Inputs 4 12 1 3 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 10 1 Publication Order Number: MC3403/D MC3403, MC3303 ORDERING INFORMATION Device MC3303D MC3303DG MC3303DR2 MC3303DR2G MC3303P MC3303PG MC3403D MC3403DG MC3403DR2 MC3403DR2G MC3403P MC3403PG Package SOIC−14 SOIC−14 (Pb−Free) SOIC−14 SOIC−14 (Pb−Free) PDIP−14 PDIP−14 (Pb−Free) SOIC−14 SOIC−14 (Pb−Free) SOIC−14 SOIC−14 (Pb−Free) PDIP−14 PDIP−14 (Pb−Free) 25 Units / Rail 2500 Tape & Reel 55 Units / Rail 25 Units / Rail 2500 Tape & Reel 55 Units / Rail Shipping † †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS Rating Power Supply Voltages Single Supply Split Supplies Input Differential Voltage Range (Note 1) Input Common Mode Voltage Range (Notes 1 and 2) Storage Temperature Range Operating Ambient Temperature Range MC3303 MC3403 Symbol VCC VCC, VEE VIDR VICR Tstg TA Value 36 ±18 ±36 ±18 −55 to +125 −40 to +85 0 to +70 150 Unit Vdc Vdc Vdc °C °C Junction Temperature TJ °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Split power supplies. 2. For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. http://onsemi.com 2 MC3403, MC3303 ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V for MC3403; VCC = +14 V, VEE = GND for MC3303 TA = 25°C, unless otherwise noted.) MC3403 Characteristic Input Offset Voltage TA = Thigh to Tlow (Note 3) Input Offset Current TA = Thigh to Tlow Large Signal Open Loop Voltage Gain VO = ±10 V, RL = 2.0 kW TA = Thigh to Tlow Input Bias Current TA = Thigh to Tlow Output Impedance f = 20 Hz Input Impedance f = 20 Hz Output Voltage Range RL = 10 kW RL = 2.0 kW RL = 2.0 kW, TA = Thigh to Tlow Input Common Mode Voltage Range Common Mode Rejection RS ≤ 10 kW Power Supply Current (VO = 0) RL = ∞ Individual Output Short−Circuit Current (Note 4) Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Average Temperature Coefficient of Input Offset Current TA = Thigh to Tlow Average Temperature Coefficient of Input Offset Voltage TA = Thigh to Tlow Power Bandwidth AV = 1, RL = 10 kW, VO = 20 V(p−p), THD = 5% Small−Signal Bandwidth AV = 1, RL = 10 kW, VO = 50 mV Slew Rate AV = 1, Vi = −10 V to +10 V Rise Time AV = 1, RL = 10 kW, VO = 50 mV Fall Time AV = 1, RL = 10 kW, VO = 50 mV Overshoot AV = 1, RL = 10 kW, VO = 50 mV Phase Margin AV = 1, RL = 2.0 kW, VO = 200 pF Crossover Distortion (Vin = 30 mVpp,Vout= 2.0 Vpp, f = 10 kHz) Symbol VIO IIO AVOL Min − − − − 20 15 − − − 0.3 ±12 ±10 ±10 +13 V −VEE 70 − ±10 − − − Typ 2.0 − 30 − 200 − −200 − 75 1.0 ±13.5 ±13 − +13 V −VEE 90 2.8 ±20 30 30 50 Max 10 12 50 200 − − −500 −800 − − − − − − − 7.0 ±45 150 150 − Min − − − − 20 15 − − − 0.3 12 10 10 +12 V −VEE 70 − ±10 − − − MC3303 Typ 2.0 − 30 − 200 − −200 − 75 1.0 12.5 12 − +12.5 V −VEE 90 2.8 ±30 30 30 50 Max 8.0 10 75 250 − − −500 −1000 − − − − − − − 7.0 ±45 150 150 − Unit mV nA V/mV IIB zo zi VO nA W MW V VICR CMR ICC, IEE ISC PSRR+ PSRR− DIIO/DT V dB mA mA mV/V mV/V pA/°C DVIO/DT − 10 − − 10 − mV/°C BWp BW SR tTLH tTLH os fm − − − − − − − − − 9.0 1.0 0.6 0.35 0.35 20 60 1.0 − − − − − − − − − − − − − − − − 9.0 1.0 0.6 0.35 0.35 20 60 1.0 − − − − − − − − kHz MHz V/ms ms ms % ° % 3. MC3303: Tlow = −40°C, Thigh = +85°C, MC3403: Tlow = 0°C, Thigh = +70°C 4. Not to exceed maximum package power dissipation. http://onsemi.com 3 MC3403, MC3303 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.) MC3403 Characteristic Input Offset Voltage Input Offset Current Input Bias Current Large Signal Open Loop Voltage Gain RL = 2.0 kW Power Supply Rejection Ratio Output Voltage Range (Note 5) RL = 10 kW, VCC = 5.0 V RL = 10 kW, 5.0 ≤ VCC ≤ 30 V Power Supply Current Channel Separation f = 1.0 kHz to 20 kHz (Input Referenced) Symbol VIO IIO IIB AVOL PSRR VOR Min − − − 10 − 3.3 VCC−2.0 − − Typ 2.0 30 −200 200 − 3.5 VCC−1.7 2.5 −120 Max 10 50 −500 − 150 − − 7.0 − Min − − − 10 − 3.3 VCC−2.0 − − MC3303 Typ − − − 200 − 3.5 VCC−1.7 2.5 −120 Max 10 75 −500 − 150 − − 7.0 − Unit mV nA nA V/mV mV/V Vpp ICC CS mA dB 5. Output will swing to ground with a 10 kW pull down resistor. Output Q19 Q20 Q18 Q17 Q16 Bias Circuitry Common to Four Amplifiers VCC Q27 Q23 5.0 pF 31k + Q22 Inputs − Q2 Q3 Q4 Q21 Q25 Q5 60 k Q6 Q7 Q8 Q10 Q24 Q1 2.0 k Q9 37 k 40 k Q28 Q15 Q13 Q11 25 Q12 Q29 Q30 2.4 k VEE (GND) Figure 1. Representative Schematic Diagram (1/4 of Circuit Shown) http://onsemi.com 4 MC3403, MC3303 CIRCUIT DESCRIPTION stage performs not only the first stage gain function but also performs the level shifting and Transconductance reduction functions. By reducing the Transconductance, a smaller compensation capacitor (only 5.0 pF) can be employed, thus saving chip area. The Transconductance reduction is accomplished by splitting the collectors of Q24 and Q22. Another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation, without saturating either the input devices or the differential to single−ended converter. The second stage consists of a standard current source load amplifier stage. The output stage is unique because it allows the output to swing to ground in single supply operation and yet does not exhibit any crossover distortion in split supply operation. This is possible because Class AB operation is utilized. Each amplifier is biased from an internal voltage regulator which has a low temperature coefficient, thus giving each amplifier good temperature characteristics as well as excellent power supply rejection. 120 AV = 100 A VOL , LARGE SIGNAL OPEN LOOP VOLTAGE GAIN (dB) 0.5 V/DIV 100 80 60 40 20 0 −20 1.0 10 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M VCC = 15 V VEE = −15 V TA = 25°C 5.0 V/DIV 20 ms/DIV Figure 2. Inverter Pulse Response The MC3403/3303 is made using four internally compensated, two−stage operational amplifiers. The first stage of each consists of differential input device Q24 and Q22 with input buffer transistors Q25 and Q21 and the differential to single ended converter Q3 and Q4. The first 50 mV/DIV *Note Class A B output stage produces distortion less sinewave. 50 ms/DIV Figure 3. Sine Wave Response Figure 4. Open Loop Frequency Response 30 VO, OUTPUT VOLTAGE RANGE (V pp) VO, OUTPUT VOLTAGE (Vpp ) 25 − 20 15 10 5.0 TA = 25°C 0 −5.0 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M + −15 V VO 10 k +15 V 30 TA = 25°C 20 10 0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 VCC AND (VEE), POWER SUPPLY VOLTAGES (V) 20 Figure 5. Power Bandwidth Figure 6. Output Swing versus Supply Voltage http://onsemi.com 5 MC3403, MC3303 300 I IB, INPUT BIAS CURRENT (nA) VCC = 15 V VEE = −15 V TA = 25°C I IB , INPUT BIAS CURRENT (nA) 170 200 160 100 −75 −55 −35 −15 5.0 25 45 65 85 105 125 150 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 T, TEMPERATURE (°C) VCC AND (VEE), POWER SUPPLY VOLTAGES (V) Figure 7. Input Bias Current versus Temperature Figure 8. Input Bias Current versus Supply Voltage VCC VCC 10 k R2 − 50 k 1N914 5.0 k 1/2 MC3403 + 10 k R1 VO 10 k Vref − 1/2 1N914 VCC VO fo = R C 1 2pRC MC3403 + R1 VO = R1 +R2 VO = 1 V 2 CC Vref = 1 V 2 CC R C For: fo = 1.0 kHz R = 16 kW C = 0.01 mF Figure 9. Voltage Reference Figure 10. Wien Bridge Oscillator e1 + MC3403 − − 1/2 1 R C R2 R Vref 1/2 Hysteresis VOH R1 − R1 a R1 MC3403 + b R1 − 1/2 MC3403 + 1 R C eo Vin MC3403 + R1 VinL = (VOL −Vref) +Vref R1 +R2 VinH = R1 (VOH −Vref) +Vref R1 +R2 R1 (VOH −VOL) R1 +R2 1/2 VO VO VOL VinL Vref VinH e2 R Vh = eo = C (1 +a +b) (e2 −e1) Figure 11. High Impedance Differential Amplifier Figure 12. Comparator with Hysteresis http://onsemi.com 6 MC3403, MC3303 R C1 Vin C − MC3403 + Vref Vref R2 R1 Bandpass Output − TBP = center frequency gain TN = passband notch gain Vref MC3403 + 1/2 1/2 R 100 k C − 100 k fo = 1 2pRC Vref = 1 V 2 CC R1 = QR R2 = R1 TBP R3 = TNR2 C1 = 10 C R2 MC3403 + Vref 1/2 − MC3403 + 1/2 R = 160 kW C = 0.001 mF R1 = 1.6 MW R2 = 1.6 MW R3 = 1.6 MW R3 C1 Notch Output For: fo Q TBP TN = 1.0 kHz = 10 =1 =1 Where: Figure 13. Bi−Quad Filter VCC C Vin R1 C R3 − MC3403 + 1/2 CO VO CO = 10 C 1 V 2 CC Vref = 1 V 2 CC Triangle Wave Output + MC3403 − C Rf f= R1 +RC 4 CRf R1 if R3 = R2 R1 R2 +R1 1/2 R2 R2 300 k R3 + 75 k R1 100 k Vref MC3403 − 1/2 Vref Given: Square Wave Output fo = center frequency A(fo) = gain at center frequency Vref Vref = Choose value fo, C Then: R3 = Q p fo C R1 = R3 2 A(fo) R2 = R1 R5 4Q2 R1 −R5 Oo fo For less than 10% error from operational amplifier < 0.1 BW where fo and BW are expressed in Hz. If source impedance varies, filter may be preceded with voltage follower buffer to stabilize filter parameters. Figure 14. Function Generator Figure 15. Multiple Feedback Bandpass Filter http://onsemi.com 7 MC3403, MC3303 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H − A− 14 8 − B− P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C −T− SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MC3403, MC3303 PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 A F N −T− SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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