MC34063LBGEVB

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Several converter design examples and numerous applications circuits with test data are included. INTRODUCTION The MC34063 and μA78S40 are monolithic switching regulator subsystems intended for use as dc to dc converters. These devices represent a significant advancement in the ease of implementing highly efficient and yet simple switching power supplies. The use of switching regulators is becoming more pronounced over that of linear regulators because the size reductions in new equipment designs require greater conversion efficiency. Another major advantage of the switching regulator is that it has increased application flexibility of output voltage. The output can be less than, greater than, or of opposite polarity to that of the input voltage. control signal will go low and turn off the gate, terminating any further switching of the series−pass element. The output voltage will eventually decrease to below nominal due to the presence of an external load, and will initiate the switching process again. The increase in conversion efficiency is primarily due to the operation of the series−pass element only in the saturated or cutoff state. The voltage drop across the element, when saturated, is small as is the dissipation. When in cutoff, the current through the element and likewise the power dissipation are also small. There are other variations of switching control. The most common are the fixed frequency pulse width modulator and the fixed on−time variable off−time types, where the on−off switching is uninterrupted and regulation is achieved by duty cycle control. Generally speaking, the example given in Figure 1b does apply to MC34063 and μA78S40. PRINCIPLE OF OPERATION In order to understand the difference in operation between linear and switching regulators we must compare the block diagrams of the two step−down regulators shown in Figure 1. The linear regulator consists of a stable reference, a high gain error amplifier, and a variable resistance series−pass element. The error amplifier monitors the output voltage level, compares it to the reference and generates a linear control signal that varies between two extremes, saturation and cutoff. This signal is used to vary the resistance of the series−pass element in a corrective fashion in order to maintain a constant output voltage under varying input voltage and output load conditions. The switching regulator consists of a stable reference and a high gain error amplifier identical to that of the linear regulator. This system differs in that a free running oscillator and a gated latch have been added. The error amplifier again monitors the output voltage, compares it to the reference level and generates a control signal. If the output voltage is below nominal, the control signal will go to a high state and turn on the gate, thus allowing the oscillator clock pulses to drive the series−pass element alternately from cutoff to saturation. This will continue until the output voltage is pumped up slightly above its nominal value. At this time, the © Semiconductor Components Industries, LLC, 2013 December, 2013 − Rev. 6 Vin Vout + Linear Control Signal Error Amp Ref Voltage − a. Linear Regulator Vin Vout Gated Latch Error Amp + Ref Voltage − Digital Control Signal OSC b. Switching Regulator Figure 1. Step−Down Regulators 1 Publication Order Number: AN920/D AN920/D GENERAL DESCRIPTION The MC34063 series is a monolithic control circuit containing all the active functions required for dc to dc converters. This device contains an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active peak current limit circuit, driver, and a high current output switch. This series was specifically designed to be incorporated in step−up, step−down and voltage−inverting converter applications. These functions are contained in an 8−pin dual in−line package shown in Figure 2a. The μA78S40 is identical to the MC34063 with the addition of an on−board power catch diode, and an uncommitted operational amplifier. This device is in a 16−pin dual in−line package which allows the reference and the noninverting input of the comparator to be pinned out. These additional features greatly enhance the flexibility of this part and allow the implementation of more sophisticated applications. These may include series−pass regulation of the main output or of a derived second output voltage, a tracking regulator configuration or even a second switching regulator. these conditions, the comparator’s output can inhibit a portion of the output switch on−cycle, a complete cycle, a complete cycle plus a portion of one cycle, multiple cycles, or multiple cycles plus a portion of one cycle. Drive 8 Collector B Latch S A Q 170 3 Timing Capacitor 1.25 V Reference Regulator + Comp Switch Emitter CT VCC 6 Comparator Inverting 5 Input 2 Q1 Ipk 7 Sense OSC Switch Collector Q2 R Ipk 1 − 4 Ground VCC Ipk Sense Driver Collector Switch Collector 10 Timing Capacitor 9 GND Inverting Input 12 13 14 15 16 11 GND CT OSC S B Comp − + 1.25 V Ref Latch A Ipk Q R 170 Op Amp − D1 3 2 1 Diode Cathode Noninverting Input 4 Diode Anode Inverting Input 5 Switch Emitter 6 VCC Op Amp 7 Ref Output + 8 Output FUNCTIONAL DESCRIPTION The oscillator is composed of a current source and sink which charges and discharges the external timing capacitor CT between an upper and lower preset threshold. The typical charge and discharge currents are 35 μA and 200 μA respectively, yielding about a one to six ratio. Thus the ramp−up period is six times longer than that of the ramp−down as shown in Figure 3. The upper threshold is equal to the internal reference voltage of 1.25 V and the lower is approximately equal to 0.75 V. The oscillator runs continuously at a rate controlled by the selected value of CT. During the ramp−up portion of the cycle, a Logic “1” is present at the “A” input of the AND gate. If the output voltage of the switching regulator is below nominal, a Logic “1” will also be present at the “B” input. This condition will set the latch and cause the “Q” output to go to a Logic “1”, enabling the driver and output switch to conduct. When the oscillator reaches its upper threshold, CT will start to discharge and Logic “0” will be present at the “A” input of the AND gate. This logic level is also connected to an inverter whose output presents a Logic “1” to the reset input of the latch. This condition will cause “Q” to go low, disabling the driver and output switch. A logic truth table of these functional blocks is shown in Figure 4. The output of the comparator can set the latch only during the ramp−up of CT and can initiate a partial or full on−cycle of output switch conduction. Once the comparator has set the latch, it cannot reset it. The latch will remain set until CT begins ramping down. Thus the comparator can initiate output switch conduction, but cannot terminate it and the latch is always reset when CT begins ramping down. The comparator’s output will be at a Logic “0” when the output voltage of the switching regulator is above nominal. Under Noninverting Input a. MC34063 b. mA78S40 Figure 2. Functional Block Diagrams V Upper Threshold 1.25 V Typical Lower Threshold 0.75 V Typical t 6t Charge t Discharge Figure 3. CT Voltage Waveform http://onsemi.com 2 AN920/D Active Condition of Timing Capacitor, CT AND Gate Inputs A Latch Inputs Output Switch B S R Begins Ramp−Up 0 0 0 Switching regulator’s output is ≥ nominal (‘B’ = 0). Begins Ramp−Down 0 0 0 No change since ‘B’ was 0 before CT Ramp− Down. Comments on State of Output Switch Ramping Down 0 0 1 0 No change even though switching regulator’s output < nominal. Output switch cannot be initiated during RT Ramp−Down. Ramping Down 0 0 1 0 No change since output switch conduction was terminated when ‘A’ went to 0. Ramping Up 1 0 Ramping Up 1 0 Switching regulator’s output went < nominal during CT Ramp−Up (‘B’ → 1). Partial on− cycle for output switch. 1 Switching regulator’s output went ≥ nominal (‘B’ → 0) during CT Ramp−Up. No change since ‘B’ cannot reset latch. Begins Ramp−Up 1 Complete on−cycle since ‘B’ was 1 before CT started Ramp−Up. Begins Ramp−Down 1 Output switch conduction is always terminated whenever CT is Ramping Down. Figure 4. Logic Truth Table of Functional Blocks Current limiting is accomplished by monitoring the voltage drop across an external sense resistor placed in series with VCC and the output switch. The voltage drop developed across this resistor is monitored by the Ipk Sense pin. When this voltage becomes greater than 330 mV, the current limit circuitry provides an additional current path to charge the timing capacitor CT. This causes it to rapidly reach the upper oscillator threshold, thereby shortening the time of output switch conduction and thus reducing the amount of energy stored in the inductor. This can be observed as an increase in the slope of the charging portion of the CT voltage Comparator Output waveform as shown in Figure 5. Operation of the switching regulator in an overload or shorted condition will cause a very short but finite time of output conduction followed by either a normal or extended off−time internal provided by the oscillator ramp−down time of CT. The extended interval is the result of charging CT beyond the upper oscillator threshold by overdriving the current limit sense input. This can be caused by operating the switching regulator with a severely overloaded or shorted output or having the input voltage grossly above the nominal design value. 1 0 Timing Capacitor, CT Output Switch On Off Nominal Output Voltage Level Output Voltage Startup Quiescent Operation Figure 5. Typical Operating Waveforms http://onsemi.com 3 AN920/D Ichg, Charging Current (mA) 30 10 3.0 TA = 25°C VCC = 40 V L Q1 +Vin +Vout MC34063 μA78S40 VCC = 5 V + D1 Co RL 1.0 a. Step−Down Vout  Vin 0.3 0.1 0.03 0 L Ichg = Idischg 0.2 0.4 0.6 0.8 VCLS, Current−Limit Sense Voltage (V) +Vin MC34063 μA78S40 1.0 +Vout D1 Figure 6. Timing Capacitor Charge Current versus Current−Limit Sense Voltage + Q1 Co RL b. Step−Up Vout  Vin Under extreme conditions, the voltage across CT will approach VCC and can cause a relatively long off−time. This action may be considered a feature since it will reduce the power dissipation of the output switch considerably. This feature may be disabled on the μA78S40 only, by connecting a small signal PNP transistor as a clamp. The emitter is connected to CT, the base to the reference output, and the collector to ground. This will limit the maximum charge voltage across CT to less than 2.0 V. With the use of current limiting, saturation of the storage inductor may be prevented as well as achieving a soft startup. In practice the current limit circuit will somewhat modify the charging slope and peak amplitude of CT each time the output switch is required to conduct. This is because the threshold voltage of the current limit sense circuit exhibits a “soft” voltage turn−on characteristic and has a turn−off time delay that causes some overshoot. The 330 mV threshold is defined where the charge and discharge currents are of equal value with VCC = 5.0 V, as shown in Figure 6. The current limit sense circuit can be disabled by connecting the Ipk Sense pin to VCC. To aid in system design flexibility, the driver collector, output switch collector and emitter are pinned out separately. This allows the designer the option of driving the output switch transistor into saturation with a selected forced gain or driving it near saturation when connected as a Darlington. The output switch has a typical current gain of 70 at 1.0 A and is designed to switch a maximum of 40 V collector−to−emitter, with up to 1.5 A peak collector current. The μA78S40 has the additional features of an on−chip uncommitted operational amplifier and catch diode. The op amp is a high gain single supply type with an input common−mode voltage range that includes ground. The output is capable of sourcing up to 150 mA and sinking 35 mA. A separate VCC pin is provided in order to reduce the integrated circuit standby current and is useful in low power applications if the operational amplifier is not incorporated into the main switching system. The catch diode is constructed from a lateral PNP transistor and is capable of blocking up to 40 V and will conduct current up to 1.5 A. There is, however, a “catch” when using it. Q1 +Vin −Vout D1 μA78S40 L + Co RL c. Voltage−Inverting |Vout|   Vin Figure 7. Basic Switching Regulator Configurations Because the integrated circuit substrate is common with the internal and external circuitry ground, the cathode of the diode cannot be operated much below ground or forward biasing of the substrate will result. This totally eliminates the diode from being used in the basic voltage inverting configuration as in Figure 15, since the substrate, pin 11, is common to ground. The diode can be considered for use only in low power converter applications where the total system component count must be held to a minimum. The substrate current will be about 10 percent of the catch diode current in the step−up configuration and about 20 percent in the step−down and voltage−inverting in which pin 11 is common to the negative output. System efficiency will suffer when using this diode and the package dissipation limits must be observed. STEP−DOWN SWITCHING REGULATOR OPERATION Shown in Figure 7a is the basic step−down switching regulator. Transistor Q1 interrupts the input voltage and provides a variable duty cycle squarewave to a simple LC filter. The filter averages the squarewaves producing a dc output voltage that can be set to any level less than the input by controlling the percent conduction time of Q1 to that of the total switching cycle time. Thus, ǒ Ǔ ton Vout + Vinǒ% tonǓ or Vout + Vin ton ) toff The MC34063/μA78S40 achieves regulation by varying the on−time and the total switching cycle time. An explanation of the step−down converter operation is as follows: Assume that the transistor Q1 is off, the inductor current IL is zero, and the output voltage Vout is at its nominal http://onsemi.com 4 AN920/D value. The output voltage across capacitor Co will eventually decay below nominal because it is the only component supply current into the external load RL. This voltage deficiency is monitored by the switching control circuit and causes it to drive Q1 into saturation. The inductor current will start to flow from Vin through Q1 and, Co in parallel with RL, and rise at a rate of ΔI/ΔT = V/L. The voltage across the inductor is equal to Vin − Vsat − Vout and the peak current at any instant is: IL + The off−time, toff, is the time that diode D1 is in conduction and it is determined by the time required for the inductor current to return to zero. The off−time is not related to the ramp−down time of CT. The cycle time of the LC network is equal to ton(max) + toff and the minimum operating frequency is: 1 fmin + ton(max) ) toff A minimum value of inductance can now be calculated for L. The known quantities are the voltage across the inductor and the required peak current for the selected switch conduction time. ǒVin * VsatL * VoutǓ t At the end of the on−time, Q1 is turned off. As the magnetic field in the inductor starts to collapse, it generates a reverse voltage that forward biases D1, and the peak current will decay at a rate of ΔI/ΔT = V/L as energy is supplied to Co and RL. The voltage across the inductor during this period is equal to Vout + VF of D1, and the current at any instant is: IL + IL(pk) * V * Vsat * Vout Lmin + in ton Ipk(switch) This minimum value of inductance was calculated by assuming the onset of continuous conduction operation with a fixed input voltage, maximum output current, and a minimum charge−current oscillator. The net charge per cycle delivered to the output filter capacitor Co, must be zero, Q+ = Q−, if the output voltage is to remain constant. The ripple voltage can be calculated from the known values of on−time, off−time, peak inductor current, and output capacitor value. ǒVoutL) VFǓ t Assume that during quiescent operation the average output voltage is constant and that the system is operating in the discontinuous mode. Then IL(peak) attained during ton must decay to zero during toff and a ratio of ton to toff can be determined. ǒ Ǔ ǒ Vripple(p−p) + Ǔ Vin * Vsat * Vout V ) VF ton + out toff L L where i t + tonń2 and iȀ t + Ť t2 iȀ t dt t1 1 I t 2 pk toffń2 Ť Ť Ť Ipk (tonń2)2 Ipk (toffń2)2 + 1 ) 1 2 2 Co ton Co toff + IL(pk)(ton ) toff) + Iout (ton ) toff) 2 Ipk (ton ) toff) 8 Co A graphical derivation of the peak−to−peak ripple voltage can be obtained from the capacitor current and voltage waveforms in Figure 8. The calculations shown account for the ripple voltage contributed by the ripple current into an ideal capacitor. In practice, the calculated value will need to be increased due to the internal equivalent series resistance ESR of the capacitor. The additional ripple voltage will be equal to Ipk(ESR). Increasing the value of the filter capacitor will reduce the output ripple voltage. However, a point of diminishing return will be reached because the comparator requires a finite voltage difference across its inputs to control the latch. This voltage difference to completely change the latch states is about 1.5 mV and the minimum achievable ripple at the output will be the feedback divider ratio multiplied by 1.5 mV or: NIL(pk) + 2 Iout The peak inductor current is also equal to the peak switch current Ipk(switch) since the two are in series. The on−time, ton, is the maximum possible switch conduction time. It is equal to the time required for CT to ramp up from its lower to upper threshold. The required value for CT can be determined by using the minimum oscillator charging current and the typical value for the oscillator voltage swing both taken from the data sheet electrical characteristics table. ǒ Ǔ CT + Ichg(min) Dt DV ǒ Ǔ 10− 5 ton 1 I t 2 pk ǒC1oǓ ŕ Substituting for t1 and t2 − t1 yields: ǒIL(pk) Ǔ ton ) ǒIL(pk) Ǔ toff + ǒIout tonǓ ) ǒIout toffǓ 2 2 + 4.0 i t dt ) Ipk t2 t1 Ipk t2 t2 + 1 ) 1 t Co on 2 0 Co toff 2 t1 t t And t1 + on and t2 * t1 + off 2 2 Note that the volt−time product of ton must be equal to that of toff and the inductance value is not of concern when determining their ratio. If the output voltage is to remain constant, the average current into the inductor must be equal to the output current for a complete cycle. The peak inductor current with respect to output current is: t 10− 6 on 0.5 t1 0 Vout ) VF t N on + Vin * Vsat * Vout toff + 20 ǒC1oǓ ŕ V Vripple(p−p)min + out (1.5 Vref http://onsemi.com 5 10− 3) AN920/D Voltage Across Switch Q1 VCE Voltage Across Diode D1 VKA Vin + VF Vin Vsat 0 Vin Vin − Vsat 0 VF Ipk Switch Q1 Current Iin = IC(AVG) 0 Ipk Diode D1 Current ID(AVG) 0 Ipk Iout = Ipk/2 = IC(AVG) + ID(AVG) Capacitor Co Current 0 −Ipk/2 Capacitor Co Ripple Voltage ÌÌÌÌ ÏÏÌÌ ÌÌÌÌÌÌÌÏÏÌÌ ÌÌÌ Q+ 1/2 Ipk/2 Q− toff/2 0 +Ipk/2 ton/2 Inductor Current Vout + Vpk Vout Vripple(p−p) Vout − Vpk t0 t1 t2 Figure 8. Step−Down Switching Regulator Waveforms This problem becomes more apparent in a step−up converter with a high output voltage. Figures 12 and 13 show two different ripple reduction techniques. The first uses the μA78S40 operational amplifier to drive the comparator in the feedback loop. The second technique uses a Zener diode to level shift the output down to the reference voltage. 1. Determine the ratio of switch conduction ton versus diode conduction toff time. ton Vout ) VF + Vin(min) * Vsat * Vout toff + 5.0 ) 0.8 21.6 * 0.8 * 5.0 + 0.37 Step−Down Switching Regulator Design Example 2. The cycle time of the LC network is equal to ton(max) + toff. A schematic of the basic step−down regulator is shown in Figure 9. The μA78S40 was chosen in order to implement a minimum component system, however, the MC34063 with an external catch diode can also be used. The frequency chosen is a compromise between switching losses and inductor size. There will be a further discussion of this and other design considerations later. Given are the following: Vout = 5.0 V Iout = 50 mA fmin = 50 kHz Vin(min) = 24 V − 10% or 21.6 V Vripple(p−p) = 0.5% Vout or 25 mVp−p ton(max) ) toff + 1 fmin + 1 50 103 + 20 ms per cycle 3. Next calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton + toff in #2. By using substitution and some algebraic gymnastics, an equation can be written for toff in terms of ton/toff and ton + toff. http://onsemi.com 6 AN920/D The equation is: toff + Note that the ratio of ton/(ton + toff) does not exceed the maximum of 6/7 or 0.857. This maximum is defined by the 6:1 ratio of charge−to−discharge current of timing capacitor CT (refer to Figure 3). 4. The maximum on−time, ton(max), is set by selecting a value for CT. ton(max) ) toff ton )1 t off + 20 10− 6 0.37 ) 1 10− 5 ton CT + 4.0 + 14.6 ms Since ton(max) ) toff + 20 ms 10− 5 (5.4 + 4.0 ton(max) + 20 ms * 14.6 ms 10− 6) + 216 pF Use a standard 220 pF capacitor. + 5.4 ms Vin = 24 V 47 + Rsc R2 R1 36 k 12 k 2.7 CT 220 pF 9 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 13 VCC 7 6 5 4 3 2 1 1N5819 * 853 μH Vout 5 V/50 mA L Co 27 Test Conditions + Results Line Regulation Vin = 18 to 30 V, Iout = 50 mA Δ = 16 mV or ± 0.16% Load Regulation Vin = 24 V, Iout = 25 to 50 mA Δ = 28 mV or ± 0.28% Output Ripple Vin = 21.6 V, Iout = 50 mA Short Circuit Current Vin = 24 V, RL = 0.1 Ω Efficiency, Internal Diode Vin = 24 V, Iout = 50 mA 45.3% Efficiency, External Diode* Vin = 24 V, Iout = 50 mA 72.6% 24 mVp−p 105 mA Figure 9. Step−Down Design Example http://onsemi.com 7 AN920/D 9. The nominal output voltage is programmed by the R1, R2 resistor divider. The output voltage is: 5. The peak switch current is: Ipk(switch) + 2 Iout + 2 (50 ǒ The divider current can go as low as 100 μA without affecting system performance. In selecting a minimum current divider R1 is equal to: + 100 mA 6. With knowledge of the peak switch current and maximum on time, a minimum value of inductance can be calculated. Lmin + R1 + * Vsat * Vout ǒVin(min)Ipk(switch) Ǔ ton(max) ǒ Ǔ + 21.6 * 0.8 * 5.0 5.4 100 10− 3 R2 + R1 R2 + 12 Ǔ ǒ Ǔ + 36 k 0.33 IȀpk(switch) 115 0.33 10− 3 This value may have to be adjusted downward to compensate for conversion losses and any increase in Ipk(switch) current if Vin varies upward. Do not set Rsc to exceed the maximum Ipk(switch) limit of 1.5 A when using the internal switch transistor. 8. A minimum value for an ideal output filter capacitor can now be obtained. + Vout + Vin 8 (25 t ǒtton Ǔ ) Vin or Vout + Vin ǒ on ) 1Ǔ toff off An explanation of the step−up converter’s operation is as follows. Initially, assume that transistor Q1 is off, the inductor current is zero, and the output voltage is at its nominal value. At this time, load current is being supplied only by Co and it will eventually fall below nominal. This deficiency will be sensed by the control circuit and it will initiate an on−cycle, driving Q1 into saturation. Current will start to flow from Vin through the inductor and Q1 and rise at a rate of ΔI/ΔT = V/L. The voltage across the inductor is equal to Vin − Vsat and the peak current is: Ipk(switch) (ton ) toff) 8 Vripple(p−p) 0.1 (20 5.0 * 1Ǔ ǒ1.25 STEP−UP SWITCHING REGULATOR OPERATION The basic step−up switching regulator is shown in Figure 7b and the waveform is in Figure 10. Energy is stored in the inductor during the time that transistor Q1 is in the “on” state. Upon turn−off, the energy is transferred in series with Vin to the output filter capacitor and load. This configuration allows the output voltage to be set to any value greater than that of the input by the following relationship: + 2.86 W, use 2.7 W Co + 103 Using the above derivation, the design is optimized to meet the assumed conditions. At Vin(min), operation is at the onset of continuous mode and the output current capability will be greater than 50 mA. At Vin(nom) i.e., 24 V, the current limit will activate slightly above the rated Iout of 50 mA. 10− 6 + 115 mA + out * 1Ǔ ǒV1.25 If a standard 5% tolerance 12 k resistor is chosen for R1, R2 will also be a standard value. V * Vsat * Vout IȀpk(switch) + in ton(max) Lmin + 24 * 0.8 * 5.0 5.4 853 10− 6 1.25 10− 6 Rearranging the above equation so that R2 can be solved yields: 10− 6 7. A value for the current limit resistor, Rsc, can be determined by using the current level of Ipk(switch) when Vin = 24 V. Rsc + 100 + 12, 500 W + 853 mH ǒ Ǔ Vout + 1.25 R2 ) 1 R1 10− 3) 10− 6) 10− 3) + 10 mF Ideally this would satisfy the design goal, however, even a solid tantalum capacitor of this value will have a typical ESR (equivalent series resistance) of 0.3 Ω which will contribute 30 mV of ripple. The ripple components are not in phase, but can be assumed to be for a conservative design. In satisfying the example shown, a 27 μF tantalum with an ESR of 0.1 Ω was selected. The ripple voltage should be kept to a low value since it will directly affect the system line and load regulation. IL + ǒVin *L VsatǓ t When the on−time is completed, Q1 will turn off and the magnetic field in the inductor will start to collapse generating a reverse voltage that forward biases D1, supplying energy to Co and RL. The inductor current will decay at a rate of ΔI/ΔT = V/L and the voltage across it is equal to Vout + VF − Vin. The current at any instant is: http://onsemi.com 8 AN920/D Voltage Across Switch Q1 VCE Diode D1 Voltage VKA Vout + VF Vin Vsat 0 Vout − Vsat 0 VF Ipk Switch Q1 Current 0 Ipk Diode D1 Current Iout 0 Ipk Inductor Current Iin = IL(AVG) 0 ÌÌ ÌÌ ÑÑ ÑÑÏÏÏÏÏÌÌÌÌÌÌ Ipk − Iout Capacitor Co Current 1/2(Ipk − Iout) 0 −Iout Capacitor Co Ripple Voltage Q+ toff t1 Vout + Vpk Q− ton Vripple(p−p) Vout Vout − Vpk Figure 10. Step−Up Switching Regulator Waveforms IL + IL(pk) * ǒVout ) VLF * VinǓ t Figure 10 shows the step−up switching regulator waveforms. By observing the capacitor current and making some substitutions in the above statement, a formula for peak inductor current can be obtained. Assuming that the system is operating in the discontinuous mode, the current through the inductor will reach zero after the toff period is completed. Then IL(pk) attained during ton must decay to zero during toff and a ratio of ton to toff can be written. ǒ Ǔ ǒ ǒIL(pk) Ǔ toff + Iout (ton ) toff) 2 ǒ Ǔ t IL(pk) + 2 Iout on ) 1 toff Ǔ Vin * Vsat V ) VF * Vin ton + out toff L L The peak inductor current is also equal to the peak switch current, since the two are in series. With knowledge of the voltage across the inductor during ton and the required peak current for the selected switch conduction time, a minimum inductance value can be determined. t V ) VF * Vin N on + out Vin * Vsat toff Note again, that the volt−time product of ton must be equal to that of toff and the inductance value does not affect this relationship. The inductor current charges the output filter capacitor through diode D1 only during toff. If the output voltage is to remain constant, the net charge per cycle delivered to the output filter capacitor must be zero, Q+ = Q−. ǒ Ǔ Vin * Vsat Lmin + t Ipk(switch) on(max) The ripple voltage can be calculated from the known values of on−time, off−time, peak inductor current, output current and output capacitor value. Referring to the Ichg toff + Idischg ton http://onsemi.com 9 AN920/D capacitor current waveforms in Figure 10, t1 is defined as the capacitor charging interval. Solving for t1 in known terms yields: Vout ) VF * Vin(min) ton + Vin(min) * Vsat toff + 28 ) 0.8 * 6.75 6.75 * 0.3 Ipk * Iout Ipk + t1 toff ǒ + 3.42 Ǔ Ipk * Iout Nt1 + toff Ipk 2. The cycle time of the LC network is equal to ton(max) + toff. And the current during t1 can be written: ǒ ton(max) ) toff + 1 fmin Ǔ Ipk * Iout I+ t t1 + The ripple voltage is: Vripple(p−p) + ǒC1oǓ ŕ t1 0 3. Next calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton + toff in #2. Ť 20 10− 6 toff + 3.42 ) 1 Ipk * Iout t2 t1 + 1 2 0 t1 Co + 4.5 ms (Ipk * Iout) + 1 t1 2 Co ton + 20 ms * 4.5 ms Substituting for t1 yields: + 15.5 ms (Ipk * Iout) (Ipk * Iout) + 1 toff 2 Ipk Co (Ipk * Iout)2 toff + 2 Ipk Co Note that the ratio of ton/(ton + toff) does not exceed the maximum of 0.857. 4. The maximum on−time, ton(max), is set by selecting a value for CT. A simplified formula that will give an error of less than 5% for a voltage step−up greater than 3 with an ideal capacitor is shown: Vripple(p−p) [ 103 + 20 ms per cycle Ipk * Iout t dt t1 Ť 1 50 CT + 4.0 + 4.0 ǒICouto Ǔ ton 10− 5 ton 10− 5 (15.5 10− 6) + 620 pF 5. The peak switch current is: This neglects a small portion of the total Q− area. The area neglected is equal to: ǒ Ǔ t Ipk(switch) + 2 Iout on ) 1 toff I A + (toff * t1) out 2 + 2 (50 10− 3) (3.42 ) 1) + 442 mA Step−Up Switching Regulator Design Example 6. A minimum value of inductance can be calculated since the maximum on−time and peak switch current are known. The basic step−up regulator schematic is shown in Figure 11. The μA78S40 again was chosen in order to implement a minimum component system. The following conditions are given: Vout = 28 V Iout = 50 mA fmin = 50 kHz Vin(min) = 9.0 V − 25% or 6.75 V Vripple(p−p) = 0.5% Vout or 140 mVp−p 1. Determine the ratio of switch conduction ton versus diode conduction toff time. Lmin + + * Vsat ǒVin(min) Ǔ ton Ipk(switch) 6.75 * 0.3 Ǔ 15.5 ǒ442 10− 3 + 226 mH http://onsemi.com 10 10− 6 AN920/D 7. A value for the current limit resistor, Rsc, can now be determined by using the current level of Ipk(switch) when Vin = 9.0 V. ǒ Co [ Ǔ [ V * Vsat IȀpk(switch) + in ton(max) Lmin + ǒ2269.0 *100.3− 6Ǔ 15.5 9 50 140 10− 3 15.5 10− 3 10− 6 [ 50 mF 10− 6 The ripple contribution due to the gain of the comparator: + 597 mA 0.33 Rsc + IȀpk(switch) + 9 Iout t Vripple(p−p) on V Vripple(p−p) + out 1.5 Vref 10− 3 + 28 1.5 1.25 10− 3 0.33 597 10− 3 + 33.6 mV + 0.55 W, use 0.5 W A 27 μF tantalum capacitor with an ESR of 0.10 Ω was again chosen. The ripple voltage due to the capacitance value is 28.7 mV and 44.2 mV due to ESR. This yields a total ripple voltage of: Note that current limiting in this basic step−up configuration will only protect the switch transistor from overcurrent due to inductor saturation. If the output is severely overloaded or shorted, D1, L, or Rsc may be destroyed since they form a direct path from Vin to Vout. Protection may be achieved by current limiting Vin or replacing the inductor with 1:1 turns ratio transformer. 8. An approximate value for an ideal output filter capacitor is: V Eripple(p−p) + out 1.5 Vref I 10− 3 ) out ton ) Ipk ESR Co + 33.6 mV ) 28.7 mV ) 44.2 mV + 107 mV http://onsemi.com 11 AN920/D Vin = 9 V + 47 226 μH Rsc R2 R1 47 k 2.2 k 0.5 CT 620 pF 9 10 11 GND CT OSC 12 13 VCC 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 240 7 6 5 4 3 2 1 1N5819 * Co 27 Test Conditions + Vout 5 V/50 mA Results Line Regulation Vin = 6.0 to 12 V, Iout = 50 mA Δ = 120 mV or ± 0.21% Load Regulation Vin = 9.0 V, Iout = 25 to 50 mA Δ = 50 mV or ± 0.09% Output Ripple Vin = 6.75 V, Iout = 50 mA 90 mVp−p Efficiency, Internal Diode Vin = 9.0 V, Iout = 50 mA 62.2% Efficiency, External Diode* Vin = 9.0 V, Iout = 50 mA 74.2% Figure 11. Step−Up Design Example http://onsemi.com 12 AN920/D Vin L Rsc CT 9 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 13 VCC 7 6 5 4 3 2 1 R2 R1 Figure 12. mA78S40 Ripple Reduction Technique http://onsemi.com 13 Vout + Co AN920/D The current required to drive the internal 170 Ω base−emitter resistor is: L I170 W + 8 1 S Q Vin The driver collector current is equal to sum of 22.1 mA + 4.1 mA = 26.2 mA. Allow 0.3 V for driver saturation and 0.2 V for the drop across Rsc (0.5 × 442 mA Ipk). Then the driver collector resistor is equal to: 2 Ipk 6 + 4.1 mA Q1 7 Rsc + 0.7 170 Q2 R OSC D1 CT VCC 3 1.25 V Reference Regulator + Comp − 5 GND Rdriver + CT + VZ = Vout − 1.25 V + Co 9. The nominal output voltage is programmed by the R1, R2 divider. Ǔ Vout + 1.25 1 ) R2 R1 Vout + Vin A standard 5% tolerance, 2.2 k resistor was selected for R1 so that the divider current is about 500 μA. R1 + 500 1.25 10− 6 out * 1Ǔ ǒV1.25 + 2200 (Vin * Vsat) ton + (|Vout| ) VF) toff 28 * 1Ǔ ǒ1.25 |Vout| ) VF t N on + Vin * Vsat toff + 47, 080 W, use 47 k The derivations and the formulas for Ipk(switch), Lmin, and Co are the same as that of the step−up converter. 10. In this design example, the output switch transistor is driven into saturation with a forced gain of 20 at an input voltage of 7.0 V. The required base drive is: IB + + Ipk(switch) Bf 442 ǒtton Ǔ off The voltage−inverting converter operates almost identically to that of the step−up previously discussed. The voltage across the inductor during ton is Vin − Vsat but during toff the voltage is equal to the negative magnitude of Vout + VF. Remember that the volt−time product of ton must be equal to that of toff, a ratio of ton to toff can be determined. + 2500 W, use 2.2 k Then R2 + R1 7.0 * 0.3 * 0.2 (22.1 ) 4.1) 10− 3 VOLTAGE−INVERTING SWITCHING REGULATOR OPERATION The basic voltage−inverting switching regulator is shown in Figure 7c and the operating waveforms are in Figure 14. Energy is stored in the inductor during the conduction time of Q1. Upon turn−off, the energy is transferred to the output filter capacitor and load. Notice that in this configuration the output voltage is derived only from the inductor. This allows the magnitude of the output to be set to any value. It may be less than, equal to, or greater than that of the input and is set by the following relationship: Figure 13. MC34063 Ripple Reduction Technique ǒ Vin * Vsat(driver) * VRSC IB ) I170 W + 248 W, use 240 W 4 Vout R1 VBE(switch) 170 10− 3 20 + 22.1 mA http://onsemi.com 14 AN920/D Vin Vsat 0 Voltage Across Switch Q1 VCE Vin − (−Vout + VF) (Vin − Vsat) + Vout Diode D1 Voltage VKA 0 VF Ipk Switch Q1 Current Iin = IC(AVG) 0 Ipk Diode D1 Current Iout 0 Ipk Inductor Current 0 Ipk − Iout Capacitor Co Current ÌÌÌ ÑÑÑ ÌÌÌ ÑÑÑÏÏÏÏÌÌÌÌÌÌÌ 1/2(Ipk − Iout) 0 −Iout Capacitor Co Ripple Voltage Q+ toff t1 −Vout + Vpk Q− ton Vripple(p−p) Vout −Vout − Vpk Figure 14. Voltage−Inverting Switching Regulator Waveforms Voltage−Inverting Switching Regulator Design Example 2. The cycle time of the LC network is equal to ton(max) + toff. A circuit diagram of the basic voltage−inverting regulator is shown in Figure 15. The μA78S40 was selected for this design since it has the reference and both comparator inputs pinned out. The following operating conditions are given: Vout = −15 V Iout = 500 mA fmin = 50 kHz Vin(min) = 15 V − 10% or 13.5 V Vripple(p−p) = 0.4% Vout or 60 mVp−p 1. Determine the ratio of switch conduction ton versus diode conductions toff time. ton(max) ) toff + 1 fmin + 50 1 10− 3 + 20 ms 3. Calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton + toff in #2. 20 10− 6 toff + 1.24 ) 1 + 8.9 ms |Vout| ) VF ton + Vin * Vsat toff ton + 20 ms * 8.9 ms + 11.1 ms + 15 ) 0.8 13.5 * 0.8 + 1.24 http://onsemi.com 15 AN920/D Note again that the ratio of ton/(ton + toff) does not exceed the maximum of 0.857. Vin = 15 V 100 R2 36 k + Q2 MPS U51A Rsc CT 430 pF 9 10 11 GND CT OSC 12 13 VCC 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 RB 160 160 7 6 1N5822 5 4 3 2 Vout −15 V/0.5 A 1 L 66.5 μH Co 470 + R1 3.0 k * RBE 0.12 Co 470 + * Heatsink, IERC PSC2−3CB Test Conditions Results Line Regulation Vin = 12 to 16 V, Iout = 0.5 A Δ = 3.0 mV or ± 0.01% Load Regulation Vin = 15 V, Iout = 0.1 to 0.5 A Δ = 27 mV or ± 0.09% Output Ripple Vin = 13.5 V, Iout = 0.5 A Short Circuit Current Vin = 15 V, RL = 0.1 Ω 2.5 A Efficiency Vin = 15 V, Iout = 0.5 A 80.6% 35 mVp−p Figure 15. Voltage−Inverting Design Example 4. A value of CT must be selected in order to set ton(max). CT + 4.0 + 4.0 10− 5 ton 10− 5 (11.1 ǒ Ǔ t Ipk(switch) + 2 Iout on ) 1 toff + 2 (500 10− 6) 10− 3) (1.24 ) 1) + 2.24 A 6. The minimum required inductance value is: + 444 pF, use 430 pF 5. The peak switch current is: http://onsemi.com 16 AN920/D Lmin + * Vsat ǒVin(min) Ǔ ton Ipk(switch) ǒ Ǔ + 13.5 * 0.8 11.1 2.24 + 66.5 mH also be at ground potential when Vout is in regulation. The magnitude of Vout is: |Vout| + 1.25 R2 R1 10− 6 A divider current of about 400 μA was desired for this example. 7. The current−limit resistor value was selected by determining the level of Ipk(switch) for Vin = 16.5 V. IȀpk(switch) + + R1 + ǒVinL*minVsatǓ ton 16.5 * 0.8 Ǔ 11.1 ǒ66.5 10− 6 Then R2 + 10− 6 + 36 k + 0.13 W, use 0.12 W IB + 8. An approximate value for an ideal output filter capacitor is: Ǔ + 64 mA The value for the base−emitter turn−off resistor RBE is determined by: 10− 6 RBE + [ 92.5 mF The ripple contribution due to the gain of the comparator is: Vripple(p−p) + |Vout| 1.5 Vref + 15 1.5 1.25 + 10− 3 10 (35) 2.24 The additional base current required due to RBE is: 10− 3 IRBE + VBE (Q2) RBE + 0.8 160 For a given level of ripple, the ESR of the output filter capacitor becomes the dominant factor in choosing a value for capacitance. Therefore two 470 μF capacitors with an ESR of 0.020 Ω each was chosen. The ripple voltage due to the capacitance value is 5.9 mV and 22.4 mV due to ESR. This yields a total ripple voltage of: |Vout| 1.5 Vref 10 Bf Ipk(switch) + 156.3 W, use 160 W + 18 mV Eripple(p−p) + Ipk(switch) Bf + 2.24 35 Iout Co [ t Vripple(p−p) on 0.5 11.1 60 10− 3 10− 3 10. Output switch transistor Q2 is driven into a soft saturation with a forced gain of 35 at an input voltage of 13.5 V in order to enhance the turn−off switching time. The required base drive is: + 0.33 2.62 [ |Vout| R1 1.25 + 15 3.0 1.25 0.33 IȀpk(switch) ǒ 1.25 10− 6 + 3,125 W, use 3.0 k + 2.62 A Rsc + 400 + 5.0 mA Then IB (Q2) is equal to the sum of 64 mA + 5.0 mA = 69 mA. Allow 0.8 V for the IC driver saturation and 0.3 V for the drop across Rsc (0.12 × 2.24 A Ipk). Then the base driver resistor is equal to: I 10− 3 ) out ton ) Ipk ESR Co RB + Vin(min) * Vsat(IC) * VRSC * VBE(Q2) IB ) I160 W + 13.5 * 0.8 * 0.3 * 1.0 (64 ) 5) 10− 3 + 165.2 W, use 160 W + 18 mV ) 5.9 mV ) 22.4 mV + 46.3 mV 9. The nominal output voltage is programmed by the R1, R2 divider. Note that with a negative output voltage, the inverting input of the comparator is referenced to ground. Therefore, the voltage at the junction of R1, R2 and the noninverting input must http://onsemi.com 17 AN920/D STEP UP/DOWN SWITCHING REGULATOR OPERATION When designing at the board level it sometimes becomes necessary to generate a constant output voltage that is less than that of the battery. The step−down circuit shown in Figure 16a will perform this function efficiently. However, as the battery discharges, its terminal voltage will eventually fall below the desired output, and in order to utilize the remaining battery energy the step−up circuit shown in Figure 16b will be required. +Vin Q1 +Vout L D1 Co + a. Step−Down Vout  Vin +Vin L General Applications Q2 By combining circuits a and b, a unique step−up/down configuration can be created (Figure 17) which still employs a simple inductor for the voltage transformation. Energy is stored in the inductor during the time that transistors Q1 and Q2 are in the “on” state. Upon turn−off, the energy is transferred to the output filter capacitor and load forward biasing diodes D1 and D2. Note that during ton this circuit is identical to the basic step−up, but during toff the output voltage is derived only from the inductor and is with respect to ground instead of Vin. This allows the output voltage to be set to any value, thus it may be less than, equal to, or greater than that of the input. Current limit protection cannot be employed in the basic step−up circuit. If the output is severely overloaded or shorted, L or D2 may be destroyed since they form a direct path from Vin to Vout. The step−up/down configuration allows the control circuit to implement current limiting because Q1 is now in series with Vout, as is in the step−down circuit. +Vout D2 Co + b. Step−Up Vout  Vin Figure 16. Basic Switching Regulator Configurations +Vin Q1 L D1 +Vout D2 Q2 Co + b. Step−Up/Down Vout   Vin Figure 17. Combined Configuration 1. Determine the ratio of switch conduction ton versus diode conduction toff time. Step−Up/Down Switching Regulator Design Example ton Vout ) VFD1 ) VFD2 + toff Vin(min) * VsatQ1 * VsatQ2 A complete step−up/down switching regulator design example is shown in Figure 18. This regulator was designed to operate from a standard 12 V battery pack with the following conditions: Vin = 7.5 to 14.5 V Vout = 10 V fmin = 50 kHz Iout = 120 mA Vripple(p−p) = 1% Vout or 100 mVp−p The following design procedure is provided so that the user can select proper component values for his specific converter application. + 10 ) 0.6 ) 0.6 7.5 * 0.8 * 0.8 + 1.9 2. The cycle time of the LC network is equal to ton(max) + toff. ton(max) ) toff + 1 fmin 1 50 103 + 20 ms per cycle + http://onsemi.com 18 AN920/D 3. Next calculate ton and toff from the ratio of ton/toff in #1 and the sum of ton(max) + toff in #2. toff + 6. A minimum value of inductance can now be calculated since the maximum on−time and peak switch current are known. ton(max) ) toff ton )1 t Lmin + off + 20 10− 6 1.9 ) 1 ǒ ton + 20 ms * 6.9 ms 4. The maximum on−time is set by selecting a value for CT. 10− 5 ton(max) 10− 5 (13.1 IȀpk(switch) + 10− 6) ǒ Use a standard 510 pF capacitor. 5. The peak switch current is: + 1.41 A Ǔ t Ipk(switch) + 2 Iout on ) 1 toff + 2 (120 * VsatQ2 ǒVin * VsatQ1 Ǔ ton(max) Lmin Ǔ + 14.5 * 0.8 * 0.8 13.1 120 10− 6 + 524 pF ǒ 10− 6 A 120 μH inductor was selected for Lmin. 7. A value for the current limit resistor, Rsc, can be determined by using the current limit level of Ipk(switch) when Vin = 14.5 V. + 13.1 ms + 4.0 Ǔ + 7.5 * 0.8 * 0.8 13.1 696 10− 3 + 111 mH + 6.9 ms CT + 4.0 VsatQ1 * VsatQ2 ǒVin(min) *Ipk(switch) Ǔ ton 10− 3) (1.9 ) 1) + 696 mA http://onsemi.com 19 10− 6 AN920/D Vout 10 V/120 mA D1 1N5818 RBE 300 D2 1N5818 120 μH Q1 MPSU51A Co 330 RB 150 8 1 S Q Q2 R 170 7 Ipk Rsc 0.22 Vin 7.5 to 14.5 V 6 + + OSC 2 CT VCC 3 + 100 Comp − 5 1.25 V Reference Regulator MC34063 GND CT 510 pF 4 R2 9.1 k R1 1.3 k Conditions Test Results Line Regulation Vin = 7.5 to 14.5 V, Iout = 120 mA Δ = 22 mV or ± 0.11% Load Regulation Vin = 12.6 V, Iout = 10 to 120 mA Δ = 3.0 mV or ± 0.015% Output Ripple Vin = 12.6 V, Iout = 120 mA Short Circuit Current Vin = 12.6 V, RL = 0.1 Ω Efficiency Vin = 7.5 to 14.5 V, Iout = 120 mA 95 mVp−p 1.54 A 74% Figure 18. Step−Up/Down Switching Regulator Design Example Rsc + Ideally this would satisfy the design goal, however, even a solid tantalum capacitor of this value will have a typical ESR (equivalent series resistance) of 0.3 Ω which will contribute an additional 209 mV of ripple. Also there is a ripple component due to the gain of the comparator equal to: 0.33 IȀpk(switch) + 0.33 1.41 + 0.23 W Use a standard 0.22 Ω resistor. 8. A minimum value for an ideal output filter capacitor is: Co [ [ Iout ǒVripple(p−p) Ǔ ton ǒ120 100 Ǔ 10− 3 13.1 10− 3 Vripple(p−p) + ǒVVout Ǔ 1.5 ref 10− 3 + 10 Ǔ 1.5 ǒ1.25 10− 3 + 12 mV 10− 6 The ripple components are not in phase, but can be assumed to be for a conservative design. From the above it becomes apparent that ESR is the dominant [ 15.7 mF http://onsemi.com 20 AN920/D DESIGN CONSIDERATIONS As previously stated, the design equations for Lmin were based upon the assumption that the switching regulator is operating on the onset of continuous conduction with a fixed input voltage, maximum output load current, and a minimum charge−current oscillator. Typically the oscillator charge−current will be greater than the specific minimum of 20 microamps, thus ton will be somewhat shorter and the actual LC operating frequency will be greater than predicted. Also note that the voltage drop developed across the current−limit resistor Rsc was not accounted for in the ton/toff and Lmin design formulas. This voltage drop must be considered when designing high current converters that operate with an input voltage of less than 5.0 V. When checking the initial switcher operation with an oscilloscope, there will be some concern of circuit instability due to the apparent random switching of the output. The oscilloscope will be difficult to synchronize. This is not a problem. It is a normal operating characteristic of this type of switching regulator and is caused by the asynchronous operation of the comparator to that of the oscillator. The oscilloscope may be synchronized by varying the input voltage or load current slightly from the design nominals. High frequency circuit layout techniques are imperative with switching regulators. To minimize EMI, all high current loops should be kept as short as possible using heavy copper runs. The low current signal and high current switch and output grounds should return on separate paths back to the input filter capacitor. The R1, R2 output voltage divider should be located as close to the IC as possible to eliminate any noise pick−up into the feedback loop. The circuit diagrams were purposely drawn in a manner to depict this. All circuits used molypermalloy power toroid cores for the magnetics where only the inductance value is given. The number of turns, wire and core size information is not given since no attempt was made to optimize their design. Inductor and transformer design information may be obtained from the magnetic core and assembly companies listed on the switching regulator component source table. In some circuit designs, mainly step−up and voltage−inverting, a ratio of ton/(ton + toff) greater than 0.857 may be required. This can be obtained by the addition of the ratio extender circuit shown in Figure 19. This circuit uses germanium components and is temperature sensitive. A negative temperature coefficient timing capacitor will help reduce this sensitivity. Figure 20 shows the output switch on and off time versus CT with and without the ratio extender circuit. Notice that without the circuit, the ratio of ton/(ton + toff) is limited to 0.857 only for values of CT greater than 2.0 nF. With the circuit, the ratio is variable depending upon the value chosen for CT since toff is now nearly a constant. Current limiting must be used on all step−up and voltage−inverting designs using the ratio extender circuit. This will allow the inductor time to reset between cycles of overcurrent during initial power up of the switcher. When factor in the selection of an output filter capacitor. A 330 μF with an ESR of 0.12 Ω was selected to satisfy this design example by the following: Vripple(p−p) * ǒ CoutǓ ton * ǒV out Ǔ 1.5 I ESR [ V 10− 3 Ref o Ipk(switch) 9. The nominal output voltage is programmed by the R1, R2 resistor divider. R2 + R1 + R1 out * 1Ǔ ǒVVRef 10 * 1Ǔ ǒ1.25 + 7 R1 If 1.3 k is chosen for R1, then R2 would be 9.1 k, both being standard resistor values. 10. Transistor Q1 is driven into saturation with a forced gain of approximately 20 at an input voltage of 7.5 V. The required base drive is: IB + + Ipk(switch) Bf 696 10− 3 20 + 35 mA The value for the base−emitter turn−off resistor RBE is determined by: RBE + 10 Bf Ipk(switch) 10 (20) 696 10− 3 + 287 W + A standard 300 Ω resistor was selected. The additional base current required due to RBE is: V IRBE + BEQ1 RBE + 0.8 300 + 3.0 mA The base drive resistor for Q1 is equal to: RB + Vin(min) * Vsat(driver) * VRSC * VBEQ1 IB ) IRBE + 7.5 * 0.8 * 0.15 * 0.8 (35 ) 3) 10− 3 + 151 W A standard 150 Ω resistor was used. The circuit performance data shows excellent line and load regulation. There is some loss in conversion efficiency over the basic step−up or step−down circuits due to the added switch transistor and diode “on” losses. However, this unique converter demonstrates that with a simple inductor, a step−up/down converter with current limiting can be constructed. http://onsemi.com 21 AN920/D ton−toff, Output Switch On−Off Time (μs) the output filter capacitor reaches its nominal voltage, the voltage feedback loop will control regulation. Vin = 5 V 8 1 S ton Q R 170 7 Ipk 6 + OSC 2 CT − 1.25 V Reference Regulator ton toff 10 toff 0 CT 2N524 4 ton Without Ratio Extender Circuit With Ratio Extender Circuit 0 1.0 10 CT, Oscillator Timing Capacitor (nF) Figure 20. Output Switch On−Off Time versus Oscillator Timing Capacitor 1N270 3 + Comp To Scope Comparator Noninverting Input = Vref Comparator Inverting Input = GND VCC = 5 V; Ipk(sense) = VCC TA = 25°C 100 100 VCC 10 5 toff 1000 ton toff Ratio Extender Circuit Figure 19. Output Switch On−Off Time Test Circuit http://onsemi.com 22 100 AN920/D APPLICATIONS SECTION Listed below is an index of all the converter circuits shown in this application note. They are categorized into three major groups based upon the main output configuration. Each of these circuits was constructed and tested, and a performance table is included. INDEX OF CONVERTER CIRCUITS Main Output Configuration Input V Output 1 V/mA Output 2 V/mA Output 3 V/mA Figure No. Step−Down μA78S40 Low Power with Minimum Components 24 5/50 − − 9 MC34063 Medium Power 36 12/750 − − 21 MC34063 Buffered Switch and Second Output 28 5.0/5000 12/300 − 22 μA78S40 Linear Pass from Main Output 33 24/500 15/50 − 23 μA78S40 Buffered Switch and Buffered Linear Pass from Main Output 28 15/3000 12/1000 − 24 μA78S40 Negative Input and Negative Output −28 −12/500 − − 25 μA78S40 Low Power with Minimum Components 9.0 28/50 − − 11 MC34063 Medium Power 12 36/225 − − 26 MC34063 High Voltage, Low Power 4.5 190/5.0 − − 27 μA78S40 High Voltage, Medium Power Photoflash 4.5 334/45 − − 28 μA78S40 Linear Pass from Main Output 2.5 9.0/100 6/30 − 29 μA78S40 Buffered Linear Pass from Main Output EE PROM Programmer 4.5 See Circuit − − 30 μA78S40 Buffered Switch and Buffered Linear Pass from Main Output 4.5 15/1000 12/500 −12/50 31 μA78S40 Dual Switcher, Step−Up and Step−Down with Buffered Switch 12 28/250 5.0/250 − 32 7.5 to 14.5 10/120 − − 18 Step−Up Step−Up/Down MC34063 Medium Power Step−Up/Down Voltage−Inverting MC34063 Low Power 5.0 −12/100 − − 33 μA78S40 Medium Power with Buffered Switch 15 −15/500 − − 15 μA78S40 High Voltage, High Power with Buffered Switch μA78S40 42 Watt Off−Line Flyback Switcher μA78S40 Tracking Regulator with Buffered Switch and Buffered Linear Pass from Input http://onsemi.com 23 28 −120/850 − − 34 115 Vac 5.0/4000 12/700 −12/700 35 15 −12/500 12/500 − 37 AN920/D 8 1 S Q R 170 7 Ipk 0.2 Vin 36 V 6 47 OSC 1N5819 CT VCC 3 + + Comp − 1.25 V Reference Regulator 5 1.74 k Test 2 GND 190 μH 470 pF 4 15 k 270 Conditions + Vout 12 V/750 mA Results Line Regulation Vin = 20 to 40 V, Iout = 750 mA Δ = 15 mV or ± 0.063% Load Regulation Vin = 36 V, Iout = 100 to 750 mA Δ = 40 mV or ± 0.17% Output Ripple Vin = 36 V, Iout = 750 mA Short Circuit Current Vin = 36 V, RL = 0.1 Ω 1.6 A Efficiency Vin = 36 V, Iout = 750 mA 89.5% 60 mVp−p A maximum power transfer of 9.0 watts is possible from an 8−pin dual−in−line package with Vin = 36 V and Vout = 12 V. Figure 21. Step−Down http://onsemi.com 24 AN920/D D45VH4 (1) MBR2540 (2) 22 51 8 1 S Q T R 0.036 100 Vin 28 V Ipk 6 2200 170 7 OSC CT 22,000 Comp − 1.25 V Reference Regulator 5 1N5819 330 pF GND 4 3.6 k 1.2 k + 3 + + 23.1 μH 2 VCC 1.4T + 470 (1) Heatsink, IERC HP3−T0127−CB (2) Heatsink, IERC UP−000−CB Vout1 5 V/5 A Vout2 12 V/300 m A Conditions Test Results Line Regulation Vout1 Vin = 20 to 30 V, Iout1 = 5.0 A, Iout2 = 300 mA Δ = 9.0 mV or ± 0.09% Load Regulation Vout1 Vin = 28 V, Iout1 = 1.0 to 5.0 A, Iout2 = 300 mA Δ = 20 mV or ± 0.2% Output Ripple Vout1 Vin = 28 V, Iout1 = 5.0 A, Iout2 = 300 mA Short Circuit Current Vout1 Vin = 28 V, RL = 0.1 Ω Line Regulation Vout2 Vin = 20 to 30 V, Iout1 = 5.0 A, Iout2 = 300 mA Δ = 72 mV or ± 0.3% Load Regulation Vout2 Vin = 20 V, Iout2 = 100 to 300 mA, Iout1 = 5.0 A Δ = 12 mV or ± 0.05% Output Ripple Vout2 Vin = 28 V, Iout1 = 5.0 A, Iout2 = 300 mA Short Circuit Current Vout2 Vin = 28 V, RL = 0.1 Ω Efficiency 60 mVp−p 11.4 A 25 mVp−p 11.25 A Vin = 28 V, Iout1 = 5.0 A, Iout2 = 300 mA 80% A second output can be easily derived by winding a secondary on the main output inductor and phasing it so that energy is delivered to Vout2 during toff. The second output power should not exceed 25% of the main output. The 100 Ω potentiometer is used to divide down the voltage across the 0.036 Ω resistor and thus fine tune the current limit. Figure 22. Step−Down with Buffered Switch and Second Output http://onsemi.com 25 AN920/D Vin = 33 V 33 18.2 k + 1.0 k 0.22 750 pF 9 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 13 VCC 7 6 1.8 k 5 4 3 2 1 Vout2 15 V/50 mA 22 k 0.1 130 μH 1N5819 100 + Vout1 24 V/500 mA 2.0 k Test Conditions Results Line Regulation Vout1 Vin = 30 to 36 V, Iout1 = 500 mA, Iout2 = 50 mA Δ = 30 mV or ± 0.63% Load Regulation Vout1 Vin = 33 V, Iout1 = 100 to 500 mA, Iout2 = 50 mA Δ = 70 mV or ± 0.15% Output Ripple Vout1 Vin = 33 V, Iout1 = 500 mA, Iout2 = 50 mA Short Circuit Current Vout1 Vin = 33 V, RL = 0.1 Ω Line Regulation Vout2 Vin = 30 to 36 V, Iout1 = 500 mA, Iout2 = 50 mA Δ = 20 mV or ± 0.067% Load Regulation Vout2 Vin = 33 V, Iout2 = 0 to 50 mA, Iout1 = 500 mA Δ = 60 mV or ± 0.2% Output Ripple Vout2 Vin = 33 V, Iout1 = 500 mA, Iout2 = 50 mA Short Circuit Current Vout2 Vin = 33 V, RL = 0.1 Ω 90 mA Vin = 33 V, Iout1 = 500 mA, Iout2 = 50 mA 88.2% Efficiency 80 mVp−p 2.5 A Figure 23. Step−Down with Linear Pass from Main Output http://onsemi.com 26 70 mVp−p AN920/D Vin = 28 to 36 V D45VH10 0.022 470 22 k 35 μH Vout1 15 V/3.0 mA * + MBR1540 * 100 2.0 k 2200 + 51 910 pF 9 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 13 VCC 7 6 5 4 3 2 1 820 TIP31 * Vout2 12 V/1.0 mA 0.1 8.2 k 963 *All devices mounted on one heatsink, extra #10 hole required for MBR2540, IERC HP3−T0127−4CB Conditions Test Results Line Regulation Vout1 Vin = 28 to 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A Δ = 13 mV or ± 0.043% Load Regulation Vout1 Vin = 36 V, Iout1 = 1.0 to 4.0 A, Iout2 = 1.0 A Δ = 21 mV or ± 0.07% Output Ripple Vout1 Vin = 36 V, Iout1 = 3.0 mA, Iout2 = 1.0 A Short Circuit Current Vout1 Vin = 36 V, RL = 0.1 Ω Line Regulation Vout2 Vin = 28 to 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A Δ = 2.0 mV or ± 0.008% Load Regulation Vout2 Vin = 36 V, Iout2 = 0 to 1.5 A Δ = 2.0 mV or ± 0.08% Output Ripple Vout2 Vin = 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A Short Circuit Current Vout2 Vin = 36 V, RL = 0.1 Ω 3.6 A Vin = 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A 78.5% Efficiency 120 mVp−p 12.6 A 25 mVp−p Figure 24. Step−Down with Buffered Switch and Buffered Linear Pass from Main Output http://onsemi.com 27 AN920/D Vin = −28 V 3.09 k 100 + 11.8 k 275 μH Vout −12 V/500 mA 470 9 10 11 GND CT OSC 12 − S Test 170 D1 + 20 k 16 Q Op Amp − 470 15 R + 7 10 k 14 470 Ipk Comp 1.25 V Ref 8 13 VCC 1N5819 + 820 pF 6 5 4 3 2 1 20 k 10 k −2.5 V Conditions Results Line Regulation Vin = −22 to −28 V, Iout = 500 mA Δ = 25 mV or ± 0.104% Load Regulation Vin = −28 V, Iout = 100 to 500 mA Δ = 10 mV or ± 0.042% Output Ripple Vin = −28 V, Iout = 500 mA 130 mVp−p Efficiency Vin = −28 V, Iout = 500 mA 85.5% In this step−down circuit, the output switch must be connected in series with the negative input, causing the internal 1.25 V reference to be with respect to −Vin. A second reference of −2.5 V with respect to ground is generated by the Op Amp. Note that the 10 k and 20 k resistors must be matched pairs for good line regulation and that no provision is made for output short−circuit protection. Figure 25. Step−Down with Negative Input and Negative Output http://onsemi.com 28 AN920/D 180 μH 7.75T T 1.25 V 1N5819 8 1 S + Q Vout 36 V/225 mA 100 R 170 7 Ipk 0.22 Vin 12 V 6 OSC CT VCC 3 + 470 Comp − 1.25 V Reference Regulator 5 2.7 k Test 2 GND 910 pF 4 75 k Conditions Results Line Regulation Vin = 11 to 15 V, Iout = 225 mA Δ = 20 mV or ± 0.028% Load Regulation Vin = 12 V, Iout = 50 to 225 mA Δ = 30 mV or ± 0.042% Output Ripple Vin = 12 V, Iout = 225 mA 100 mVp−p Efficiency Vin = 12 V, Iout = 225 mA 90.4% A maximum power transfer of 8.1 watts is possible with Vin = 12 V and Vout = 36 V. The high efficiency is partially due to the use of the tapped inductor. The tap point is set for a voltage differential of 1.25 V. The range of Vin is somewhat limited when using this method. Figure 26. Step−Up http://onsemi.com 29 AN920/D T1 + Lp = 140 μH 8 1N4936 Vout 190 V/5.0 mA To SCD 504 Display 1.0 1 S Q R 170 7 Ipk 0.24 Vin 4.5 to12 V 6 100 OSC CT VCC 3 + + Comp − 5 27 k 2 1.25 V Reference Regulator 680 pF 4 GND 4.7 M T1: Primary = 25 Turns #28 AWG Secondary = 260 Turns #40 AWG Core = Ferroxcube 1408P−L00−3CB Bobbin = Ferroxcube 1408PCB1 Gap = 0.003″ Spacer for a primary inductance of 140 μH. 10 k Test Conditions Results Line Regulation Vin = 4.5 to 12 V, Iout = 5.0 mA Δ = 2.3 V or ± 0.61% Load Regulation Vin = 5.0 V, Iout = 1.0 to 6.0 mA Δ = 1.4 V or ± 0.37% Output Ripple Vin = 5.0 V, Iout = 5.0 mA Short Circuit Current Vin = 5.0 V, RL = 0.1 Ω Efficiency Vin = 5.0 V, Iout = 5.0 mA 250 mVp−p 113 mA 68% This circuit was designed to power the ON Semiconductor Solid Ceramic Displays from a Vin of 4.5 to 12 V. The design calculations are based on a step−up converter with an input of 4.5 V and a 24 V output rated at 45 mA. The 24 V level is the maximum step−up allowed by the oscillator ratio of ton/(ton + toff). The 45 mA current level was chosen so that the transformer primary power level is about 10% greater than that required by the load. The maximum Vin of 12 V is determined by the sum of the flyback and leakage inductance voltages present at the collector of the output switch during turn−off must not exceed 40 V. Figure 27. High−Voltage, Low Power Step−Up for Solid Ceramic Display http://onsemi.com 30 AN920/D Vin = 4.5 to 6.0 V D45VH10 0.022 2200 * T1 + 27 Lp = 16.5 μH 5.1 1600 pF 10 11 GND CT OSC 12 14 15 16 − S Comp Q C1 500 + 10 0.033 170 Op Amp − G.E. FT−118 D1 + 6 18 k 22 M R + 7 MR817 Ipk 1.25 V Ref 8 13 VCC 5 4 3 2 1 1.8 M Shutter 9 TRAID PL−10 * Heatsink, IERC PB1−36CB 120 4.7 M 18 k Charging Indicator LED T1: Primary = 10 Turns #17 AWG Secondary = 130 Turns #30 AWG Core = Ferroxcube 2616P−L00−3C8 Bobbin = Ferroxcube 2616PCB1 Gap = 0.018″ Spacer for a Primary Inductance of 16.5 μH. With Vin of 6.0 V, this step−up converter will charge capacitor C1 from 0 to 334 V in 4.7 seconds. The switching operation will cease until C1 bleeds down to 323 V. The charging time between flashes is 4.0 seconds. The output current at 334 V is 45 mA. Figure 28. High−Voltage Step−Up with Buffered Switch for Photoflash Applications http://onsemi.com 31 AN920/D Vin = 2.5 V 470 62 k + 10 k 40 μH 0.22 10 11 GND CT OSC 12 − 14 15 S 16 Q 170 Op Amp D1 + 6 + R − 7 Vout1 9.0 V/100 mA Ipk + 8 13 VCC Comp 1.25 V Ref 330 27 910 pF 9 1N5819 5 4 3 2 1 8.2 k Vout2 6.0 V/30 mA 38.3 k 0.1 10 k Test Conditions Results Line Regulation Vout1 Vin = 2.5 to 3.5 V, Iout1 = 100 mA, Iout2 = 30 mA Δ = 20 mV or ± 0.11% Load Regulation Vout1 Vin = 2.5 V, Iout1 = 25 to 100 mA, Iout2 = 30 mA Δ = 20 mV or ± 0.11% Output Ripple Vout1 Vin = 2.5 V, Iout1 = 100 mA, Iout2 = 30 mA Line Regulation Vout2 Vin = 2.5 to 3.5 V, Iout1 = 100 mA, Iout2 = 30 mA Δ = 1.0 mV or ± 0.0083% Load Regulation Vout2 Vin = 2.5 V, Iout2 = 0 to 50 mA, Iout1 = 100 mA Δ = 1.0 mV or ± 0.0083% Output Ripple Vout2 Vin = 2.5 V, Iout1 = 100 mA, Iout2 = 30 mA Short Circuit Current Vout2 Vin = 2.5 V, RL = 0.1 Ω Efficiency 60 mVp−p 5.0 mVp−p 150 mA Vin = 3.0 V, Iout1 = 100 mA, Iout2 = 30 mA Figure 29. Step−Up with Linear Pass from Main Output http://onsemi.com 32 68.3% AN920/D Vin = 4.5 to 5.5 V 16.5 k ‘A’ + 47 70 μH 0.22 ‘B’ 13.7 k 294 k 68 820 pF 9 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 13 VCC 7 6 5 4 3 2 1 1.0 k 1.0 2N5089 + 470 57.6 k 470 TIP29 ‘X’ 16.5 k 0.058 WRITE TTL Input + 4.7 k VPP Output 10.2 k 47 k 3.4 k Voltage @ Switch Position WRITE Pins 1 & 5 X VPP A < 1.5 23.52 5.24 20.95 A > 2.25 23.52 1.28 5.12 B < 1.5 28.07 6.25 25.01 B > 2.25 28.07 1.28 5.12 NOTE: All values are in volts. Vref = 1.245 V. Contributed by Steve Hageman of Calex Mfg. Co. Inc. Used in conjunction with two transistors, the μA78S40 can generate the required VPP voltage of 21 V or 25 V needed to program and erase EEPROMs from a single 5.0 V supply. A step−up converter provides a selectable regulated voltage at Pins 1 and 5. This voltage is used to generate a second reference at point ‘X’ and to power the linear regulator consisting of the internal op amp and a TIP29 transistor. When the WRITE input is less than 1.5 V, the 2N5089 transistor is OFF, allowing the voltage at ‘X’ to rise exponentially with an approximate time constant of 600 μs as required by some EEPROMs. The linear regulator amplifies the voltage at ‘X’ by four, generating the required VPP output voltage for the byte−erase write cycle. When the WRITE input is greater than 2.25 V, the 2N5089 turns ON clamping point ‘X’ to the internal reference level of 1.245 V. The VPP output will not be at approximately 5.1 V or 4.0 (1.245 + Vsat 2N5089). The μA78AS40 reference can only source current, therefore a reference pre bias of 470 Ω is used. The VPP output is short−circuit protected and can supply a current of 100 mA at 21 V or 75 mA at 25 V over an input range of 4.5 to 5.5 V. Figure 30. Step−Up with Buffered Linear Pass from Main Output for Programming EEPROMs http://onsemi.com 33 AN920/D Vin = 4.5 to 5.5 V 6800 22 k + 2.0 k 0.022 8.8 μH 5.1 1200 pF 9 10 11 GND CT OSC 12 13 VCC 15 16 2N5824 2200 − S Q 170 Op Amp − D1 + 1N5818 MC79L12 ACP + 47 6 5 4 3 2 1 820 D44 VH1 (1) 27 1N5818 + 7 Vout1 15 V/1.0 mA R + 8 + Ipk Comp 1.25 V Ref 14 47 Vout3 −12 V/50 mA 0.1 TIP29 (2) 0.1 8.2 k 47 + Vout2 −12 V/50 mA (1) Heatsink, IERC LAT0127B5CB (2) Heatsink, IERC PB1−36CB 953 Conditions Test Results Line Regulation Vout1 Vin = 4.5 to 5.5 V Δ = 18 mV or ± 0.06% Load Regulation Vout1 Vin = 5.0 V, Iout1 = 0.25 to 1.0 A Δ = 25 mV or ± 0.083% Output Ripple Vout1 Vin = 5.0 V Line Regulation Vout2 Vin = 4.5 to 5.5 V Δ = 3.0 mV or ± 0.013% Load Regulation Vout2 Vin = 5.0 V, Iout2 = 100 to 500 mA Δ = 5.0 mV or ± 0.021% Output Ripple Vout2 Vin = 5.0 V Short Circuit Current Vout2 Vin = 5.0 V, RL = 0.1 Ω Line Regulation Vout3 Vin = 4.5 to 5.5 V Load Regulation Vout3 Vin = 5.0 V, Iout3 = 0 to 50 mA Output Ripple Vout3 Vin = 5.0 V Short Circuit Current Vout3 Vin = 5.0 V, RL = 0.1 Ω Efficiency NOTE: 75 mVp−p 20 mVp−p 2.7 A Δ = 2.0 mV or ± 0.008% Δ = 29 mV or ± 0.12% 15 mVp−p 130 mA Vin = 5.0 V 71.8% All outputs are at nominal load current unless otherwise noted. Figure 31. Step−Up with Buffered Switch and Buffered Linear Pass from Main Output http://onsemi.com 34 AN920/D Vin = 12 V 47 + 47 k 108 μH 0.24 2.2 k 1N5819 9 10 11 GND CT OSC 12 − 14 15 S 16 Q R 170 Op Amp − 6 10 k D1 + 7 5 4 3 2 1 100 0.1 Vout1 28 V/250 mA Ipk + 8 13 VCC Comp 1.25 V Ref 470 180 470 pF + MPSU51A 1.0 M 4.4 mH 470 1N5819 2200 + Vout2 5.0 V/250 mA 3.6 k 1.2 k Conditions Test Results Line Regulation Vout1 Vin = 9.0 to 15 V, Iout1 = 250 mA, Iout2 = 250 mA Δ = 30 mV or ± 0.054% Load Regulation Vout1 Vin = 12 V, Iout1 = 100 to 300 mA, Iout2 = 250 mA Δ = 20 mV or ± 0.036% Output Ripple Vout1 Vin = 12 V, Iout1 = 250 mA, Iout2 = 250 mA Short Circuit Current Vout1 Vin = 12 V, RL = 0.1 Ω Line Regulation Vout2 Vin = 9.0 to 15 V, Iout1 = 250 mA, Iout2 = 250 mA Δ = 4.0 mV or ± 0.04% Load Regulation Vout2 Vin = 12 V, Iout2 = 100 to 300 mA, Iout1 = 250 A Δ = 18 mV or ± 0.18% Output Ripple Vout2 Vin = 12 V, Iout1 = 250 mA, Iout2 = 250 mA 70 mVp−p Vin = 12 V, Iout1 = 250 mA, Iout2 = 250 mA 81.8% Efficiency 35 mVp−p 1.7 A This circuit shows a method of using the μA78S40 to construct two independent converters. Output 1 uses the typical step−up circuit configuration while Output 2 makes the use of the op amp connected with positive feedback to create a free running step−down converter. The op amp slew rate limits the maximum switching frequency at rated load to less than 2.0 kHz. Figure 32. Dual Switcher, Step−Up and Step−Down with Buffered Switch http://onsemi.com 35 AN920/D 8 1 S Q R 170 7 Ipk 0.24 Vin 4.5 to 6.0 V 100 6 OSC 2 88 μH CT VCC 3 + + Comp − 1.25 V Reference Regulator 5 R2 8.2 k Test GND R1 953 + 1300 pF 1N5819 4 |Vout| + 1.25 ǒ1 ) R2Ǔ R1 1000 Conditions + Vout −12 V/100 mA Results Line Regulation Vin = 4.5 to 5.0 V, Iout = 100 mA Δ = 2.0 mV or ± 0.008% Load Regulation Vin = 5.0 V, Iout = 10 to 100 mA Δ = 10 mV or ± 0.042% Output Ripple Vin = 5.0 V, Iout = 100 mA Short Circuit Current Vin = 5.0 V, RL = 0.1 Ω 1.4 A Efficiency Vin = 5.0 V, Iout = 100 mA 60% 35 mVp−p The above circuit shows a method of using the MC34063 to construct a low power voltage−inverting converter. Note that the integrated circuit ground, pin 4, is connected directly to the negative output, thus allowing the internally connected comparator and reference to function properly for output voltage control. With this configuration, the sum of Vin + Vout + VF must not exceed 40 V. The conversion efficiency is modest since the output switch is connected as a Darlington and its on−voltage is a large portion of the minimum operating input voltage. A 12% improvement can be realized with the addition of an external PNP saturated switch when connected in a similar manner to that shown in Figure 15. Figure 33. Low Power Voltage−Inverting http://onsemi.com 36 AN920/D Vin = 28 V Rsc 0.022 2N6438 * 4700 + 100 100 k 10 51 1050 1200 pF 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − MR822 D1 + 8 13 VCC 7 6 5 4 3 2 Vout −120 V/850 mA 1 + 9 1000 pF 560 200 μH Center Tapped *Heatsink IERC Nested Pair HP1−T03−CB HP3−T03−CB Test Conditions Results Line Regulation Vin = 24 to 28 V, Iout = 850 mA Δ = 100 mV or ± 0.042% Load Regulation Vin = 28 V, Iout = 100 to 850 mA Δ = 70 mV or ± 0.029% Output Ripple Vin = 28 V, Iout = 850 mA Short Circuit Current Vin = 28 V, RL = 0.1 Ω 6.4 A Efficiency Vin = 28 V, Iout = 850 mA 81.8% 450 mVp−p This high power voltage−inverting circuit makes use of a center tapped inductor to step−up the magnitude of the output. Without the tap, the output switch transistor would need a VCE breakdown greater than 148 V at the start of toff; the maximum rating of this device is 120 V. All calculations are done for the typical voltage−inverting converter with an input of 28 V and an output of −120 V. The inductor value will be 50 μH or 200 μH center tapped for the value of CT used. The 1000 pF capacitor is used to filter the spikes generated by the high switching current flowing through the wiring and Rsc inductance. Figure 34. High Power Voltage−Inverting with Buffered Switch used. Output regulation and isolation is achieved by the use of the TL431 as an output reference and comparator, and a 4N35 optocoupler. As the 5.0 V output reaches its nominal level, the TL431 will start to conduct current through the LED in the 4N35. This in turn will cause the optoreceiver transistor to turn on, raising the voltage at Pin 10 which will cause a reduction in percent on−time of the output switch. The peak drain current at 42 W output is 2.0 A. As the output loading is increased, the MPS6515 will activate the Ipk(sense) pin and shorten ton on a cycle−by−cycle basis. If an An economical 42 watt off−line flyback switcher is shown in Figure 35. In this circuit the μA78S40 is connected to operate as a fixed frequency pulse width modulator. The oscillator sawtooth waveform is connected to the noninverting input of the comparator and a preset voltage of 685 mV, derived from the reference is connected to the inverting input. The preset voltage reduces the maximum percent on−time of the output switch from a nominal of 85.7% to about 45%. The maximum must be less than 50% when an equal turns ratio of primary to clamp winding is http://onsemi.com 37 AN920/D output filter capacitor must have separate ground returns to the transformer as shown on the circuit diagram. A complete printed circuit board with component layout is shown in Figure 36. The μA78S40 may be used in any of the previously shown circuit designs as a fixed frequency pulse width modulator, however consideration must be given to the proper selection of the feedback loop elements in order to insure circuit stability. output is shorted, the Ipk(sense) circuit will cause CT to charge beyond the upper oscillator trip point and the oscillator frequency will decrease. This action will result in a lower average power dissipation for the output switching transistor. Each output has a series inductor and a second shunt filter capacitor forming a Pi filter. This is used to reduce the level of high frequency ripple and spikes. Care must be taken with the layout of grounds in the Pi filter network. Each input and T1 6 680 12 6 Fusible Resistor 100 1 1/2 4N35 + 1N4303 2 2200 20 Ω 470 20 A + 22 3.3 k 1.0 k + 1000 0.1 15 k 2.0 W + Vout1 5.0 V/4.5 A L1 MBR1635 10 11 11 3.3 k TL431 1N965A 5.0 V Return 1000 pF 1.0 k 9 10 11 GND 12 13 VCC CT Ipk OSC + − 9 9 4 170 6 5 4 10 3 2 L3 1 MTP 4N50 MPSA55 MPS6515 4 680 1000 5 + + ±12 V Return Vout3 −12 V/0.8 A * 5 6 10 7 470 pF 560 + 1000 D1 + 7 8 + Op Amp Vout2 12 V/0.8 A L2 MUR110 16 R − 8 15 S Q Comp 1.25 V Ref 14 1.0 k 1N4937 115 VAC ±20% 0.1 0.0047 UL/CSA 0.24 1.8 k T1 − Primary: Pins 4 and 6 = 72 Turns #24 AWG, Bifilar Wound Pins 5 and 6 = 72 Turns #26 AWG, Bifilar Wound Secondary 5.0 V: 6 Turns (two strands) #18 AWG Bifilar Wound Secondary 12 V: 14 Turns #23 AWG Bifilar Wound 1000 pF 3.9 k *Heatsink Thermalloy 6072B−MT T1 − Core and Bobbin: Coilcraft PT3995 Gap: 0.030″ Spacer in each leg for a primary inductance of 550 μH. Primary to primary leakage inductance must be less than 30 μH. L1 − Coilcraft Z7156: Remove one layer for final inductance of 4.5 mH. L2, L3 − Coilcraft Z7157: 25 μH at 1.0 A Figure 35. 42 Watt Off−Line Flyback Switcher with Primary Power Limiting http://onsemi.com 38 AN920/D Conditions Test Results Line Regulation Vout1 Vin = 92 to 138 Vac Δ = 1.0 mV or ± 0.01% Load Regulation Vout1 Vin = 115 Vac, Iout1 = 1.0 to 4.5 A Δ = 3.0 mV or ± 0.03% Output Ripple Vout1 Vin = 115 Vac Short Circuit Current Vout1 Vin = 115 Vac, RL = 0.1 Ω 40 mVp−p 19.2 A Line Regulation Vout2 or Vout3 Vin = 92 to 138 Vac Δ = 10 mV or ± 0.04% Load Regulation Vout2 or Vout3 Vin = 115 Vac, Iout2 or Iout3 = 0.25 to 0.8 A Δ = 384 mV or ± 1.6% Output Ripple Vout2 or Vout3 Vin = 115 Vac Short Circuit Current Vout2 or Vout3 Vin = 115 Vac, RL = 0.1 Ω 10.8 A Vin = 115 Vac 75.7% Efficiency NOTE: 80 mVp−p All outputs are at nominal load current unless otherwise noted. Figure 35. (continued) 42 Watt Off−Line Flyback Switcher with Primary Power Limiting http://onsemi.com 39 AN920/D Component Layout − Bottom View Printed Circuit Board Negative − Bottom View Figure 36. 42 Watt Off−Line http://onsemi.com 40 AN920/D Vin = 15 V MPSU51A 0.15 100 1N5822 * Vout1 −12 V/500 mA + 100 Vout2 Voltage Adj 36.1 μH + 2.0 k 12 k 1.5 k 100 270 180 pF 9 10 11 GND CT OSC 12 14 15 16 Ipk S Comp − Q R + 1.25 V Ref 170 Op Amp − D1 + 8 13 VCC 7 6 5 4 3 2 1 *Heatsink IERC PSC2−3 6.2 k MPSU01A * 12 k Vout2 12 V/500 mA 0.1 200 Tracking Adj 12 k Test Conditions Results Line Regulation Vout1 Vin = 14.5 to 18 V, Iout1 = 500 mA, Iout2 = 500 mA Δ = 10 mV or ± 0.042% Load Regulation Vout1 Vin = 15 V, Iout1 = 100 to 500 mA, Iout2 = 500 mA Δ = 2.0 mV or ± 0.008% Output Ripple Vout1 Vin = 15 V, Iout1 = 500 mA, Iout2 = 500 mA Line Regulation Vout2 Vin = 14.5 to 18 V, Iout1 = 500 mA, Iout2 = 500 mA Δ = 10 mV or ± 0.042% Load Regulation Vout2 Vin = 15 V, Iout2 = 100 to 500 mA, Iout1 = 500 A Δ = 5.0 mV or ± 0.021% Output Ripple Vout2 Vin = 15 V, Iout1 = 500 mA, Iout2 = 500 mA 140 mVp−p Vin = 15 V, Iout1 = 500 mA, Iout2 = 500 mA 77.2% Efficiency 125 mVp−p This tracking regulator provides a ±12 V output from a single 15 V input. The negative output is generated by a voltage−inverting converter while the positive is a linear pass regulator taken from the input. The ±12 V outputs are monitored by the op amp in a corrective fashion so that the voltage at the center of the divider is zero ± VIO. The op amp is connected as a unity gain inverter when |Vout1| = |Vout2|. Figure 37. Tracking Regulator, Voltage−Inverting with Buffered Switch and Buffered Linear Pass from Input http://onsemi.com 41 AN920/D SWITCHING REGULATOR COMPONENT SOURCES SUMMARY The goal of this application note is to convey the theory of operation of the MC34063 and μA78S40, and to show the derivation of the basic first order design equations. The circuits were chosen to explore a variety of cost effective and practical solutions in designing switching converters. Another major objective is to show the ease and simplicity in designing switching converters and to remove any mystical “black magic” fears. ON Semiconductor maintains a Linear and Discrete products applications staff that is dedicated to assisting customers with any design problems or questions. Capacitor Erie Technical Products P.O. Box 961 Erie, PA 16512 (814) 452−5611 Mallory Capacitor Co. P.O. Box 1284 Indianapolis, IN 46206 (317) 856−3731 United Chemi−Con 9801 W. Higgins Road Rosemont, IL 60018 (312) 696−2000 BIBLIOGRAPHY Steve Hageman, DC/dc Converter Powers EEPROMs, EDN, January 20, 1983. Design Manual for SMPS Power Transformers, Copyright 1982 by Pulse Engineering. Heatsinks IERC 135 W. Magnolia Blvd. Burbank, CA (213) 849−2481 HeatSink/Dissipator Products and Thermal Management Guide, Copyright 1980 by International Electronic Research Corporation. Linear and Interface Integrated Circuits Data Manual, Copyright 1988 by Motorola Inc. Thermalloy, Inc. 2021 W. Valley View Lane Dallas, Texas 75234 (214) 243−4321 Linear Ferrite Materials and Components Sixth Edition, by Ferroxcube Corporation. Linear/Switchmode Voltage Regulator Hanbook Theory and Practice, Copyright 1989 by Motorola Inc. Magnetic Assemblies Coilcraft, Inc. 1102 Silver Lake Rd. Cary, IL 60013 (312) 639−2361 Molypermalloy Powder Cores, Catalog MPP−303U, Copyright 1981 by Magnetics Inc. Motorola Power Data Book, Copyright 1989 by Motorola Inc. Pulse Engineering P.O. Box 12235 San Diego, CA 92112 (714) 279−5900 Motorola Rectifiers and Zener Diodes Data Book, Copyright 1988 by Motorola Inc. Structured Design of Switching Power Magnetics, AN−P100, by Coilcraft Inc. Magnetic Cores Ferroxcube 5083 Kings Highway Saugerties, NY 12477 (914) 246−2811 Switching and Linear Power Supply, Power Converter Design, by Abraham I. Pressman, Copyright 1977 by Hayden Book Company Inc. mA78S40 Switching Voltage Regulator, Application Note 370, Copyright 1982 by Fairchild Camera and Instruments Corporation. Magnetics, Inc. P.O. Box 391 Butler, PA 16001 (412) 282−8282 Switchmode Transformer Ferrite E−Core Packages, DS−P200, by Coilcraft Inc. Jim Lange, Tapped Inductor Improves Efficiency for Switching Regulator, ED 16, August 2, 1979. TDK Corporation of America 4709 Golf Rd., Suite 300 Skokie, IL 60076 (312) 679−8200 Voltage Regulator Handbook, Copyright 1978 by Fairchild Camera and Instruments Corporation. ON Semiconductor does not endorse or warrant the suppliers referenced. http://onsemi.com 42 AN920/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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