DATA SHEET
www.onsemi.com
Inverting Regulator - Buck,
Boost, Switching
MARKING
DIAGRAMS
8
3x063
ALYWA
G
1.5 A
MC34063A, MC33063A,
SC34063A, SC33063A,
NCV33063A
8
1
The MC34063A Series is a monolithic control circuit containing the
primary functions required for DC−to−DC converters. These devices
consist of an internal temperature compensated reference, comparator,
controlled duty cycle oscillator with an active current limit circuit,
driver and high current output switch. This series was specifically
designed to be incorporated in Step−Down and Step−Up and
Voltage−Inverting applications with a minimum number of external
components. Refer to Application Notes AN920A/D and AN954/D
for additional design information.
Features
•
•
•
•
•
•
•
•
•
Operation from 3.0 V to 40 V Input
Low Standby Current
Current Limiting
Output Switch Current to 1.5 A
Output Voltage Adjustable
Frequency Operation to 100 kHz
Precision 2% Reference
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
Drive 8
Collector
Ipk
Sense
1
8
3x063V
ALYWA
G
1
8
3x063AP1
AWL
YYWWG
PDIP−8
P, P1 SUFFIX
CASE 626
8
1
8
33063AVP
AWL
YYWWG
1
1
DFN8
CASE 488AF
1
x
A
L, WL
Y, YY
W, WW
G or G
33063
ALYWA
G
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Q2
S Q
ORDERING INFORMATION
Q1
R
7
Switch
Collector
SOIC−8
D SUFFIX
CASE 751
100
2
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Switch
Emitter
Ipk
Oscillator CT
6
VCC
3
Comparator
+
-
Timing
Capacitor
1.25 V
Reference
Regulator
Comparator 5
Inverting
Input
4
GND
(Bottom View)
This device contains 79 active transistors.
Figure 1. Representative Schematic Diagram
© Semiconductor Components Industries, LLC, 2016
August, 2021 − Rev. 25
1
Publication Order Number:
MC34063A/D
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
1
8
Driver
Collector
Switch
Emitter
2
7
Ipk Sense
Timing
Capacitor
3
6
VCC
GND
4
5
Comparator
Inverting
Input
Switch
Collector
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Switch Collector
Switch Emitter
Timing Capacitor
EP Flag
GND
(Top View)
(Top View)
Ç
Ç
Ç
Ç
Ç
Driver Collector
Ipk Sense
VCC
Comparator
Inverting Input
Figure 2. Pin Connections
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
40
Vdc
Comparator Input Voltage Range
VIR
−0.3 to + 40
Vdc
Switch Collector Voltage
VC(switch)
40
Vdc
Switch Emitter Voltage (VPin 1 = 40 V)
VE(switch)
40
Vdc
Switch Collector to Emitter Voltage
VCE(switch)
40
Vdc
Driver Collector Voltage
VC(driver)
40
Vdc
Driver Collector Current (Note 1)
IC(driver)
100
mA
ISW
1.5
A
PD
1.25
W
RqJA
115
°C/W
PD
625
mW
Thermal Resistance
RqJA
160
°C/W
Thermal Resistance
RqJC
45
°C/W
Switch Current
Power Dissipation and Thermal Characteristics
Plastic Package, P, P1 Suffix
TA = 25°C
Thermal Resistance
SOIC Package, D Suffix
TA = 25°C
DFN Package
TA = 25°C
PD
1.25
mW
RqJA
80
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature Range
TA
Thermal Resistance
MC34063A, SC34063A
°C
0 to +70
MC33063AV, NCV33063A
−40 to +125
MC33063A, SC33063A
−40 to + 85
Storage Temperature Range
Tstg
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum package power dissipation limits must be observed.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per MIL−STD−883, Method 3015.
Machine Model Method 400 V.
3. NCV prefix is for automotive and other applications requiring site and change control.
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2
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = Tlow to Thigh [Note 4], unless otherwise specified.)
Characteristics
Symbol
Min
Typ
Max
Unit
fosc
24
33
42
kHz
OSCILLATOR
Frequency (VPin 5 = 0 V, CT = 1.0 nF, TA = 25°C)
Charge Current (VCC = 5.0 V to 40 V, TA = 25°C)
Ichg
24
35
42
mA
Idischg
140
220
260
mA
Discharge to Charge Current Ratio (Pin 7 to VCC, TA = 25°C)
Idischg/Ichg
5.2
6.5
7.5
−
Current Limit Sense Voltage (Ichg = Idischg, TA = 25°C)
Vipk(sense)
250
300
350
mV
Saturation Voltage, Darlington Connection
( ISW = 1.0 A, Pins 1, 8 connected)
VCE(sat)
−
1.0
1.3
V
Saturation Voltage (Note 6)
(ISW = 1.0 A, RPin 8 = 82 W to VCC, Forced b ] 20)
VCE(sat)
−
0.45
0.7
V
hFE
50
75
−
−
IC(off)
−
0.01
100
mA
1.225
1.21
1.25
−
1.275
1.29
−
−
1.4
1.4
5.0
6.0
IIB
−
−20
−400
nA
ICC
−
−
4.0
mA
Discharge Current (VCC = 5.0 V to 40 V, TA = 25°C)
OUTPUT SWITCH (Note 5)
DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C)
Collector Off−State Current (VCE = 40 V)
COMPARATOR
Threshold Voltage
TA = 25°C
TA = Tlow to Thigh
Vth
Threshold Voltage Line Regulation (VCC = 3.0 V to 40 V)
MC33063, MC34063
MC33063V, NCV33063
Regline
Input Bias Current (Vin = 0 V)
V
mV
TOTAL DEVICE
Supply Current (VCC = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = VCC,
VPin 5 > Vth, Pin 2 = GND, remaining pins open)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Tlow = 0°C for MC34063, SC34063; − 40°C for MC33063, SC33063, MC33063V, NCV33063
Thigh = +70°C for MC34063, SC34063; + 85°C for MC33063, SC33063; +125°C for MC33063V, NCV33063
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
6. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents
(≥ 30 mA), it may take up to 2.0 ms for it to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is
magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a
non−Darlington configuration is used, the following output drive condition is recommended:
IC output
w 10
Forced b of output switch :
IC driver – 7.0 mA *
* The 100 W resistor in the emitter of the driver device requires about 7.0 mA before the output switch conducts.
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3
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
18
OFF TIME (ms)
14
140
12
120
ON TIME (ms)
10
100
8
80
6
OFF TIME (ms)
4
60
40
FREQUENCY (kHz)
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
20
200 mV/DIV
160
V OSC , OSCILLATOR VOLTAGE (V)
16
ON TIME (ms), FREQUENCY (kHz)
180
VCC = 5.0 V, Pin 7 = VCC
Pin 5 = GND, TA = 25°C
VCC = 5.0 V
Pin 7 = VCC
Pin 2 = GND
Pins 1, 5, 8 = Open
CT = 1.0 nF
TA = 25°C
0
5.0
10 ms/DIV
Figure 4. Timing Capacitor Waveform
Ct, TIMING CAPACITOR CAPACITANCE (nF)
Figure 3. Oscillator Frequency
VCE(sat), SATURATION VOLTAGE (V)
VCE(sat), SATURATION VOLTAGE (V)
1.8
1.7
1.6
1.5
1.4
1.3
VCC = 5.0 V
Pins 1, 7, 8 = VCC
Pins 3, 5 = GND
TA = 25°C
(See Note 7)
1.2
1.1
1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
IE, EMITTER CURRENT (A)
1.4
1.1
1.0
0.9
0.7
0.6
0.4
0.3
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
IC, COLLECTOR CURRENT(A)
1.4
1.6
Figure 6. Common Emitter Configuration Output
Switch Saturation Voltage versus
Collector Current
3.6
380
3.2
VCC = 5.0 V
Ichg = Idischg
I CC, SUPPLY CURRENT (mA)
VIPK(sense), CURRENT LIMIT SENSE VOLTAGE (V)
Forced b = 20
0.1
0
1.6
400
320
300
280
260
240
220
200
-55
VCC = 5.0 V
Pin 7 = VCC
Pins 2, 3, 5 = GND
TA = 25°C
(See Note 7)
0.5
Figure 5. Emitter Follower Configuration Output
Saturation Voltage versus Emitter Current
360
340
Darlington Connection
0.8
2.8
2.4
2.0
1.6
1.2
CT = 1.0 nF
Pin 7 = VCC
Pin 2 = GND
0.8
0.4
0
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
0
125
Figure 7. Current Limit Sense Voltage
versus Temperature
5.0
10
15
20
25
30
VCC, SUPPLY VOLTAGE (V)
35
Figure 8. Standby Supply Current versus
Supply Voltage
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
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4
40
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
170 mH
L
1
8
180
S Q
Q2
R
Q1
7
2
1N5819
Ipk
Rsc
0.22
Vin
12 V
OSC
6
+
CT
3
CT
VCC
100
+
-
Comp.
1.25 V
Ref
Reg
1500
pF
5
4
1.0 mH
R2
R1
Vout
28 V/175 mA
47 k
2.2 k
Vout
+
330
+
CO
100
Optional Filter
Test
Conditions
Results
Line Regulation
Vin = 8.0 V to 16 V, IO = 175 mA
30 mV = ±0.05%
Load Regulation
Vin = 12 V, IO = 75 mA to 175 mA
10 mV = ±0.017%
Output Ripple
Vin = 12 V, IO = 175 mA
400 mVpp
Efficiency
Vin = 12 V, IO = 175 mA
87.7%
Output Ripple With Optional Filter
Vin = 12 V, IO = 175 mA
40 mVpp
Figure 9. Step−Up Converter
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5
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
8
1
7
R
Vout
8
7
2
Rsc
Vin
1
Vout
2
Rsc
Vin
6
6
R ³ 0 for
constant Vin
Figure 10. External Current Boost Connections for IC Peak Greater than 1.5 A
9a. External NPN Switch
9b. External NPN Saturated Switch
(See Note 8)
8. If the output switch is driven into hard saturation (non−Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents
(≥ 30 mA), it may take up to 2.0 ms to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is magnified
at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a
non−Darlington configuration is used, the following output drive condition is recommended.
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6
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
1
8
S Q
Q2
Q1
R
7
2
Ipk
Rsc
0.33
Vin
25 V
OSC
6
100
+
CT
1N5819
3
L
CT
VCC
+
-
1.25 V
Ref
Reg
Comp.
220 mH
470
pF
5
4
3.6 k
R1
1.0 mH
Vout
5.0 V/500 mA
R2
+
1.2 k
470
+
CO
Vout
100
Optional Filter
Test
Conditions
Results
Line Regulation
Vin = 15 V to 25 V, IO = 500 mA
12 mV = ±0.12%
Load Regulation
Vin = 25 V, IO = 50 mA to 500 mA
3.0 mV = ±0.03%
Output Ripple
Vin = 25 V, IO = 500 mA
120 mVpp
Short Circuit Current
Vin = 25 V, RL = 0.1 W
1.1 A
Efficiency
Vin = 25 V, IO = 500 mA
83.7%
Output Ripple With Optional Filter
Vin = 25 V, IO = 500 mA
40 mVpp
Figure 11. Step−Down Converter
8
1
1
V
8
7
Vout
Rsc
Vin
7
2
2
Rsc
6
Vin
6
Figure 12. External Current Boost Connections for IC Peak Greater than 1.5 A
11a. External NPN Switch
11b. External PNP Saturated Switch
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7
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
1
8
S Q
Q2
R
Q1
7
2
Ipk
Rsc
0.24
OSC
6
Vin
4.5 V to 6.0 V
88 mH
L
CT
VCC
3
+
100
+
-
Comp.
+
1.25 V
Ref
Reg
1500
pF
1N5819
4
5
1.0 mH
R1
Vout
-12 V/100 mA
953
R2
1000 mf
8.2 k
+
Vout
CO
+
100
Optional Filter
Test
Conditions
Results
Line Regulation
Vin = 4.5 V to 6.0 V, IO = 100 mA
3.0 mV = ± 0.012%
Load Regulation
Vin = 5.0 V, IO = 10 mA to 100 mA
0.022 V = ± 0.09%
Output Ripple
Vin = 5.0 V, IO = 100 mA
500 mVpp
Short Circuit Current
Vin = 5.0 V, RL = 0.1 W
910 mA
Efficiency
Vin = 5.0 V, IO = 100 mA
62.2%
Output Ripple With Optional Filter
Vin = 5.0 V, IO = 100 mA
70 mVpp
Figure 13. Voltage Inverting Converter
8
1
1
Vout
8
7
2
7
Vout
Vin
2
3
6
Vin
3 +
6
+
4
4
Figure 14. External Current Boost Connections for IC Peak Greater than 1.5 A
13a. External NPN Switch
13b. External PNP Saturated Switch
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8
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Figure 15. Printed Circuit Board and Component Layout
(Circuits of Figures 9, 11, 13)
INDUCTOR DATA
Converter
Inductance (mH)
Turns/Wire
Step−Up
170
38 Turns of #22 AWG
Step−Down
220
48 Turns of #22 AWG
Voltage−Inverting
88
28 Turns of #22 AWG
All inductors are wound on Magnetics Inc. 55117 toroidal core.
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9
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Figure 16. Printed Circuit Board for DFN Device
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10
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
Calculation
Step−Up
ton/toff
V out ) V
V
F
in(min)
* V sat
in(min)
(ton + toff)
|V out| ) V
Ipk(switch)
2I
ǒ
10−5
out(max)
4.0 x
ǒ
Ǔ
t on
) 1
t
off
V
Ǔ
off
ton
) 1
t
off
(ton + toff) − toff
ton
* V sat)
in(min)
I
pk(switch)
9
F
* V sat
t on ) t
off
ton
) 1
t
off
2I
0.3/Ipk(switch)
(V
in
1
f
t on ) t
(ton + toff) − toff
4.0 x
V
1
f
off
ton
) 1
t
off
CT
CO
V out ) V
F
* V sat * V out
in(min)
t on ) t
ton
L(min)
V
Voltage−Inverting
1
f
toff
Rsc
* V
Step−Down
t
on(max)
ǒ
10−5
in(min)
I
I
I outt on
ripple(pp)
4.0 x 10−5 ton
ton
2I
out(max)
0.3/Ipk(switch)
(V
(ton + toff) − toff
* V sat * V out)
pk(switch)
Ǔ
t
(t
) t )
pk(switch) on
off
8V
ripple(pp)
on(max)
ǒ
out(max)
ǒ
Ǔ
t on
) 1
t
off
0.3/Ipk(switch)
(V
* V sat)
in(min)
I
pk(switch)
9
V
Ǔ
t
on(max)
I outt on
ripple(pp)
Vsat = Saturation voltage of the output switch.
VF = Forward voltage drop of the output rectifier.
The following power supply characteristics must be chosen:
Vin − Nominal input voltage.
Vout − Desired output voltage, |V out| + 1.25 1 ) R2
R1
Iout − Desired output current.
fmin − Minimum desired output switching frequency at the selected values of Vin and IO.
Vripple(pp) − Desired peak−to−peak output ripple voltage. In practice, the calculated capacitor value will need to be increased due to its
equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the
line and load regulation.
ǒ
Ǔ
NOTE: For further information refer to Application Note AN920A/D and AN954/D.
Figure 17. Design Formula Table
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11
MC34063A, MC33063A, SC34063A, SC33063A, NCV33063A
ORDERING INFORMATION
Package
Shipping†
MC33063ADG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SC33063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC33063AP1G
PDIP−8
(Pb−Free)
50 Units / Rail
MC33063AVDG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33063AVDR2G
SOIC−8
(Pb−Free)
NCV33063AVDR2G*
SOIC−8
(Pb−Free)
MC33063AVPG
PDIP−8
(Pb−Free)
50 Units / Rail
MC34063ADG
SOIC−8
(Pb−Free)
98 Units / Rail
MC34063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
SC34063ADR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC34063AP1G
PDIP−8
(Pb−Free)
50 Units / Rail
SC34063AP1G
PDIP−8
(Pb−Free)
50 Units / Rail
MC33063MNTXG
DFN8
(Pb−Free)
4000 Units / Tape & Reel
Device
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCV33063A: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and
change control.
SENSEFET is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
(A3)
A
A1
C
D2
ÇÇÇÇ
e
8X
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
E2
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
L
4
ÇÇÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
TOP VIEW
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS.
L
L
L1
NOTE 4
DETAIL A
DATE 15 JAN 2009
b
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.21
8X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.63
4.30 2.39
PACKAGE
OUTLINE
8X
0.35
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15232D
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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