DATA SHEET
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Single Supply 3.0 V to 44 V
Operational Amplifiers
8
1
MC34071,2,4,A
MC33071,2,4,A,
NCV33072,4,A
SOIC−8
D SUFFIX
CASE 751
WQFN10
MT SUFFIX
CASE 510AJ
Quality bipolar fabrication with innovative design concepts are
employed for the MC33071/72/74, MC34071/72/74, NCV33072/74A
series of monolithic operational amplifiers. This series of operational
amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/ms slew rate
and fast settling time without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common
mode input voltage range includes ground potential (VEE). With a
Darlington input stage, this series exhibits high input resistance, low
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output
voltage swing, provides high capacitance drive capability, excellent
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74, NCV33072/74,A series of
devices are available in standard or prime performance (A Suffix)
grades and are specified over the commercial, industrial/vehicular or
military temperature ranges. The complete series of single, dual and
quad operational amplifiers are available in plastic SOIC, QFN and
TSSOP surface mount packages.
SOIC−14
D SUFFIX
CASE 751A
14
1
14
1
TSSOP−14
DTB SUFFIX
CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of
this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 19 of this data sheet.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Bandwidth: 4.5 MHz
High Slew Rate: 13 V/ms
Fast Settling Time: 1.1 ms to 0.1%
Wide Single Supply Operation: 3.0 V to 44 V
Wide Input Common Mode Voltage Range: Includes Ground (VEE)
Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
Large Output Voltage Swing: −14.7 V to +14 V (with ±15 V
Supplies)
Large Capacitance Drive Capability: 0 pF to 10,000 pF
Low Total Harmonic Distortion: 0.02%
Excellent Phase Margin: 60°
Excellent Gain Margin: 12 dB
Output Short Circuit Protection
ESD Diodes/Clamps Provide Input Protection for Dual and Quad
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2014
October, 2021 − Rev. 24
1
Publication Order Number:
MC34071/D
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PIN CONNECTIONS
CASE 751A/CASE 948G
CASE 751
CASE 510AJ
VCC
Offset Null
1
2
Inputs
+
3
VEE
4
8
NC
7
VCC
Output 1
Inputs 1
6
Output
5
Offset Null
(Single, Top View)
2
Inputs 1
VEE
8
1
3
7
+
+
4
VCC
Output 2
Output 2
1
+
4
+
4
5
Inputs 2
Output 1
2
3
VCC
14
1
6
2
3
Inputs 4
12
8
Output 1
1
9
Output 2
NC
2
8
NC
7
In 2
6
In + 2
VEE
In 1
+ 10
9
7
10
13
11
+
-
Output 4
Inputs 3
In + 1
3
4
5
Output 3
VEE/GND
6
5
Inputs 2
(Quad, Top View)
(Top View)
(Dual, Top View)
VCC
Q3
Q4
Q1
Q7
Q17
Q2
R1
C1
R2
D2
Bias
-
Q6
Q5
Q8
Q9
Q11
Q10
Q18
R6
R7
Output
R8
Inputs
+
C2
D3
Q19
Base
Current
Cancellation
Q13
Q14
Q15
Q16
Q12
D1
R5
R3
Current
Limit
R4
VEE/GND
Offset Null
(MC33071, MC34071 only)
Figure 1. Representative Schematic Diagram
(Each Amplifier)
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2
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+44
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Input Voltage Range
VIR
(Note 1)
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
Sec
Supply Voltage (from VEE to VCC)
Operating Junction Temperature
TJ
+150
°C
Storage Temperature Range
Tstg
−60 to +150
°C
ESDHBM
ESDMM
2000
200
ESD Capability, Dual and Quad (Note 3)
Human Body Model
Machine Model
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Either or both input voltages should not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115)
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3
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground, unless otherwise noted. See Note 4 for
TA = Tlow to Thigh)
A Suffix
Characteristics
Symbol
Input Offset Voltage (RS = 100 W, VCM = 0 V, VO = 0 V)
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh
VIO
Average Temperature Coefficient of Input Offset
Voltage
RS = 10 W, VCM = 0 V, VO = 0 V,
TA = Tlow to Thigh
IIB
Input Offset Current (VCM = 0 V, VO = 0V)
TA = +25°C
TA = Tlow to Thigh
IIO
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh
VICR
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kW)
TA = +25°C
TA = Tlow to Thigh
AVOL
Output Voltage Swing (VID = ±1.0 V)
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kW, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 kW, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 2.0 kW,
TA = Tlow to Thigh
VOH
VCC = +5.0 V, VEE = 0 V, RL = 2.0 kW, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 kW, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 2.0 kW,
TA = Tlow to Thigh
VOL
Output Short Circuit Current (VID = 1.0 V, VO = 0 V,
TA = 25°C)
Source
Sink
Typ
Max
0.5
0.5
−
3.0
3.0
5.0
−
10
−
−
−
100
−
−
−
6.0
−
−
−
−
DVIO/DT
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = Tlow to Thigh
Min
Non−Suffix
Min
Typ
Max
1.0
1.5
−
5.0
5.0
7.0
−
10
−
500
700
−
−
100
−
500
700
50
300
−
−
6.0
−
75
300
Unit
mV
−
−
−
mV/°C
nA
nA
VEE to (VCC −1.8)
VEE to (VCC −2.2)
V
VEE to (VCC −1.8)
VEE to (VCC −2.2)
V/mV
50
25
100
−
−
−
25
20
100
−
−
−
3.7
13.6
13.4
4.0
14
−
−
−
−
3.7
13.6
13.4
4.0
14
−
−
−
−
0.1
−14.7
−
0.3
−14.3
−13.5
−
−
−
0.1
−14.7
−
0.3
−14.3
−13.5
V
−
−
−
ISC
V
mA
10
20
30
30
−
−
10
20
30
30
−
−
Common Mode Rejection
RS ≤ 10 kW, VCM = VICR, TA = 25°C
CMR
80
97
−
70
97
−
dB
Power Supply Rejection (RS = 100 W)
VCC/VEE = +16.5 V/−16.5 V to +13.5 V/−13.5 V,
TA = 25°C
PSR
80
97
−
70
97
−
dB
−
−
−
1.6
1.9
−
2.0
2.5
2.8
−
−
−
1.6
1.9
−
2.0
2.5
2.8
Power Supply Current (Per Amplifier, No Load)
VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°C
VCC = +15 V, VEE = −15 V, VO = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, VO = 0 V,
TA = Tlow to Thigh
ID
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Tlow = −40°C for MC33071,2,4,/A, NCV33074/A Thigh = +85°C for MC33071,2,4,/A, NCV33074/A
= 0°C for MC34071,2,4,/A
= +70°C for MC34071,2,4,/A
= −40°C for MC34072,4/V, NCV33072,4A
= +125°C for MC34072,4/V, NCV33072,4A, NCV34074V
Case 510AJ Tlow/Thigh guaranteed by product characterization.
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4
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.)
A Suffix
Characteristics
Symbol
Non−Suffix
Min
Typ
Max
Min
Typ
Max
8.0
−
10
13
−
−
8.0
−
10
13
−
−
−
−
1.1
2.2
−
−
−
−
1.1
2.2
−
−
GBW
3.5
4.5
−
3.5
4.5
−
MHz
BW
−
160
−
−
160
−
kHz
−
−
60
40
−
−
−
−
60
40
−
−
−
−
12
4.0
−
−
−
−
12
4.0
−
−
SR
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, CL = 500 pF)
AV = +1.0
AV = −1.0
Setting Time (10 V Step, AV = −1.0)
To 0.1% (+1/2 LSB of 9−Bits)
To 0.01% (+1/2 LSB of 12−Bits)
V/ms
ts
Gain Bandwidth Product (f = 100 kHz)
Power Bandwidth
AV = +1.0, RL = 2.0 kW, VO = 20 Vpp, THD = 5.0%
Unit
ms
Phase margin
RL = 2.0 kW
RL = 2.0 kW, CL = 300 pF
fm
Gain Margin
RL = 2.0 kW
RL = 2.0 kW, CL = 300 pF
Am
Equivalent Input Noise Voltage
RS = 100 W, f = 1.0 kHz
en
−
32
−
−
32
−
nV/ √ Hz
Equivalent Input Noise Current
f = 1.0 kHz
in
−
0.22
−
−
0.22
−
pA/ √ Hz
Differential Input Resistance
VCM = 0 V
Rin
−
150
−
−
150
−
MW
Differential Input Capacitance
VCM = 0 V
Cin
−
2.5
−
−
2.5
−
pF
THD
−
0.02
−
−
0.02
−
%
−
−
120
−
−
120
−
dB
|ZO|
−
30
−
−
30
−
W
Total Harmonic Distortion
AV = +10, RL = 2.0 kW, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
Channel Separation (f = 10 kHz)
Open Loop Output Impedance (f = 1.0 MHz)
Single Supply
Deg
dB
Split Supplies
VCC+|VEE|≤44 V
3.0 V to 44 V
VCC
VCC
VCC
2
1
VCC
1
3
2
2
3
3
VEE
4
6
+
1
5
4
10 k
4
VEE
7
-
VEE
Offset nulling range is approximately ± 80 mV with a 10 k
potentiometer (MC33071, MC34071 only).
VEE
Figure 2. Power Supply Configurations
Figure 3. Offset Null Circuit
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5
V IO INPUT OFFSET VOLTAGE (mV)
V,
2400
2000
1600
8 & 14 Pin Plastic Pkg
SOIC-14 Pkg
1200
800
400
2.0
0
-4.0
0
-55 -40 -20
0
20
40
60
80
100 120 140 160
-55
25
50
75
100
Figure 4. Maximum Power Dissipation versus
Temperature for Package Types
Figure 5. Input Offset Voltage versus
Temperature for Representative Units
VCC
VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V
VCC -1.6
VCC -2.4
VEE +0.01
VEE
-55
-25
0
25
50
75
100
125
125
1.3
VCC = +15 V
VEE = -15 V
VCM = 0
1.2
1.1
1.0
0.9
0.8
0.7
-55
-25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Common Mode Voltage
Range versus Temperature
Figure 7. Normalized Input Bias Current
versus Temperature
125
50
1.4
VO, OUTPUT VOLTAGE SWING (Vpp )
VCC = +15 V
VEE = -15 V
TA = 25°C
1.2
1.0
0.8
0.6
0
TA, AMBIENT TEMPERATURE (°C)
VCC -0.8
VEE
-25
TA, AMBIENT TEMPERATURE (°C)
VCC
I,
IB INPUT BIAS CURRENT (NORMALIZED)
VCC = +15 V
VEE = -15 V
VCM = 0
4.0
-2.0
SOIC-8 Pkg
V,
ICR INPUT COMMON MODE VOLTAGE RANGE (V)
I,
IB INPUT BIAS CURRENT (NORMALIZED)
P,
D MAXIMUM POWER DISSIPATION (mW)
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
RL Connected
to Ground TA = 25°C
40
30
RL = 10 k
RL = 2.0 k
20
10
0
-12
-8.0
-4.0
0
4.0
8.0
12
0
5.0
10
15
20
VIC, INPUT COMMON MODE VOLTAGE (V)
VCC, |VEE|, SUPPLY VOLTAGE (V)
Figure 8. Normalized Input Bias Current versus
Input Common Mode Voltage
Figure 9. Split Supply Output Voltage
Swing versus Supply Voltage
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6
25
VCC/VEE = +4.5 V/ -4.5 V to +22 V/ -22 V
Source
VCC -1.0
25
125
25
VEE +1.0
85
125
0
5.0
10
15
0.2
0.1
GND
0
100
20
1.0 k
10 k
RL, LOAD RESISTANCE TO GROUND (W)
Figure 10. Split Supply Output Saturation
versus Load Current
Figure 11. Single Supply Output Saturation
versus Load Resistance to Ground
60
VCC
-0.4
-0.8
2.0
VCC = +15 V
RL to VCC
TA = 25°C
1.0
GND
50
Sink
40
Source
30
20
VCC = +15 V
VEE = -15 V
RL ≤ 0.1 W
DVin = 1.0 V
10
0
100
1.0 k
10 k
-55
100 k
25
50
75
100
Figure 12. Single Supply Output Saturation
versus Load Resistance to VCC
Figure 13. Output Short Circuit Current
versus Temperature
20
AV = 1000
AV = 100
AV = 10
AV = 1.0
10
10 k
125
28
VCC = +15 V
VEE = -15 V
VCM = 0
VO = 0
DIO = ±0.5 mA
TA = 25°C
0
1.0 k
0
TA, AMBIENT TEMPERATURE (°C)
VO, OUTPUT VOLTAGE SWING (Vpp )
30
-25
RL, LOAD RESISTANCE TO VCC (W)
50
40
100 k
IL, LOAD CURRENT (± mA)
0
Z,
Ω
O OUTPUT IMPEDANCE ()
VCC = +15 V
RL = GND
TA = 25°C
VCC-4.0
VEE +2.0 Sink
VEE
VCC
VCC-2.0
−40
VCC -2.0
VCC
I,
SC OUTPUT CURRENT (mA)
Vsat , OUTPUT SATURATION VOLTAGE (V)
Vsat , OUTPUT SATURATION VOLTAGE (V)
VCC
Vsat , OUTPUT SATURATION VOLTAGE (V)
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
100
f, FREQUENCY (Hz)
1.0 M
20
16
12
8.0
4.0
0
3.0 k
10 M
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k
THD ≤ 1.0%
TA = 25°C
24
Figure 14. Output Impedance
versus Frequency
10 k
30 k
100 k
300 k
f, FREQUENCY (Hz)
1.0 M
Figure 15. Output Voltage Swing
versus Frequency
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3.0 M
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
THD, TOTAL HARMONIC DISTORTION (%)
AV = 1000
0.3
VCC = +15 V
VEE = -15 V
VO = 2.0 Vpp
RL = 2.0 k
TA = 25°C
0.2
AV = 100
0.1
AV = 10
AV = 1.0
0
100
1.0 k
10 k
108
2.0
AV = 100
1.0
AV = 10
AV = 1.0
0
4.0
20
Figure 17. Total Harmonic Distortion
versus Output Voltage Swing
100
VCC = +15 V
VEE = -15 V
VO= -10 V to +10 V
RL = 10 k
f ≤ 10Hz
0
80
Gain
60
Phase
Margin
= 60°
40
0
25
50
75
100
20
1.0
125
10
GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)
100
Gain
Margin = 12 dB
120
140
-10
1. Phase RL = 2.0 k
2. Phase RL = 2.0 k, CL = 300 pF
-20 3. Gain RL = 2.0 k
4. Gain RL = 2.0 k, CL = 300 pF
-30 VCC = +15 V
VEE = 15 V
VO = 0 VTA = 25°C
-40
1.0
2.0
3.0 5.0
7.0
3
160
180
4
2
10
180
100
1.0 k
10 k
100 k
1.0 M
10 M
100 M
Figure 19. Open Loop Voltage Gain and
Phase versus Frequency
Phase
Margin = 60°
0
135
f, FREQUENCY (Hz)
20
φ, EXCESS PHASE (DEGREES)
1
90
VCC = +15 V
VEE = -15 V
VO = 0 V
RL = 2.0 k
TA = 25°C
0
-25
45
Phase
Figure 18. Open Loop Voltage Gain
versus Temperature
A,
VOL OPEN LOOP VOLTAGE GAIN (dB)
16
Figure 16. Total Harmonic Distortion
versus Frequency
TA, AMBIENT TEMPERATURE (°C)
10
12
VO, OUTPUT VOLTAGE SWING (Vpp)
100
20
8.0
f, FREQUENCY (Hz)
104
96
-55
VCC = +15 V
VEE = -15 V
RL = 2.0 k
TA = 25°C
AV = 1000
0
116
112
3.0
100 k
A,
VOL OPEN LOOP VOLTAGE GAIN (dB)
A,
VOL OPEN LOOP VOLTAGE GAIN (dB)
10
4.0
φ, EXCESS PHASE (DEGREES)
THD, TOTAL HARMONIC DISTORTION (%)
0.4
30
1.15
VCC = +15 V
VEE = -15 V
RL = 2.0 k
1.1
1.05
1.0
0.95
0.9
0.85
-55
-25
0
25
50
75
100
f, FREQUENCY (MHz)
TA, AMBIENT TEMPERATURE (°C)
Figure 20. Open Loop Voltage Gain and
Phase versus Frequency
Figure 21. Normalized Gain Bandwidth
Product versus Temperature
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8
125
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
70
VCC = +15 V
VEE = -15 V
RL = 2.0 k
VO = -10 V to +10 V
TA = 25°C
80
60
φ m , PHASE MARGIN (DEGREES)
40
20
0
10
100
1.0 k
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k to R
VO = -10 V to +10 V
TA = 25°C
60
50
40
30
20
10
0
10 k
10
100
Figure 22. Percent Overshoot versus
Load Capacitance
Figure 23. Phase Margin versus
Load Capacitance
14
80
10
8.0
φ m , PHASE MARGIN (DEGREES)
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k to ∞
VO = -10 V to +10 V
TA = 25°C
12
A,
m GAIN MARGIN (dB)
10 k
CL, LOAD CAPACITANCE (pF)
CL, LOAD CAPACITANCE (pF)
6.0
4.0
2.0
0
10
100
1.0 k
CL = 10 pF
CL = 100 pF
60
40
CL = 1,000 pF
20
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k to ∞
VO = -10 V to +10 V
CL = 10,000 pF
0
10 k
-55
-25
0
25
50
75
100
125
CL, LOAD CAPACITANCE (pF)
TA, AMBIENT TEMPERATURE (°C)
Figure 24. Gain Margin versus Load Capacitance
Figure 25. Phase Margin versus Temperature
16
8.0
4.0
10
CL = 10 pF
VEE = -15 V
AV = +1.0
RL = 2.0 k to ∞
VO = -10 V to +10 V
A,
m GAIN MARGIN (dB)
12
70
12
VCC = +15 V
A,
m GAIN MARGIN (dB)
1.0 k
CL = 100 pF
CL = 10,000 pF
CL = 1,000 pF
8.0
R1
6.0
-25
0
25
50
75
100
125
50
-
VO
40
+
R2
4.0
30
VCC = +15 V
VEE = -15 V
RT = R1 + R2
AV = +100
VO = 0 V
TA = 25°C
2.0
0
0
-55
60
Gain
1.0
10
20
Phase
10
100
1.0 k
10 k
TA, AMBIENT TEMPERATURE (°C)
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 26. Gain Margin versus Temperature
Figure 27. Phase Margin and Gain Margin
versus Differential Source Resistance
www.onsemi.com
9
0
100 k
φ m , PHASE MARGIN (DEGREES)
PERCENT OVERSHOOT
100
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
Δ V,
O OUTPUT VOLTAGE SWING FROM 0 V (V)
1.1
1.05
1.0
0.95
10
0.9
0
-25
0
25
50
75
100
125
1.0 mV
5.0
Compensated
Uncompensated
0
1.0 mV
10 mV
1.0 mV
-10
0
0.5
1.0
1.5
3.0
Figure 28. Normalized Slew Rate
versus Temperature
Figure 29. Output Settling Time
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25°C
100
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25°C
0
Figure 31. Large Signal Transient Response
100
TA = 125°C
VCC = +15 V
VEE = -15 V
VCM = 0 V
DVCM = ±1.5 V
TA = 25°C
TA = -55°C
60
40
DVCM
ADM
20
DVCM
CMR = 20 Log
1.0
DVO
+
DVO
10
100
x ADM
1.0 k
3.5
1.0 ms/DIV
PSR, POWER SUPPLY REJECTION (dB)
CMR, COMMON MODE REJECTION (dB)
2.5
ts, SETTLING TIME (ms)
Figure 30. Small Signal Transient Response
0
0.1
2.0
TA, AMBIENT TEMPERATURE (°C)
2.0 ms/DIV
80
VCC = +15 V
VEE = -15 V
AV = -1.0
TA = 25°C
1.0 mV
10 mV
-5.0
0.85
-55
50 mV/DIV
VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 k
CL = 500 pF
5.0 V/DIV
SR, SLEW RATE (NORMALIZED)
1.15
10 k
100 k
1.0 M
10 M
VCC = +15 V
VEE = -15 V
TA = 25°C
80
DVCC
ADM
60
DVEE
40
(DVCC = +1.5 V)
DVO
+
+PSR = 20 Log
20
+PSR
DVO/ADM
DVCC
DVO/ADM
-PSR = 20 Log
-PSR
(DVEE = +1.5 V)
DVEE
0
0.1
1.0
10
100
1.0 k
10 k
100 k
1.0 M 10 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 32. Common Mode Rejection
versus Frequency
Figure 33. Power Supply Rejection
versus Frequency
www.onsemi.com
10
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
105
PSR, POWER SUPPLY REJECTION (dB)
TA = -55°C
8.0
7.0
TA = 25°C
6.0
TA = 125°C
5.0
Quad device
4.0
0
5.0
10
15
20
85
+PSR = 20 Log
75
DVCC
DVO/ADM
ADM
DVCC
DVO
+
-PSR = 20 Log
DVO/ADM
DVEE
DVEE
-55
-25
0
25
50
75
100
VCC, |VEE|, SUPPLY VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 34. Supply Current versus
Supply Voltage
Figure 35. Power Supply Rejection
versus Temperature
e,
n INPUT NOICE VOLTAGE ( nV √ Hz)
CHANNEL SEPARATION (dB)
+PSR (DVCC = +1.5 V)
65
VCC = +15 V
VEE = -15 V
TA = 25°C
80
VCC = +15 V
VEE = -15 V
95
25
120
100
-PSR (DVEE = +1.5 V)
60
40
20
0
2.8
70
VCC = +15 V
VEE = -15 V
VCM = 0
TA = 25°C
60
50
40
20
30
50
70
100
200
300
2.4
2.0
1.6
Voltage
30
1.2
Current
20
0.8
10
0.4
0
10
125
10
100
1.0 k
10 k
0
100 k
i,
n INPUT NOISE CURRENT (pA √ Hz )
I
CC , SUPPLY CURRENT (mA)
9.0
f, FREQUENCY (kHz)
f, FREQUENCY (kHz)
Figure 36. Channel Separation versus Frequency
Figure 37. Input Noise versus Frequency
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
Since the input common mode voltage range of this input
stage includes the VEE potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VEE and VCC supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from VEE through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D−to−A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
www.onsemi.com
11
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
Because the PNP output emitter−follower transistor has
been eliminated, the MC34071 series offers a 20 mA
minimum current sink capability, typically to an output
voltage of (VEE +1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for fast high current
switching applications.
In addition, the all NPN transistor output stage is
inherently fast, contributing to the bipolar amplifier’s high
gain bandwidth product and fast settling capability. The
associated high frequency low output impedance (30 W typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60° phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25°C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on the
die.
As with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input−output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for ±15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 2.0 kW of feedback
resistance, the MC34071 series can settle to within 1/2 LSB
of 8−bits in 1.0 ms, and within 1/2 LSB of 12−bits in 2.2 ms
for a 10 V step. In a inverting unity gain fast settling
configuration, the symmetrical slew rate is ±13 V/ms. In the
classic noninverting unity gain configuration, the output
positive slew rate is +10 V/ms, and the corresponding
negative slew rate will exceed the positive slew rate as a
function of the fall time of the input waveform.
Since the bipolar input device matching characteristics
are superior to that of JFETs, a low untrimmed maximum
offset voltage of 3.0 mV prime and 5.0 mV downgrade can
be economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kW load resistance can swing within 1.0 V of the
positive rail (VCC), and within 0.3 V of the negative rail
(VEE), providing a 28.7 Vpp swing from ±15 V supplies.
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, and VBE of the NPN pull up
transistor Q17, and the voltage drop associated with the short
circuit resistance, R7. The negative swing is limited by the
saturation voltage of the pull−down transistor Q16, the
voltage drop ILR6, and the voltage drop associated with
resistance R7, where IL is the sink load current. For small
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
millivolts of VEE. For large valued sink currents (>5.0 mA),
diode D3 clamps the voltage across R6, thus limiting the
negative swing to the saturation voltage of Q16, plus the
forward diode drop of D3 (≈VEE +1.0 V). Thus for a given
supply voltage, unprecedented peak−to−peak output voltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to VCC during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull up
capability.
www.onsemi.com
12
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
(Typical Single Supply Applications VCC = 5.0 V)
VCC
5.1 M
VO
0
3.7 Vpp
0
VCC
20 k
100 k
1.0 M
Cin
CO
+
VO
68 k
MC34071
36.6 mVpp
Cin
100 k
Vin
10 k
RL
-
VO
CO
10 k
RL
100 k
AV = 10 BW (-3.0 dB) = 450 kHz
BW (-3.0 dB) = 45 kHz
Figure 38. AC Coupled Noninverting Amplifier
Figure 39. AC Coupled Inverting Amplifier
VCC
4.75 Vpp
2.63 V
+
MC34071
10 k
Vin 370 mVpp
AV = 101
1.0 k
VO
3.7 Vpp
91 k
5.1 k
RL
5.1 k
2.5 V
+
VO
MC34071
100 k
0
-
0 to 10,000 pF
+
Vin
1.0 M
MC54/74XX
MC34071
Vin
Figure 40. DC Coupled Inverting Amplifier
Maximum Output Swing
C
0.047
R1
16 k
C
0.01
32 k
R
VO
VCC
0.4 VCC
Then:
R3 =
fo = 1.0 kHz
fo =
2.0 C
0.02
+
fo = 30 kHz
Ho = 10
Ho = 1.0
Given fo = Center Frequency
AO = Gain at Center Frequency
Choose Value fo, Q, Ao, C
16 k
2.0 R
MC34071
C
0.047
MC34071
+
R3
2.2 k
-
1.1 k
R2
5.6 k
VO
R
Vin
TTL Gate
Figure 41. Unity Gain Buffer TTL Driver
Vin
Vin ≥ 0.2 Vdc
Cable
AV = 10
BW (-3.0 dB) = 450 kHz
1
4pRC
Q
R3
R1 =
2Ho
pfoC
R2 =
R1 R3
4Q2R1-R3
For less than 10% error from operational amplifier
Qofo
GBW
< 0.1
where fo and GBW are expressed in Hz.
GBW = 4.5 MHz Typ.
2.0 C
0.02
Figure 43. Active Bandpass Filter
Figure 42. Active High−Q Notch Filter
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13
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
Vin
CF
2.0 V
RF
5.0 k
5.0 k
5.0 k
Vin
-
VO
10 k
+
10 k
t
2.0 k
RL
MC34071
10 k
VO
+
MC34071
VCC
1.0 V
VO
0.2 ms
Delay
4.0 V
Bit
Switches
13 V/ms
(R-2R) Ladder Network
25 V/ms
0.1
t
Delay
1.0 ms
Settling Time
1.0 ms (8-Bits, 1/2 LSB)
Figure 44. Low Voltage Fast D/A Converter
Figure 45. High Speed Low Voltage Comparator
VCC
“ON"
Vin < Vref
VCC
VCC
+
Vin
RL
MC34071
Vref
+
+
MC34071
MC34071
-
-
“ON"
Vin > Vref
RL
(A) PNP
Figure 46. LED Driver
(B) NPN
Figure 47. Transistor Driver
ILoad
RF
+
MC34071
VO
Ground Current
Sense Resistor
RS
-
ICell
MC34071
R1
R2
VO
+
VO = ILoad RS
1+
R1
R2
For VO > 0.1V
BW ( -3.0 dB) = GBW
VCell = 0 V
R2
R1+R2
VO = ICell RF
VO > 0.1 V
Figure 48. AC/DC Ground Current Monitor
Figure 49. Photovoltaic Cell Amplifier
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14
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
VO
Hysteresis
R2
Vref
VOH
R1
Iout
+
MC34071
VOL
-
Vin
Vin
Vin
VinL
VinL =
R1
(VOL-Vref)+Vref
R1+R2
VinH =
R1
(VOH-Vref)+Vref
R1+R2
VH =
R1
(VOH -VOL)
R1+R
MC34071
-
Vref
Iout =
Figure 50. Low Input Voltage Comparator
with Hysteresis
R1
+
VinH
R
Figure 51. High Compliance Voltage to
Sink Current Converter
R2
+Vref
R4
RF
- 1/2
R3
- 1/2
MC34072
MC34072
+V1
R
Vin±VIO
+
R
VO
R
-
+
R
R = DR
R2
R4
=
(Critical to CMRR)
R1
R3
R4
R4
V2-V1
VO = 1 +
R3
R3
For (V2 ≥ V1), V > 0
Figure 52. High Input Impedance
Differential Amplifier
+
VO = Vref
RF
DR < < R
RF > > R
DR RF
2R2
(VO ≥ 0.1 V)
Figure 53. Bridge Current Amplifier
fOSC ^
0.85
RC
+ IB
V
VP
0
t
-
Vin
+
VO
MC34071
+V2
VO = Vin (pk)
+
ISC
t
Base Charge
Removal
MC34071
Iout
RL
VP
10,000 pF
C
+ 1/2
MC34072
+
-
V+
±IB
100 k
100 k
Vin
R
MC34072
- 1/2
+
47 k
VP
Pulse Width
Control Group
VP
OSC
t
Figure 54. Low Voltage Peak Detector
Comparator
High Current
Output
Figure 55. High Frequency Pulse
Width Modulation
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15
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = ±15.0 V
C2
0.02
R1
560
C2
0.05
-
R2
5.6 k
R3
510
MC34071
C1
1.0
-
R2
1.1 k
MC34071
C1
0.44
R1
46.1 k
C1
1.0
fo = 1.0 kHz
Ho = 10
+
fo = 100 Hz
Ho = 20
+
Then: R1 =
Choose: fo, Ho, C1
Choose: fo, Ho, C2
Then: C1 = 2C2 (Ho+1)
R2 =
Ǹ2
R2
R1 =
Ho
R2
R3 =
Ho+1
4pfoC2
R2 =
C2 =
Figure 56. Second Order Low−Pass Active Filter
Ho+0.5
pfoC1 Ǹ2
Ǹ2
2pfoC1 (1/Ho+2)
C
Ho
Figure 57. Second Order High−Pass Active Filter
CF *
VO = 10 V
Step
RF
2.0 k
+
MC34071
MC34071
R1
VO
+
I
High Speed
DAC
Vin
ts = 1.0 ms
Uncompensated
RL
R2
to 1/2 LSB (8-Bits)
ts = 2.2 ms
Compensated
VO
to 1/2 LSB (12-Bits)
Vin
=
R2
BW (-3.0 dB) = GBW
R1
SR = 13 V/ms
*Optional Compensation
VO
-
R1
R1 +R2
SR = 13 V/ms
Figure 58. Fast Settling Inverter
Figure 59. Basic Inverting Amplifier
+
MC34071
VO
Vin
Vin
R2
+
MC34071
RL
VO
R1
VO
Vin
=
1+
R2
R1
BW (-3.0 dB) = GBW
BWp = 200 kHz
VO = 20 Vpp
SR = 10 V/ms
R1
R1 +R2
Figure 60. Basic Noninverting Amplifier
Figure 61. Unity Gain Buffer (AV = +1.0)
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16
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
+
R
R
MC34074
R
VO
MC34074
RE
+
R
-
R
Example:
Let: R = RE = 12 k
Then: AV = 3.0
BW = 1.5 MHz
MC34074
+
R
AV = 1 +2
R
RE
Figure 62. High Impedance Differential Amplifier
+VO
+
+
MC34074
100 k
-
10
+
RL
10
+10
MC34074
+
220 pF
100 k
-10
+
+
RL
+VO
-VO
∞
18.93
-18.78
10 k
5.0 k
18
15.4
-18
-15.4
+
MC34074
100 k
-
10
RL
10
-VO
Figure 63. Dual Voltage Doubler
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17
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
ORDERING INFORMATION
Op Amp
Function
Single
Device
MC34071DR2G
Operating
Temperature Range
TA = 0° to +70°C
MC33071DR2G
MC33071ADR2G
TA = −40° to +85°C
MC34072DR2G
MC34072ADR2G
Dual
SOIC−8
(Pb−Free)
2500 / Tape & Reel
SOIC−8
(Pb−Free)
WQFN10
(Pb−Free)
MC33072DR2G
SOIC−8
(Pb−Free)
TA = −40° to +85°C
MC34072VDR2G
NCV33072DR2G*
TA = −40° to +125°C
MC34074ADR2G
MC34074DR2G
TA = 0° to +70°C
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
MC33074DR2G
SOIC−14
(Pb−Free)
NCV33074DR2G*
SOIC−14
(Pb−Free)
MC33074ADR2G
SOIC−14
(Pb−Free)
NCV33074ADR2G*
TA = −40° to +85°C
SOIC−14
(Pb−Free)
MC33074DTBR2G
TSSOP−14
(Pb−Free)
MC33074ADTBR2G
TSSOP−14
(Pb−Free)
NCV33074ADTBR2G*
TSSOP−14
(Pb−Free)
MC34074VDR2G
SOIC−14
(Pb−Free)
NCV34074VDR2G*
TA = −40° to +125°C
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
TA = 0° to +70°C
Shipping†
SOIC−8
(Pb−Free)
MC34072AMTTBG
MC33072ADR2G
Quad
Package
SOIC−8
(Pb−Free)
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
3000 Units / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 Units / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAP
capable.
www.onsemi.com
18
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
MARKING DIAGRAMS
SOIC−8
D SUFFIX
CASE 751
8
8
3x071
ALYW
8
3x072
ALYW
1
1
8
8
3x071
ALYWA
1
1
34072
ALYWV
3x072
ALYWA
1
*applies to NCV33072DR2G
SOIC−14
D SUFFIX
CASE 751A
14
14
MC3x074DG
AWLYWW
1
TSSOP−14
DTB SUFFIX
CASE 948G
MC3x074ADG
AWLYWW
1
14
14
MC33
074
ALYW
MC34074VDG
AWLYWW
1
*applies to NCV34074VDR2G
14
1
WQFN10
MT SUFFIX
CASE 510AJ
4072
AAYW
x
= 3 or 4
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or = Pb−Free Package
(Note: Microdot may be in either location)
www.onsemi.com
19
14
MC33
074A
ALYW
1
NCV3
074A
ALYW
1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN10 2.6x2.6, 0.5P
CASE 510AJ−01
ISSUE A
SCALE 2:1
ÍÍÍ
ÍÍÍ
ÍÍÍ
D
L
A B
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
0.15 C
0.15 C
A3
DETAIL B
0.08 C
9X
MOLD CMPD
DETAIL B
A1
C
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ALTERNATE
CONSTRUCTIONS
A
NOTE 4
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
0.10 C
L
L1
PIN ONE
REFERENCE
DATE 27 MAR 2009
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
DETAIL A
5
L
4
XXXX
AAYW
G
6
1
9
XXXX
AA
Y
W
G
e
10
L2
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
2.60 BSC
2.60 BSC
0.50 BSC
0.45
0.55
0.00
0.15
0.55
0.65
10X
b
0.10 C A
0.05 C
BOTTOM VIEW
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
B
NOTE 3
SOLDERING FOOTPRINT*
2.90
1
10X
10X
0.50
PITCH
2.90
0.30
0.73
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON38696E
WQFN10 2.6X2.6, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
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