DATA SHEET
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Universal Voltage Monitors
MC34161, MC33161,
NCV33161
The MC34161/MC33161 are universal voltage monitors intended
for use in a wide variety of voltage sensing applications. These devices
offer the circuit designer an economical solution for positive and
negative voltage detection. The circuit consists of two comparator
channels each with hysteresis, a unique Mode Select Input for channel
programming, a pinned out 2.54 V reference, and two open collector
outputs capable of sinking in excess of 10 mA. Each comparator
channel can be configured as either inverting or noninverting by the
Mode Select Input. This allows over, under, and window detection of
positive and negative voltages. The minimum supply voltage needed
for these devices to be fully functional is 2.0 V for positive voltage
sensing and 4.0 V for negative voltage sensing.
Applications include direct monitoring of positive and negative
voltages used in appliance, automotive, consumer, and industrial
equipment.
Features
•
•
•
•
•
•
•
•
•
Unique Mode Select Input Allows Channel Programming
Over, Under, and Window Voltage Detection
Positive and Negative Voltage Detection
Fully Functional at 2.0 V for Positive Voltage Sensing and 4.0 V
for Negative Voltage Sensing
Pinned Out 2.54 V Reference with Current Limit Protection
Low Standby Current
Open Collector Outputs for Enhanced Device Flexibility
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
8
1
VS
7
+
+
1.27 V
+
3
+
+
-
MC3x161P
AWL
YYWWG
1
1
8
SOIC−8
D SUFFIX
CASE 751
1
3x161
ALYW
G
1
8
Micro8t
DM SUFFIX
CASE 846A
1
x161
AYW G
G
1
x
= 3 or 4
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Vref
1
8
VCC
Input 1
2
7
Mode Select
Input 2
3
6
Output 1
GND
4
5
Output 2
ORDERING INFORMATION
+
6
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
2.8 V
+
-
8
PDIP−8
P SUFFIX
CASE 626
(TOP VIEW)
2.54 V
Reference
2
MARKING
DIAGRAMS
+
5
0.6 V
1.27 V
4
This device contains
141 transistors.
Figure 1. Simplified Block Diagram
(Positive Voltage Window Detector Application)
© Semiconductor Components Industries, LLC, 2015
August, 2021 − Rev. 14
1
Publication Order Number:
MC34161/D
MC34161, MC33161, NCV33161
MAXIMUM RATINGS (Note 1)
Symbol
Value
Unit
Power Supply Input Voltage
Rating
VCC
40
V
Comparator Input Voltage Range
Vin
− 1.0 to +40
V
Comparator Output Sink Current (Pins 5 and 6) (Note 2)
ISink
20
mA
Comparator Output Voltage
Vout
40
V
PD
RqJA
800
100
mW
°C/W
PD
RqJA
450
178
mW
°C/W
RqJA
240
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature (Note 3)
MC34161
MC33161
NCV33161
TA
Storage Temperature Range
Tstg
Power Dissipation and Thermal Characteristics (Note 2)
P Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
D Suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
DM Suffix, Plastic Package, Case 846A
Thermal Resistance, Junction−to−Ambient
0 to +70
− 40 to +105
−40 to +125
− 55 to +150
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
2. Maximum package power dissipation must be observed.
Thigh = +70°C for MC34161
3. Tlow = 0°C for MC34161
−40°C for MC33161
+105°C for MC33161
−40°C for NCV33161
+125°C for NCV33161
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MC34161, MC33161, NCV33161
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, for typical values TA = 25°C, for min/max values TA is the operating ambient
temperature range that applies [Notes 4 and 5], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
Vth
1.245
1.235
1.27
−
1.295
1.295
V
COMPARATOR INPUTS
Threshold Voltage, Vin Increasing (TA = 25°C)
(TA = Tmin to Tmax)
Threshold Voltage Variation (VCC = 2.0 V to 40 V)
DVth
−
7.0
15
mV
Threshold Hysteresis, Vin Decreasing
VH
15
25
35
mV
Threshold Difference |Vth1 − Vth2|
VD
−
1.0
15
mV
VRTD
1.20
1.27
1.32
V
IIB
−
−
40
85
200
400
nA
Vth(CH 1)
Vth(CH 2)
Vref+0.15
0.3
Vref+0.23
0.63
Vref+0.30
0.9
V
Output Sink Saturation Voltage (ISink = 2.0 mA)
(ISink = 10 mA)
(ISink = 0.25 mA, VCC = 1.0 V)
VOL
−
−
−
0.05
0.22
0.02
0.3
0.6
0.2
V
Off−State Leakage Current (VOH = 40 V)
IOH
−
0
1.0
mA
Output Voltage (IO = 0 mA, TA = 25°C)
Vref
2.48
2.54
2.60
V
Load Regulation (IO = 0 mA to 2.0 mA)
Regload
−
0.6
15
mV
Line Regulation (VCC = 4.0 V to 40 V)
Regline
−
5.0
15
mV
DVref
2.45
−
2.60
V
ISC
−
8.5
30
mA
ICC
−
−
450
560
700
900
mA
VCC
2.0
4.0
−
−
40
40
V
Reference to Threshold Difference (Vref − Vin1), (Vref − Vin2)
Input Bias Current (Vin = 1.0 V)
(Vin = 1.5 V)
MODE SELECT INPUT
Mode Select Threshold Voltage (Figure 6)
Channel 1
Channel 2
COMPARATOR OUTPUTS
REFERENCE OUTPUT
Total Output Variation over Line, Load, and Temperature
Short Circuit Current
TOTAL DEVICE
Power Supply Current (VMode, Vin1, Vin2 = GND)
(VCC = 5.0 V)
(VCC = 40 V)
Operating Voltage Range (Positive Sensing)
(Negative Sensing)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = +70°C for MC34161
5. Tlow = 0°C for MC34161
−40°C for MC33161
+105°C for MC33161
−40°C for NCV33161
+125°C for NCV33161
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MC34161, MC33161, NCV33161
500
VCC = 5.0 V
RL = 10 k to VCC
5.0 TA = 25°C
IIB , INPUT BIAS CURRENT (nA)
Vout , OUTPUT VOLTAGE (V)
6.0
4.0
3.0
2.0
TA = 85°C
TA = 25°C
1.0
TA = -40°C
0
1.22
1.23
TA = 85°C
TA = 25°C
TA = -40°C
1.24
1.25
1.26
1.27
Vin, INPUT VOLTAGE (V)
1.28
VCC = 5.0 V
VMode = GND
TA = 25°C
400
300
200
100
0
1.29
0
t PHL, OUTPUT PROPAGATION DELAY TIME (ns)
Figure 2. Comparator Input Threshold Voltage
5.0
8.0
VCC = 5.0 V
TA = 25°C
1. VMode = GND, Output Falling
2. VMode = VCC, Output Rising
3. VMode = VCC, Output Falling
4. VMode = GND, Output Rising
Vout , OUTPUT VOLTAGE (V)
3000
2400
1800
1
2
1200
3
Undervoltage Detector
Programmed to trip at 4.5 V
R1 = 1.8 k, R2 = 4.7 k
RL = 10 k to VCC
Refer to Figure 17
6.0
4.0
2.0
TA = -40°C
TA = -25°C
TA = -85°C
4
0
2.0
4.0
6.0
8.0
0
10
4.0
6.0
8.0
Figure 4. Output Propagation Delay Time
versus Percent Overdrive
Figure 5. Output Voltage versus Supply Voltage
Channel 2 Threshold
Channel 1 Threshold
VCC = 5.0 V
RL = 10 k to VCC
4.0
3.0
2.0
TA = 85°C
TA = 25°C
TA = -40°C
1.0
0
0
2.0
VCC, SUPPLY VOLTAGE (V)
6.0
5.0
0
PERCENT OVERDRIVE (%)
I Mode , MODE SELECT INPUT CURRENT (μ A)
600
4.0
2.0
3.0
Vin, INPUT VOLTAGE (V)
Figure 3. Comparator Input Bias Current
versus Input Voltage
3600
Vout , CHANNEL OUTPUT VOLTAGE (V)
1.0
0.5
1.0
1.5
TA = -40°C
2.0
2.5
TA = 85°C
TA = 25°C
3.0
3.5
40
VCC = 5.0 V
TA = 25°C
35
30
25
20
15
10
5.0
0
0
VMode, MODE SELECT INPUT VOLTAGE (V)
Figure 6. Mode Select Thresholds
1.0
2.0
3.0
4.0
VMode, MODE SELECT INPUT VOLTAGE (V)
Figure 7. Mode Select Input Current
versus Input Voltage
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5.0
MC34161, MC33161, NCV33161
Vref , REFERENCE OUTPUT VOLTAGE (V)
Vref, REFERENCE VOLTAGE (V)
2.8
2.4
2.0
1.6
1.2
0.8
VMode = GND
TA = 25°C
0.4
0
0
10
20
30
VCC, SUPPLY VOLTAGE (V)
2.610
Vref Max = 2.60 V
2.578
2.546
Vref Typ = 2.54 V
2.514
VCC = 5.0 V
VMode = GND
2.482
Vref Min = 2.48 V
2.450
40
-55
0
TA = -40°C
-6.0
-8.0
TA = 25°C
VCC = 5.0 V
VMode = GND
TA = 85°C
-2.0
-4.0
-10
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Iref, REFERENCE SOURCE CURRENT (mA)
8.0
0.5
125
0.4
TA = 85°C
0.3
TA = 25°C
0.2
TA = -40°C
0.1
0
0
8.0
12
4.0
Iout, OUTPUT SINK CURRENT (mA)
16
Figure 11. Output Saturation Voltage
versus Output Sink Current
1.6
0.8
VMode = GND
Pins 2, 3 = 1.5 V
0.6
VMode = VCC
Pins 2, 3 =
GND
I CC , INPUT SUPPLY CURRENT (mA)
I CC , SUPPLY CURRENT (mA)
100
VCC = 5.0 V
VMode = GND
Figure 10. Reference Voltage Change
versus Source Current
VMode = Vref
Pin 1 = 1.5 V
Pin 2 = GND
0.4
0.2
ICC measured at Pin 8
TA = 25°C
0
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Reference Voltage
versus Ambient Temperature
Vout , OUTPUT SATURATION VOLTAGE (V)
Vref , REFERENCE VOLTAGE CHANGE (mV)
Figure 8. Reference Voltage
versus Supply Voltage
-25
0
10
20
30
VCC, SUPPLY VOLTAGE (V)
1.2
0.8
0
40
VCC = 5.0 V
VMode = GND
TA = 25°C
0.4
0
Figure 12. Supply Current versus
Supply Voltage
8.0
12
4.0
Iout, OUTPUT SINK CURRENT (mA)
Figure 13. Supply Current
versus Output Sink Current
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16
MC34161, MC33161, NCV33161
VCC
8
2.54V
Reference
Vref
1
Mode Select
Channel 1
7
+
+
Input 1
2
+
Output 1
2.8V
+
6
1.27V
Channel 2
+
+
Input 2
+
3
+
Output 2
0.6V
5
1.27V
4
GND
Figure 14. MC34161 Representative Block Diagram
Mode Select
Pin 7
Input 1
Pin 2
Output 1
Pin 6
Input 2
Pin 3
Output 2
Pin 5
GND
0
1
0
1
0
1
0
1
Channels 1 & 2: Noninverting
Vref
0
1
0
1
0
1
1
0
Channel 1: Noninverting
Channel 2: Inverting
VCC (>2.9 V)
0
1
1
0
0
1
1
0
Channels 1 & 2: Inverting
Figure 15. Truth Table
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Comments
MC34161, MC33161, NCV33161
FUNCTIONAL DESCRIPTION
Introduction
Reference
To be competitive in today’s electronic equipment market,
new circuits must be designed to increase system reliability
with minimal incremental cost. The circuit designer can take
a significant step toward attaining these goals by
implementing economical circuitry that continuously
monitors critical circuit voltages and provides a fault signal
in the event of an out−of−tolerance condition. The
MC34161, MC33161 series are universal voltage monitors
intended for use in a wide variety of voltage sensing
applications. The main objectives of this series was to
configure a device that can be used in as many voltage
sensing applications as possible while minimizing cost. The
flexibility objective is achieved by the utilization of a unique
Mode Select input that is used in conjunction with
traditional circuit building blocks. The cost objective is
achieved by processing the device on a standard Bipolar
Analog flow, and by limiting the package to eight pins. The
device consists of two comparator channels each with
hysteresis, a mode select input for channel programming, a
pinned out reference, and two open collector outputs. Each
comparator channel can be configured as either inverting or
noninverting by the Mode Select input. This allows a single
device to perform over, under, and window detection of
positive and negative voltages. A detailed description of
each section of the device is given below with the
representative block diagram shown in Figure 14.
The 2.54 V reference is pinned out to provide a means for
the input comparators to sense negative voltages, as well as
a means to program the Mode Select input for window
detection applications. The reference is capable of sourcing
in excess of 2.0 mA output current and has built−in short
circuit protection. The output voltage has a guaranteed
tolerance of ±2.4% at room temperature.
The 2.54 V reference is derived by gaining up the internal
1.27 V reference by a factor of two. With a power supply
voltage of 4.0 V, the 2.54 V reference is in full regulation,
allowing the device to accurately sense negative voltages.
Mode Select Circuit
The key feature that allows this device to be flexible is the
Mode Select input. This input allows the user to program
each of the channels for various types of voltage sensing
applications. Figure 15 shows that the Mode Select input has
three defined states. These states determine whether
Channel 1 and/or Channel 2 operate in the inverting or
noninverting mode. The Mode Select thresholds are shown
in Figure 6. The input circuitry forms a tristate switch with
thresholds at 0.63 V and Vref + 0.23 V. The mode select input
current is 10 mA when connected to the reference output, and
42 mA when connected to a VCC of 5.0 V, refer to Figure 7.
Output Stage
The output stage uses a positive feedback base boost
circuit for enhanced sink saturation, while maintaining a
relatively low device standby current. Figure 11 shows that
the sink saturation voltage is about 0.2 V at 8.0 mA over
temperature. By combining the low output saturation
characteristics with low voltage comparator operation, this
device is capable of sensing positive voltages at a VCC of
1.0 V. These characteristics are important in undervoltage
sensing applications where the output must stay in a low
state as VCC approaches ground. Figure 5 shows the Output
Voltage versus Supply Voltage in an undervoltage sensing
application. Note that as VCC drops below the programmed
4.5 V trip point, the output stays in a well defined active low
state until VCC drops below 1.0 V.
Input Comparators
The input comparators of each channel are identical, each
having an upper threshold voltage of 1.27 V ±2.0% with
25 mV of hysteresis. The hysteresis is provided to enhance
output switching by preventing oscillations as the
comparator thresholds are crossed. The comparators have an
input bias current of 60 nA at their threshold which
approximates a 21.2 MW resistor to ground. This high
impedance minimizes loading of the external voltage
divider for well defined trip points. For all positive voltage
sensing applications, both comparator channels are fully
functional at a VCC of 2.0 V. In order to provide enhanced
device ruggedness for hostile industrial environments,
additional circuitry was designed into the inputs to prevent
device latchup as well as to suppress electrostatic discharges
(ESD).
APPLICATIONS
Note that many of the voltage detection circuits are shown
with a dashed line output connection. This connection gives
the inverse function of the solid line connection. For
example, the solid line output connection of Figure 16 has
the LED ‘ON’ when input voltage VS is above trip voltage
V2, for overvoltage detection. The dashed line output
connection has the LED ‘ON’ when VS is below trip voltage
V2, for undervoltage detection.
The following circuit figures illustrate the flexibility of
this device. Included are voltage sensing applications for
over, under, and window detectors, as well as three unique
configurations. Many of the voltage detection circuits are
shown with the open collector outputs of each channel
connected together driving a light emitting diode (LED).
This ‘ORed’ connection is shown for ease of explanation
and it is only required for window detection applications.
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MC34161, MC33161, NCV33161
VCC
8
V2
Input VS
VHys
VS1
V1
R2
GND
Output
VCC
Voltage
Pins 5, 6 GND
VS2
R1
1
2.54V
Reference
7
+
2 +
LED `ON'
+
1.27V
+
R2
3 +
R1
+
1.27V
+
2.8V
+
0.6V
6
5
4
The above figure shows the MC34161 configured as a dual positive overvoltage detector. As the input voltage increases from ground, the LED will turn ‘ON’ when
VS1 or VS2 exceeds V2. With the dashed line output connection, the circuit becomes a dual positive undervoltage detector. As the input voltage decreases from
the peak towards ground, the LED will turn ‘ON’ when VS1 or VS2 falls below V1.
For known resistor values, the voltage trip points are:
ǒ
V 1 + (V th * V H)
R2
R1
Ǔ
)1
V 2 + V th
ǒ
For a specific trip voltage, the required resistor ratio is:
R2
R1
Ǔ
R2
)1
R1
+
V1
V th * V H
R2
*1
R1
+
V2
V th
*1
Figure 16. Dual Positive Overvoltage Detector
VCC
8
1
2.54V
Reference
7
+
V2
Input VS
VHys
VS1
V1
R2
GND
2 +
VS2
Output
VCC
Voltage
Pins 5, 6 GND
LED `ON'
R1
+
1.27V
+
R2
3 +
R1
+
1.27V
+
2.8V
+
0.6V
6
5
4
The above figure shows the MC34161 configured as a dual positive undervoltage detector. As the input voltage decreases towards ground, the LED will turn ‘ON’
when VS1 or VS2 falls below V1. With the dashed line output connection, the circuit becomes a dual positive overvoltage detector. As the input voltage increases
from ground, the LED will turn ‘ON’ when VS1 or VS2 exceeds V2.
For known resistor values, the voltage trip points are:
ǒ
V 1 + (V th * V H)
R2
R1
Ǔ
)1
V 2 + V th
ǒ
R2
R1
For a specific trip voltage, the required resistor ratio is:
Ǔ
R2
)1
R1
+
V1
V th * V H
*1
Figure 17. Dual Positive Undervoltage Detector
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R2
R1
+
V2
V th
*1
MC34161, MC33161, NCV33161
VCC
8
GND
R2
V1
Input -VS
7
R1
VHys
-VS1
V2
2 +
R2
R1
Output
VCC
Voltage
Pins 5, 6 GND
+
+
1.27V
+
-VS2
LED `ON'
2.54V
Reference
1
3 +
+
1.27V
+
2.8V
6
+
0.6V
5
4
The above figure shows the MC34161 configured as a dual negative overvoltage detector. As the input voltage increases from ground, the LED will turn ‘ON’ when
−VS1 or −VS2 exceeds V2. With the dashed line output connection, the circuit becomes a dual negative undervoltage detector. As the input voltage decreases from
the peak towards ground, the LED will turn ‘ON’ when −VS1 or −VS2 falls below V1.
For known resistor values, the voltage trip points are:
V1 +
R1
R2
(V th * Vref) ) V th
V2 +
R1
R2
For a specific trip voltage, the required resistor ratio is:
R1
(V th * VH * V ref) ) V th * V H
R2
+
V 1 * V th
R1
V th * V ref
R2
+
V 2 * V th ) V H
V th * V H * V ref
Figure 18. Dual Negative Overvoltage Detector
VCC
8
R2
GND
7
R1
V1
-VS1
VHys
Input -VS
V2
2 +
R2
R1
Output
VCC
Voltage
Pins 5, 6 GND
2.54V
Reference
1
+
+
1.27V
+
-VS2
3 +
LED `ON'
+
1.27V
+
2.8V
+
0.6V
6
5
4
The above figure shows the MC34161 configured as a dual negative undervoltage detector. As the input voltage decreases towards ground, the LED will turn ‘ON’
when −VS1 or −VS2 falls below V1. With the dashed line output connection, the circuit becomes a dual negative overvoltage detector. As the input voltage increases
from ground, the LED will turn ‘ON’ when −VS1 or −VS2 exceeds V2.
For known resistor values, the voltage trip points are:
V1 +
R1
R2
(V th * Vref) ) V th
V2 +
R1
R2
For a specific trip voltage, the required resistor ratio is:
R1
(V th * VH * V ref) ) V th * V H
R2
+
V 1 * V th
V th * V ref
Figure 19. Dual Negative Undervoltage Detector
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R1
R2
+
V 2 * V th ) V H
V th * V H * V ref
MC34161, MC33161, NCV33161
VCC
8
CH2
V4
V3
CH1
V2
V1
Input VS
VHys2
VS
VHys1
7
R3
+
2 +
GND
R2
VCC
Output
Voltage
Pins 5, 6
2.54V
Reference
1
`ON'
LED `OFF'
LED `ON'
`OFF'
+
LED `ON'
GND
+
1.27V
3 +
R1
+
1.27V
+
2.8V
6
+
0.6V
5
4
The above figure shows the MC34161 configured as a positive voltage window detector. This is accomplished by connecting channel 1 as an undervoltage detector,
and channel 2 as an overvoltage detector. When the input voltage VS falls out of the window established by V1 and V4, the LED will turn ‘ON’. As the input voltage
falls within the window, VS increasing from ground and exceeding V2, or VS decreasing from the peak towards ground and falling below V3, the LED will turn ‘OFF’.
With the dashed line output connection, the LED will turn ‘ON’ when the input voltage VS is within the window.
For known resistor values, the voltage trip points are:
ǒ
V 1 + (V th1 * V H1)
V 2 + V th1
ǒ
R3
R3
R1 ) R2
R1 ) R2
Ǔ
)1
Ǔ
)1
For a specific trip voltage, the required resistor ratio is:
ǒ
V 3 + (V th2 * V H2)
V 4 + V th2
ǒ
R2 ) R3
R2 ) R3
R1
R1
Ǔ
R2
)1
R1
Ǔ
R2
)1
R1
+
+
V 3(V th2 * V H2)
V 1(V th1 * V H1)
R3
*1
R1
V 4 x V th1
*1
V 2 x V th2
R3
R1
Figure 20. Positive Voltage Window Detector
+
+
V 3(V 1 * V th1 ) V H1)
V 1(V th2 * V H2)
V 4(V 2 * V th1)
V 2 x V th2
VCC
8
CH2
Input -VS
2.54V
Reference
1
GND
V1
VHys2
V2
CH1 V3
V4
7
R3
+
2 +
VHys1
R2
+
1.27V
+
Output
Voltage
Pins 5, 6
VCC
`ON'
LED `OFF'
LED `ON'
`OFF'
LED `ON'
GND
3 +
R1
+
1.27V
-VS
+
2.8V
+
0.6V
6
5
4
The above figure shows the MC34161 configured as a negative voltage window detector. When the input voltage −VS falls out of the window established by V1
and V4, the LED will turn ‘ON’. As the input voltage falls within the window, −VS increasing from ground and exceeding V2, or −VS decreasing from the peak towards
ground and falling below V3, the LED will turn ‘OFF’. With the dashed line output connection, the LED will turn ‘ON’ when the input voltage −VS is within the window.
For known resistor values, the voltage trip points are:
V1 +
V2 +
V3 +
V4 +
R 1(V th2 * V ref)
R2 ) R3
For a specific trip voltage, the required resistor ratio is:
R1
) V th2
R 1(V th2 * V H2 * V ref)
R2 ) R3
(R 1 ) R 2)(V th1 * V ref)
R3
R2 ) R3
R2 ) R3
R3
) Vth1
(R 1 ) R 2)(V th1 * V H1 * Vref)
R3
R1
) Vth2 * V H2
R1 ) R2
R3
) V th1 * V H1
R1 ) R2
+
+
+
+
Figure 21. Negative Voltage Window Detector
www.onsemi.com
10
V 1 * V th2
V th2 * V ref
V 2 * V th2 ) VH2
V th2 * V H2 * Vref
V th1 * V ref
V 3 * V th1
V th1 * V H1 * Vref
V 4 ) V H1 * Vth1
MC34161, MC33161, NCV33161
VCC
8
V4
Input VS2
1
GND
7
R4
Input -VS1
2.54V
Reference
VHys2
V3
-VS1
V1
V2
Output
VCC
Voltage
Pins 5, 6 GND
2 +
R3
VHys1
+
+
1.27V
+
R2
LED `ON'
VS2
3 +
R1
+
1.27V
+
2.8V
6
+
0.6V
5
4
The above figure shows the MC34161 configured as a positive and negative overvoltage detector. As the input voltage increases from ground, the LED will turn
‘ON’ when either −VS1 exceeds V2, or VS2 exceeds V4. With the dashed line output connection, the circuit becomes a positive and negative undervoltage detector.
As the input voltage decreases from the peak towards ground, the LED will turn ‘ON’ when either VS2 falls below V3, or −VS1 falls below V1.
For known resistor values, the voltage trip points are:
V1 +
V2 +
R3
R4
R3
R4
For a specific trip voltage, the required resistor ratio is:
ǒ
Ǔ
(V th1 * Vref) ) V th1
V 3 + (V th2 * V H2)
(V th1 * VH1 * V ref) ) V th1 * V H1
V 4 + V th2
ǒ
R2
R1
R2
R1
Ǔ
R3
)1
R4
R3
)1
R4
+
+
(V 1 * V th1)
R2
(V th1 * V ref)
R1
(V 2 * V th1 ) V H1)
R2
(V th1 * V H1 * V ref)
R1
+
+
V4
V th2
*1
V3
V th2 * V H2
*1
Figure 22. Positive and Negative Overvoltage Detector
VCC
8
V2
V1
Input VS1
2.54V
Reference
VHys1
1
GND
7
R4
V3
Input -VS2
VS1
VHys2
V4
+
2 +
R3
+
1.27V
R2
Output VCC
Voltage
Pins 5, 6 GND
LED `ON'
+
3 +
R1
+
1.27V
-VS2
+
2.8V
6
+
0.6V
5
4
The above figure shows the MC34161 configured as a positive and negative undervoltage detector. As the input voltage decreases toward ground, the LED will
turn ‘ON’ when either VS1 falls below V1, or −VS2 falls below V3. With the dashed line output connection, the circuit becomes a positive and negative overvoltage
detector. As the input voltage increases from the ground, the LED will turn ‘ON’ when either VS1 exceeds V2, or −VS1 exceeds V1.
For known resistor values, the voltage trip points are:
ǒ
Ǔ
V 1 + (V th1 * V H1)
V 2 + V th1
ǒ
R4
R3
)1
R4
R3
Ǔ
)1
V3 +
V4 +
R1
R2
R1
R2
For a specific trip voltage, the required resistor ratio is:
R4
(V th * Vref) ) V th2
R3
(V th * VH2 * V ref) ) V th2 * V H2
R4
R3
+
+
V2
V th1
V1
V th1 * V H1
Figure 23. Positive and Negative Undervoltage Detector
www.onsemi.com
11
R1
*1
R2
*1
R1
R2
+
+
V 4 ) V H2 * V th2
V th2 * V H2 * V ref
V 3 * V th2
V th2 * V ref
MC34161, MC33161, NCV33161
VCC
8
VHys
Input VS
1
VS
V1
7
R2
GND
Output
VCC
Voltage
Pins 5, 6 GND
+
+
1.27V
2 +
R1
RA
2.54V
Reference
V2
Osc `ON'
+
+
1.27V
3 +
Piezo
+
2.8V
6
+
0.6V
5
4
RB
CT
The above figure shows the MC34161 configured as an overvoltage detector with an audio alarm. Channel 1 monitors input voltage VS while channel 2 is connected
as a simple RC oscillator. As the input voltage increases from ground, the output of channel 1 allows the oscillator to turn ‘ON’ when VS exceeds V2.
For known resistor values, the voltage trip points are:
ǒ
V 1 + (V th * V H)
R2
R1
Ǔ
ǒ
For a specific trip voltage, the required resistor ratio is:
Ǔ
R
) 1 V 2 + V th 2 ) 1
R1
R2
R1
+
V1
V th * V H
R2
*1
R1
+
V2
V th
*1
Figure 24. Overvoltage Detector with Audio Alarm
VCC
8
Input VS
V2
V1
2.54V
Reference
1
VHys
7
GND
Output
Voltage
Pin 5
2 +
VS
VCC
GND
R2
3 +
R1
VCC
+
0.6V
+
tDLY
Output
Voltage
Pin 6
+
1.27V
+ +
2.8V
+
1.27V
R3
6
RDLY
5
Reset LED `ON'
GND
4
CDLY
The above figure shows the MC34161 configured as a microprocessor reset with a time delay. Channel 2 monitors input voltage VS while channel 1 performs the
time delay function. As the input voltage decreases towards ground, the output of channel 2 quickly discharges CDLY when VS falls below V1. As the input voltage
increases from ground, the output of channel 2 allows RDLY to charge CDLY when VS exceeds V2.
For known resistor values, the voltage trip points are:
ǒ
V 1 + (V th * V H)
R2
R1
Ǔ
)1
V 2 + V th
ǒ
R2
R1
For a specific trip voltage, the required resistor ratio is:
Ǔ
R2
)1
For known RDLY CDLY values, the reset time delay is:
R1
tDLY = RDLYCDLY In
+
V1
V th * V H
*1
1
Vth
1−
VCC
Figure 25. Microprocessor Reset with Time Delay
www.onsemi.com
12
R2
R1
+
V2
V th
*1
MC34161, MC33161, NCV33161
B+
MAC
228A6FP
220
250V
75k
+
220
250V
75k
MR506
T
Input
92 Vac to
276 Vac
+
8
3.0A
2.54V
Reference
1
10k
7
2
+
+
100k
+
1.27V
+
1.6M
3
+
1N
4742
+
10
10k
+
+
1.27V
47
+
2.8V
+
0.6V
1.2k
RTN
6
5
4
10k
3W
The above circuit shows the MC34161 configured as an automatic line voltage selector. The IC controls the triac, enabling the circuit to function
as a fullwave voltage doubler or a fullwave bridge. Channel 1 senses the negative half cycles of the AC line voltage. If the line voltage is less
than150 V, the circuit will switch from bridge mode to voltage doubling mode after a preset time delay. The delay is controlled by the 100 kW resistor
and the 10 mF capacitor. If the line voltage is greater than 150 V, the circuit will immediately return to fullwave bridge mode.
Figure 26. Automatic AC Line Voltage Selector
www.onsemi.com
13
MC34161, MC33161, NCV33161
470mH
Vin
12V
MPS750
330
+
8
2.54V
Reference
1
0.01
4.7k
1.6k
7
2
+
+
+
1.27V
+
3
+
+
1.27V
1N5819
470
1000
VO
5.0V/250mA
1.8k
0.01
+
2.8V
+
6
+
0.6V
5
47k
4
0.005
Figure 27. Step−Down Converter
Test
Conditions
Results
Line Regulation
Vin = 9.5 V to 24 V, IO = 250 mA
40 mV = ±0.1%
Load Regulation
Vin = 12 V, IO = 0.25 mA to 250 mA
2.0 mV = ±0.2%
Output Ripple
Vin = 12 V, IO = 250 mA
50 mVpp
Efficiency
Vin = 12 V, IO = 250 mA
87.8%
The above figure shows the MC34161 configured as a step−down converter. Channel 1 monitors the output voltage while Channel
2 performs the oscillator function. Upon initial powerup, the converters output voltage will be below nominal, and the output of Channel
1 will allow the oscillator to run. The external switch transistor will eventually pump−up the output capacitor until its voltage exceeds
the input threshold of Channel 1. The output of Channel 1 will then switch low and disable the oscillator. The oscillator will commence
operation when the output voltage falls below the lower threshold of Channel 1.
www.onsemi.com
14
MC34161, MC33161, NCV33161
ORDERING INFORMATION
Package
Shipping†
MC34161PG
PDIP−8
(Pb−Free)
50 Units / Rail
MC34161DG
SOIC−8
(Pb−Free)
Device
MC34161DR2G
98 Units / Rail
2500 / Tape & Reel
MC34161DMR2G
Micro8
(Pb−Free)
4000 / Tape & Reel
MC33161PG
PDIP−8
(Pb−Free)
50 Units / Rail
MC33161DG
MC33161DR2G
98 Units / Rail
SOIC−8
(Pb−Free)
NCV33161DR2G*
MC33161DMR2G
NCV33161DMR2G*
2500 / Tape & Reel
2500 / Tape & Reel
Micro8
(Pb−Free)
4000 / Tape & Reel
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control
Change Requirements; AEC−Q100 Qualified and PPAP Capable.
www.onsemi.com
15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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