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SN74CBTLV3257
SCDS040M – DECEMBER 1997 – REVISED JULY 2018
SN74CBTLV3257 Low-Voltage 4-Bit 1-of-2 FET Multiplexer/Demultiplexer
1 Features
3 Description
•
•
•
•
The SN74CBTLV3257 device is a 4-bit 1-of-2 highspeed FET multiplexer/demultiplexer. The low onstate resistance of the switch allows connections to
be made with minimal propagation delay.
1
•
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
2 Applications
•
•
•
•
Internet of Things
Wireless Headphones
Television Set
4-Bit Bus Multiplexing and Demultiplexing
The select (S) input controls the data flow. The FET
multiplexers/demultiplexers are disabled when the
output-enable (OE) input is high.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device
when it is powered down. The device has isolation
during power off.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74CBTLV3257DBQ SSOP (16)
4.90 mm × 3.90 mm
SN74CBTLV3257PW
TSSOP (16)
5.00 mm × 4.40 mm
SN74CBTLV3257DGV TVSOP (16)
3.60 mm × 4.40 mm
SN74CBTLV3257D
9.90 mm × 3.91 mm
SOIC (16)
SN74CBTLV3257RGY VQFN (16)
4.00 mm × 3.50 mm
SN74CBTLV3257RSV
2.60 mm × 1.80 mm
UQFN (16)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic (Each FET Switch)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CBTLV3257
SCDS040M – DECEMBER 1997 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (October 2016) to Revision M
Page
•
Changed the pin images appearance ................................................................................................................................... 3
•
Changed the Thermal Information table ................................................................................................................................ 5
Changes from Revision K (April 2015) to Revision L
Page
•
Added TSSOP (16) to Device Information table..................................................................................................................... 1
•
Added Junction temperature, TJ in Absolute Maximum Ratings ............................................................................................ 5
•
Changed wording in Detailed Design Procedure to clarify device operation ....................................................................... 10
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 12
Changes from Revision J (December 2012) to Revision K
Page
•
Removed Ordering Information table, see Mechanical, Packaging, and Orderable Information ........................................... 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
Changes from Revision I (October 2003) to Revision J
•
2
Page
Added QFN ordering info and package pinout ...................................................................................................................... 1
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SCDS040M – DECEMBER 1997 – REVISED JULY 2018
5 Pin Configuration and Functions
D, DBQ, DGV, and PW Package
16-Pin SOIC, SSOP, TVSOP, and TSSOP
(Top View)
S
VCC
RGY Package
16-Pin VQFN
(Top View)
VCC
1B1
2
15
OE
1B2
3
14
4B1
1A
4
13
4B2
2B1
5
12
4A
2B2
6
11
3B1
2A
7
10
3B2
GND
8
9
3A
16
1B1
2
15
OE
1B2
3
14
4B1
1A
4
13
4B2
Thermal
Pad
5
12
4A
2B2
6
11
3B1
2A
7
10
3B2
8
2B1
GND
Not to scale
9
16
3A
1
1
S
Not to scale
1B2
OE
VCC
14
1
13
S
15
16
1B1
RSV Package
16-Pin UQFN
(Top View)
12
4B1
2B1
3
10
4A
2B2
4
9
3B1
3B2
3A
GND
2A
8
4B2
7
11
6
2
5
1A
Not to scale
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Pin Functions
PIN
NAME
SOIC, SSOP, TVSOP,
TSSOP, VQFN
UQFN
I/O
DESCRIPTION
1A
4
2
I/O
Channel 1 out/in common
1B1
2
16
I/O
Channel 1 in/out 1
1B2
3
1
I/O
Channel 1 in/out 2
2A
7
5
I/O
Channel 2 out/in common
2B1
5
3
I/O
Channel 2 in/out 1
2B2
6
4
I/O
Channel 2 in/out 2
3A
9
7
I/O
Channel 3 out/in common
3B1
11
9
I/O
Channel 3 in/out 1
3B2
10
8
I/O
Channel 3 in/out 2
4A
12
10
I/O
Channel 4 out/in common
4B1
14
12
I/O
Channel 4 in/out 1
4B2
13
11
I/O
Channel 4 in/out 2
Ground
GND
8
6
—
OE
15
13
I
Output Enable, active low
S
1
15
I
Select
VCC
16
14
—
Power
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VI
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
(2)
–0.5
Input voltage
Continuous channel current
IIK
Input clamp current
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
VI/O < 0
–65
4.6
V
128
mA
–50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
VALUE
UNIT
2000
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
UNIT
2.3
3.6
V
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
–40
85
V
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or
Floating CMOS InputsSCBA004.
6.4 Thermal Information
SN74CBTLV3257
THERMAL METRIC
(1)
D
DBQ
DGV
PW
RGY
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
86.7
112.4
123.1
110.9
43.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.8
63.6
48.7
45.8
57.2
°C/W
RθJB
Junction-to-board thermal resistance
43.7
54.8
54.9
56.0
21.4
°C/W
ψJT
Junction-to-top characterization parameter
12.3
17.0
5.2
5.4
1.7
°C/W
ψJB
Junction to baord characterization parameter
43.5
54.4
54.3
55.4
21.5
°C/W
RθJC(botto
Junction-to-case (bottom) thermal resistance
-
-
-
-
9.7
°C/W
m
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
VCC = 3 V,
II = –18 mA
II
VCC = 3.6 V,
VI = VCC or GND
Ioff
VCC = 0,
VI or VO = 0 to 3.6 V
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
VCC = 3.6 V,
One input at 3 V,
Other inputs at VCC
or GND
∆ICC (2)
Ci
Cio(OFF)
Control
inputs
A port
B port
VI = 3 V or 0
MAX
VO = 3 V or 0,
OE = VCC
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 0
VI = 1.7 V
VI = 0
VCC = 3 V
VI = 2.4 V
UNIT
–1.2
V
±1
µA
15
µA
10
µA
300
µA
3
ron (3)
(1)
(2)
(3)
TYP (1)
pF
10.5
pF
5.5
II = 64 mA
5
8
II = 24 mA
5
8
II = 15 mA
27
40
II = 64 mA
5
7
II = 24 mA
5
7
II = 15 mA
10
15
Ω
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (See Figure 1)
PARAMETER
VCC = 2.5 ± 0.2 V
VCC = 3.3 V ± 0.3 V
FROM (INPUT)
TO (OUTPUT)
A or B (1)
B or A
S
A or B
1.8
6.1
1.8
5.3
S
A or B
1.7
6.1
1.7
5.3
ns
tdis
S
A or B
1
4.8
1
4.5
ns
ten
OE
A or B
1.9
5.6
2
5
ns
tdis
OE
A or B
1
5.5
1.6
5.5
ns
tpd
ten
(1)
6
MIN
MAX
MIN
0.15
MAX
0.25
UNIT
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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7 Parameter Measurement Information
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
CL
30 pF
50 pF
VCC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
LOAD CIRCUIT
V∆
0.15 V
0.3 V
RL
500 Ω
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC/2
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
0V
tPLZ
t
Output PZL
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
VCC
Output
Control
VCC/2
VCC
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CBTLV3257 device is a 4-bit 1-of-2 high-speed FET multiplexer and demultiplexer. The low ONstate resistance of the switch allows connections to be made with minimal propagation delay.
The select (S) input controls the data flow. The FET multiplexers and demultiplexers are disabled when the
output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation
during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
4
2
1A
1B1
SW
3
1B2
SW
7
5
2A
2B1
SW
6
2B2
SW
9
11
3A
3B1
SW
10
3B2
SW
14
12
4A
4B1
SW
13
SW
4B2
1
S
15
OE
8.3 Feature Description
The SN74CBTLV3257 features 5-Ω switch connection between ports, allowing for low signal loss across the
switch. Rail-to-rail switching on data I/O allows for full voltage swing outputs. Ioff supports partial-power-down
mode operation, protecting the chip from voltages at output ports when it is not powered on. Latch-up
performance exceeds 100 mA per JESD 78, Class II.
8.4 Device Functional Modes
Table 1 shows the functional modes of SN74CBTLV3257.
Table 1. Function Table
INPUTS
OE
8
S
FUNCTION
L
L
A port = B1 port
L
H
A port = B2 port
H
X
Disconnect
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74CBTLV3257 can be used to multiplex and demultiplex up to 4 channels simultaneously in a 2:1
configuration. The application shown here is a 4-bit bus being multiplexed between two devices. the OE and S
pins are used to control the chip from the bus controller. This is a very generic example, and could apply to many
situations. If an application requires less than 4 bits, be sure to tie the A side to either high or low on unused
channels.
9.2 Typical Application
VCC
SN74CBTLV3257
S
1A
16
1
4
RON
2
3
2A
Bus
Controller
7
RON
5
6
4
3A
9
RON
11
10
4A
12
RON
14
13
GND
8
15
VCC
1B1
0.1 PF
1B2
2B1
4
Device 1
2B2
3B1
3B2
4
4B1
Device 2
4B2
OE
Figure 2. Typical Application of the SN74CBTLV3257
9.2.1 Design Requirements
1. Recommended Input Conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Inputs and outputs are overvoltage tolerant slowing them to go as high as 4.6 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed ±128 mA per channel.
3. Frequency Selection Criterion:
– Maximum frequency tested is 200 MHz.
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Typical Application (continued)
– Added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout.
9.2.2 Detailed Design Procedure
The 4-bit bus is connected directly to the 1A, 2A, 3A, and 4A ports (known as the xA port) on the
SN74CBTLV3257, which essentially splits it into two busses, coming out of the xB1 and xB2 ports. When S is
high, xB2 is the active bus, and when S is low, xB1 is the active bus. This means that Device 2 is connected to
the bus controller when S is high, and Device 1 is connected to the bus controller when S is low. This setup is
especially useful when two devices are hard coded with the same address and only one bus is available. The OE
connection can be used to disconnect all devices from the bus controller if necessary.
The 0.1-µF capacitor on VCC is a decoupling capacitor and should be placed as close as possible to the device.
9.2.3 Application Curve
3
Voltage (V)
2
Input
Output
1
0
0
1
2
3
4
Time (ns)
5
C001
Figure 3. Propagation Delay (tpd) Simulation Result at VCC = 2.5 V
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
10
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11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 4 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 4. Trace Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74CBTLV3257PWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL257
74CBTLV3257PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL257
74CBTLV3257RGYRG4
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CL257
SN74CBTLV3257D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3257
SN74CBTLV3257DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CL257
SN74CBTLV3257DE4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3257
SN74CBTLV3257DGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL257
SN74CBTLV3257DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3257
SN74CBTLV3257DRE4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTLV3257
SN74CBTLV3257PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL257
SN74CBTLV3257PWE4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL257
SN74CBTLV3257PWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CL257
SN74CBTLV3257PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
CL257
SN74CBTLV3257RGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CL257
SN74CBTLV3257RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZTR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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