MC44608P100

MC44608 Few External Components Reliable and Flexible SMPS Controller General Features • • • • • Flexibility Duty Cycle Control Undervoltage Lockout with Hysteresis On Chip Oscillator Switching Frequency 40, 75, or 100 kHz Secondary Control with Few External Components • PIN CONNECTIONS AND MARKING DIAGRAM Demag 1 Isense 2 Control Input 3 8 4 Vi 7 6 VCC 5 Driver AWL = Manufacturing Code YYWW = Date Code ORDERING INFORMATION Device Low Power Mode Lossless Startup Low dV/dT for Low EMI Radiations December, 2003 − Rev. 6 PDIP−8 P SUFFIX CASE 626 (Top View) • Pulsed Mode Techniques for a Very High Efficiency  Semiconductor Components Industries, LLC, 2003 1 GND Maximum Duty Cycle Limitation Cycle by Cycle Current Limitation Demagnetization (Zero Current Detection) Protection “Over VCC Protection” Against Open Loop Programmable Low Inertia Over Voltage Protection Against Open Loop Internal Thermal Protection SMPS Controller • • 8 (Top View) Protections • • • • • http://onsemi.com 44608Pxxx AWL YYWW The MC44608 is a high performance voltage mode controller designed for off−line converters. This high voltage circuit that integrates the start−up current source and the oscillator capacitor, requires few external components while offering a high flexibility and reliability. The device also features a very high efficiency stand−by management consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand−by power consumption to approximately 1.0 W while delivering 300 mW in a 150 W SMPS. • Integrated Start−Up Current Source • Lossless Off−Line Start−Up • Direct Off−Line Operation • Fast Start−Up 1 Switching Frequency Package Shipping MC44608P40 40 kHz Plastic DIP−8 50/Rail MC44608P75 75 kHz Plastic DIP−8 50/Rail MC44608P100 100 kHz Plastic DIP−8 50/Rail Publication Order Number: MC44608/D MC44608 Demag Vi 1 DMG + − 8 UVLO2 50 mV /20 mV >24 A 9 mA >120  A Start−up Source Latched off Phase Demag Logic 1 Start−up Phase Output Start−up Phase 200  A Switching Phase 0 Switching Phase Latched off Phase & Stand−by & OSC Enable S1 Stand−by Management OC NOC Leading Edge Blanking Output 2 Isense + − & & 5 Driver 4 GND VPWM + CS − 1V Buffer Thermal S Shutdown PWM Latch R Q & PWM V CC OUT Disable DMG Clock OSC 6 OVP UVLO1 UVLO2 2 S Start−up Phase V CC Management 4 kHz Filter Latched off Phase & Stand−by S2 S3 Regulation Block Switching Phase 3 Control Input Figure 1. Representative Block Diagram MAXIMUM RATINGS Rating Symbol Value Unit Total Power Supply Current ICC 30 mA Output Supply Voltage with Respect to Ground VCC 16 V Vinputs −1.0 to +16 V Line Voltage Absolute Rating Vi 500 V Recommended Line Voltage Operating Condition Vi 400 V PD RJA 600 100 mW °C/W Operating Junction Temperature TJ 150 °C Operating Ambient Temperature TA −25 to +85 °C All Inputs except Vi Power Dissipation and Thermal Characteristics Maximum Power Dissipation at TA = 85°C Thermal Resistance, Junction−to−Air http://onsemi.com 2 MC44608 ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Typ Max Unit ROL ROH 5.0 − 8.5 15 15 − Output Voltage Rise Time (from 3.0 V up to 9.0 V) (Note 1) tr − 50 − ns Output Voltage Falling Edge Slew−Rate (from 9.0 V down to 3.0 V) (Note 1) tf − 50 − ns Duty Cycle @ Ipin3 = 2.5 mA d2mA − − 2.0 % Duty Cycle @ Ipin3 = 1.0 mA d1mA 36 43 48 % OUTPUT SECTION
Output Resistor Sink Resistance Source Resistance CONTROL INPUT SECTION Control Input Clamp Voltage (Switching Phase) @ Ipin3 = −1.0 mA 4.75 5.0 5.25 V Latched Phase Control Input Voltage (Stand−by) @ Ipin3 = +500 A VLP−stby 3.4 3.9 4.3 V Latched Phase Control Input Voltage (Stand−by) @ Ipin3 = +1.0 mA VLP−stby 2.4 3.0 3.7 V VCS−th 0.95 1.0 1.05 V IB−cs −1.8 − 1.8 A ICS−stby 180 200 220 A CURRENT SENSE SECTION Maximum Current Sense Input Threshold Input Bias Current Stand−By Current Sense Input Current Start−up Phase Current Sense Input Current Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3.0 V) ICS−stup 180 200 220 A TPLH(In/Out) − 220 − ns Leading Edge Blanking Duration MC44608P40 TLEB − 480 − ns Leading Edge Blanking Duration MC44608P75 TLEB − 250 − ns Leading Edge Blanking Duration MC44608P100 TLEB − 200 − ns Leading Edge Blanking + Propagation Delay MC44608P40 TDLY 500 680 900 ns Leading Edge Blanking + Propagation Delay MC44608P75 TDLY 370 470 570 ns Leading Edge Blanking + Propagation Delay MC44608P100 TDLY 300 420 500 ns Normal Operation Frequency MC44608P40 fosc 36 40 44 kHz Normal Operation Frequency MC44608P75 fosc 68 75 82 kHz Normal Operation Frequency MC44608P100 fosc 90 100 110 kHz Maximum Duty Cycle @ f = fosc dmax 78 82 86 % Tfilt − 250 − ns OSCILLATOR SECTION OVERVOLTAGE SECTION Quick OVP Input Filtering (Rdemag = 100 k
) Propagation Delay (Idemag > Iovp to output low) Quick OVP Current Threshold Protection Threshold Level on VCC Minimum Gap Between VCC−OVP and Vstup−th TPHL(In/Out) − 2.0 − s IOVP 105 120 140 A VCC−OVP 14.8 15.3 15.8 V VCC−OVP − Vstup 1.0 − − V 1. This parameter is measured using 1.0 nF connected between the output and the ground. http://onsemi.com 3 MC44608 ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA = −25°C to +85°C unless otherwise noted) (Note 2) Characteristic Symbol Min Typ Max Unit Vdmg−th 30 50 69 mV Hdmg − 30 − mV tPHL(In/Out) − 300 − ns Idem−lb −0.6 − − A Negative Clamp Level (Idemag = −1.0 mA) Vcl−neg−dem −0.9 −0.7 −0.4 V Positive Clamp Level @ Idemag = 125 A Vcl−pos− 2.05 2.3 2.8 V 1.4 1.7 1.9 V DEMAGNETIZATION DETECTION SECTION (Note 3) Demag Comparator Threshold (Vpin1 increasing) Demag Comparator Hysteresis (Note 4) Propagation Delay (Input to Output, Low to High) Input Bias Current (Vdemag = 50 mV) dem−H Positive Clamp Level @ Idemag = 25 A Vcl−pos− dem−L OVERTEMPERATURE SECTION Trip Level Over Temperature Thigh − 160 − °C Hysteresis Thyst − 30 − °C Idem−NM 20 25 30 A STAND−BY MAXIMUM CURRENT REDUCTION SECTION Normal Mode Recovery Demag Pin Current Threshold K FACTORS SECTION FOR PULSED MODE OPERATION ICCS / Istup MC44608P40 10 x K1 2.4 2.9 3.8 − ICCS / Istup MC44608P75 10 x K1 2.8 3.3 4.2 − ICCS / Istup MC44608P100 10 x K1 3.1 7.0 4.5 − 103 x K2 46 52 63 − x Ksstup 1.8 2.2 2.6 − 90 120 150 − ICCL / Istup 102 (Vstup − UVLO2) / (Vstup − UVLO1) 102 x Ksl (UVLO1 − UVLO2) / (Vstup − UVLO1) 106 ICS / Vcsth 175 198 225 − Dmgr 3.0 4.7 5.5 − (V3 1.0 mA − V3 0.5 mA) / (1.0 mA − 0.5 mA) R3 − 1800 −
Vcontrol Latch−off V3 − 4.8 − V Demag ratio Iovp / Idem NM x Ycstby SUPPLY SECTION Minimum Start−up Voltage VCC Start−up Voltage Output Disabling VCC Voltage After Turn On Hysteresis (Vstup−th − Vuvlo1) VCC Undervoltage Lockout Voltage Vilow − − 50 V Vstup−th 12.5 13.1 13.8 V Vuvlo1 9.5 10 10.5 V Hstup−uvlo1 − 3.1 − V Vuvlo2 6.2 6.6 7.0 V Huvlo1−uvlo2 − 3.4 − V −(ICC) 7.0 9.5 12.8 mA ICCS 2.0 2.4 2.6 2.6 3.2 3.4 3.6 4.0 4.5 mA Latched Off Phase Supply Current ICC−latch 0.3 0.5 0.68 mA Hiccup Mode Duty Cycle (no load) Hiccup − 10 − % Hysteresis (Vuvlo1 − Vuvlo2) Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and (VCC = 9.0 V) Switching Phase Supply Current (no load) MC44608P40 MC44608P75 MC44608P100 2. Adjust VCC above the start−up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. This function can be inhibited by connecting pin 1 to GND. 4. Guaranteed by design (non tested). http://onsemi.com 4 MC44608 PIN FUNCTION DESCRIPTION Pin Name Description 1 Demag The Demag pin offers 3 different functions: Zero voltage crossing detection (50 mV), 24 A current detection and 120 A current detection. The 24 A level is used to detect the secondary reconfiguration status and the 120 A level to detect an Over Voltage status called Quick OVP. 2 Isense The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the power MOSFET. When Isense reaches 1.0 V, the Driver output (pin 5) is disabled. This is known as the Over Current Protection function. A 200 A current source is flowing out of the pin 3 during the start−up phase and during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor and the pin 2, thus a programmable peak current detection can be performed during the SMPS stand−by mode. 3 Control Input A feedback current from the secondary side of the SMPS via the Opto−coupler is injected into this pin. A resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during the Stand−by mode. 4 Ground 5 Driver 6 VCC This pin is the ground of the primary side of the SMPS. The current and slew rate capability of this pin are suited to drive Power MOSFETs. This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher than 15 V and the operating range is between 6.6 V and 13 V. An intermediate voltage level of 10 V creates a disabling condition called Latched Off phase. 7 This pin is to provide isolation between the Vi pin 8 and the VCC pin 6. 8 Vi This pin can be directly connected to a 500 V voltage source for start−up function of the IC. During the Start−up phase a 9.0 mA current source is internally delivered to the VCC pin 6 allowing a rapid charge of the VCC capacitor. As soon as the IC starts−up, this current source is disabled. OPERATING DESCRIPTION Regulation The switch S3 is closed in Stand−by mode during the Latched Off Phase while the switch S2 remains open. (See section PULSED MODE DUTY CYCLE CONTROL). The resistor Rdpulsed (Rduty cycle burst) has no effect on the regulation process. This resistor is used to determine the burst duty cycle described in the chapter “Pulsed Duty Cycle Control” on page 8. V LP−stby V CC Control Input 1 S3 0 1 S2 0 Stand−by Latched off Phase & 3 20
5V Switching Phase PWM Latch V dd The MC44608 works in voltage mode. The on−time is controlled by the PWM comparator that compares the oscillator sawtooth with the regulation block output (refer to the block diagram on page 2). The PWM latch is initialized by the oscillator and is reset by the PWM comparator or by the current sense comparator in case of an over current. This configuration ensures that only a single pulse appears at the circuit output during an oscillator cycle. PWM Regulation Comparator Output 4 kHz Filter 1.6 V Figure 2. Regulator The pin 3 senses the feedback current provided by the Opto coupler. During the switching phase the switch S2 is closed and the shunt regulator is accessible by the pin 3. The shunt regulator voltage is typically 5.0 V. The dynamic resistance of the shunt regulator represented by the zener diode is 20
. The gain of the Control input is given on Figure 11 which shows the duty cycle as a function of the current injected into the pin 3. A 4.0 kHz filter network is inserted between the shunt regulator and the PWM comparator to cancel the high frequency residual noise. Current Sense The inductor current is converted to a positive voltage by inserting a ground reference sense resistor RSense in series with the power switch. The maximum current sense threshold is fixed at 1.0 V. The peak current is given by the following equation: Ipk max  http://onsemi.com 5 1 (A) R sense(
) MC44608 Oscillator Buffer Output In stand−by mode, this current can be lowered as due to the activation of a 200 A current source: R Q DMG S 1  (R cs(k
)
0, 2) Ipk  (A) max stby R sense(
) Demag 200  A 1 DMG & 50/20 mV STAND−BY & 0 Idemag > 24  A >120  A START−UP 1 + − Idemag Switching Phase Current Mirror Isense Rcs L.E.B. 2 Overcurrent Comparator + Figure 4. Demagnetization Block OC This function can be inhibited by grounding it but in this case, the quick and programmable OVP is also disabled. − Rsense 1V Oscillator The MC44608 contains a fixed frequency oscillator. It is built around a fixed value capacitor CT successively charged and discharged by two distinct current sources ICH and IDCH. The window comparator senses the CT voltage value and activates the sources when the voltage is reaching the 2.4 V/4.0 V levels. Figure 3. Current Sense The current sense input consists of a filter (6.0 k
, 4.0 pF) and of a leading edge blanking. Thanks to that, this pin is not sensitive to the power switch turn on noise and spikes and practically in most applications, no filtering network is required to sense the current. Finally, this pin is used: − as a protection against over currents (Isense > I) − as a reduction of the peak current during a Pulsed Mode switching phase. The overcurrent propagation delay is reduced by producing a sharp output turn off (high slew rate). This results in an abrupt output turn off in the event of an over current and in the majority of the pulsed mode switching sequence. ICH DMG from Demag logic block OSC SCH & 4V 2.4 V Window + comp Clock − SDCH IDCH CT Demagnetization Section The MC44608 demagnetization detection consists of a comparator designed to compare the VCC winding voltage to a reference that is typically equal to 50 mV. This reference is chosen low to increase effectiveness of the demagnetization detection even during start−up. A latch is incorporated to turn the demagnetization block output into a low level as soon as a voltage less than 50 mV is detected, and to keep it in this state until a new pulse is generated on the output. This avoids any ringing on the input signal which may alter the demagnetization detection. For a higher safety, the demagnetization block output is also directly connected to the output, which is disabled during the demagnetization phase. The demagnetization pin is also used for the quick, programmable OVP. In fact, the demagnetization input current is sensed so that the circuit output is latched off when this current is detected as higher than 120 A. Figure 5. Oscillator Block The complete demagnetization status DMG is used to inhibit the recharge of the CT capacitor. Thus in case of incomplete transformer demagnetization the next switching cycle is postpone until the DMG signal appears. The oscillator remains at 2.4 V corresponding to the sawtooth valley voltage. In this way the SMPS is working in the so called SOPS mode (Self Oscillating Power Supply). In that case the effective switching frequency is variable and no longer depends on the oscillator timing but on the external working conditions (Refer to DMG signal in the Figure 6). http://onsemi.com 6 MC44608 OSC 4V V CC 13 V Vcont 2.4 V 10 V Clock 6.5 V DMG Start−up Phase Latched off Phase Switching Phase Iprim Figure 7. Hiccup Mode Figure 6. In case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%. The OSC and Clock signals are provided according to the Figure 6. The Clock signals correspond to the CT capacitor discharge. The bottom curve represents the current flowing in the sense resistor Rcs. It starts from zero and stops when the sawtooth value is equal to the control voltage Vcont. In this way the SMPS is regulated with a voltage mode control. Mode Transition The LW latch Figure 8 is the memory of the working status at the end of every switching sequence. Two different cases must be considered for the logic at the termination of the SWITCHING PHASE: 1. No Over Current was observed 2. An Over Current was observed These 2 cases are corresponding to the signal labelled NOC in case of “No Over Current” and “OC” in case of Over Current. So the effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over current and Q=0 for over current. This sequence is repeated during the Switching phase. Several events can occur: 1. SMPS switch OFF 2. SMPS output overload 3. Transition from Normal to Pulsed Mode 4. Transition from Pulsed Mode to Normal Mode Overvoltage Protection The MC44608 offers two OVP functions: − a fixed function that detects when VCC is higher than 15.4 V − a programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and compared to the reference current Iovp (120 A). Thus this OVP is quicker as it is not impacted by the VCC inertia and is called QOVP. In both cases, once an OVP condition is detected, the output is latched off until a new circuit START−UP. Start−up Management The Vi pin 8 is directly connected to the HV DC rail Vin. This high voltage current source is internally connected to the VCC pin and thus is used to charge the VCC capacitor. The VCC capacitor charge period corresponds to the Start−up phase. When the VCC voltage reaches 13 V, the high voltage 9.0 mA current source is disabled and the device starts working. The device enters into the switching phase. It is to be noticed that the maximum rating of the Vi pin 8 is 500 V. ESD protection circuitry is not currently added to this pin due to size limitations and technology constraints. Protection is limited by the drain−substrate junction in avalanche breakdown. To help increase the application safety against high voltage spike on that pin it is possible to insert a small wattage 1.0 k
series resistor between the Vin rail and pin 8. The Figure 7 shows the VCC voltage evolution in case of no external current source providing current into the VCC pin during the switching phase. This case can be encountered in SMPS when the self supply through an auxiliary winding is not present (strong overload on the SMPS output for example). The Figure 17 also depicts this working configuration. Latched Off Phase VPWM OUT & NOC OC S Q R LEB out 1V & LW Q + CS − & S Q Mode R1 R2 Stand−by & S1 Switch Start−up Idemag Switching Start−up Phase > 24  A Phase Phase Figure 8. Transition Logic • 1. SMPS SWITCH OFF When the mains is switched OFF, so long as the bulk electrolithic bulk capacitor provides energy to the SMPS, the controller remains in the switching phase. Then the peak current reaches its maximum peak value, the switching frequency decreases and all the secondary voltages are reduced. The VCC voltage is also reduced. When VCC is equal to 10 V, the SMPS stops working. http://onsemi.com 7 MC44608 • 2. Overload according to the equation of the current sense section, page 5. The C.S. clamping level depends on the power to be delivered to the load during the SMPS stand−by mode. Every switching sequence ON/OFF is terminated by an OC as long as the secondary Zener diode voltage has not been reached. When the Zener voltage is reached the ON cycle is terminated by a true PWM action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW latch stores this NOC status. The LATCHED OFF PHASE: The MODE latch is set. The START−UP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1). The SWITCHING PHASE: The Stand−by signal is validated and the 200 A is sourced out of the Current Sense pin 2. In the hiccup mode the 3 distinct phases are described as follows (refer to Figure 7): The SWITCHING PHASE: The SMPS output is low and the regulation block reacts by increasing the ON time (dmax = 80%). The OC is reached at the end of every switching cycle. The LW latch (Figure 8) is reset before the VPWM signal appears. The SMPS output voltage is low. The VCC voltage cannot be maintained at a normal level as the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. Vout nominal / Vout short−circuit). Consequently the VCC voltage is reduced at an operating rate given by the combination VCC capacitor value together with the ICC working consumption (3.2 mA) according to the equation 2. When VCC crosses 10V the WORKING PHASE gets terminated. The LW latch remains in the reset status. The LATCHED−OFF PHASE: The VCC capacitor voltage continues to drop. When it reaches 6.5 V this phase is terminated. Its duration is governed by equation 3. The START−UP PHASE is reinitiated. The high voltage start−up current source (−ICC1 = 9.0 mA) is activated and the MODE latch is reset. The VCC voltage ramps up according to the equation 1. When it reaches 13 V, the IC enters into the SWITCHING PHASE. The NEXT SWITCHING PHASE: The high voltage current source is inhibited, the MODE latch (Q=0) activates the NORMAL mode of operation. Figure 3 shows that no current is injected out pin 2. The over current sense level corresponds to 1.0 V. As long as the overload is present, this sequence repeats. The SWITCHING PHASE duty cycle is in the range of 10%. • 4. Transition from Stand−by to Normal The secondary reconfiguration is removed. The regulation on the low voltage secondary rail can no longer be achieved, thus at the end of the SWITCHING PHASE, no PWM condition can be encountered. The LW latch is reset. At the next WORKING PHASE a NORMAL mode status takes place. In order to become independent of the recovery time constant on the secondary side of the SMPS an additional reset input R2 is provided on the MODE latch. The condition Idemag