MC74AC00, MC74ACT00
Quad 2-Input NAND Gate
High−Performance Silicon−Gate CMOS
Features
•
•
•
•
•
•
•
Output Drive Capability: $24 mA
Operating Voltage Range: 2 to 6 V AC00; 4.5 to 5.5 ACT00
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 32 FETs
These are Pb−Free Devices
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MARKING
DIAGRAMS
14
14
A1
B1
1
3
2
SOIC−14
D SUFFIX
CASE 751A
xxx00G
AWLYWW
1
1
Y1
14
A2
B2
A3
B3
A4
B4
4
6
5
Y2
Y = AB
9
8
10
xxx
00
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
14
Y3
1
12
11
13
xxx
= AC or ACT
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or G
= Pb−Free Package
Y4
PIN 14 = VCC
PIN 7 = GND
Figure 1. Logic Diagram
(Note: Microdot may be in either location)
VCC
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
FUNCTION TABLE
Inputs
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
Figure 2. Pinout: 14−Lead Packages (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 10
1
Publication Order Number:
MC74AC00/D
MC74AC00, MC74ACT00
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 v VI v VCC )0.5
V
*0.5 v VO v VCC )0.5
V
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$50
mA
IO
DC Output Sink/Source Current
$50
mA
ICC
DC Supply Current per Output Pin
$50
mA
IGND
DC Ground Current per Output Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
°C
TL
Lead temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction temperature under Bias
)150
°C
qJA
Thermal Resistance (Note 2)
SOIC
TSSOP
125
170
°C/W
PD
Power Dissipation in Still Air at 85°C
SOIC
TSSOP
125
170
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85°C (Note 6)
$100
mA
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
(Note 1)
Level 1
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
MC74AC00
MC74ACT00
Min
Typ
Max
Unit
2.0
4.5
5.0
5.0
6.0
5.5
V
0
−
VCC
V
VCC
Supply Voltage
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note 7)
MC74AC00
VCC @ 3.0 V
VCC @ 4.5 V
VCC @ 5.5 V
−
−
−
150
40
25
−
−
−
ns/V
tr, tf
Input Rise and Fall Time (Note 8)
MC74ACT00
VCC @ 4.5 V
VCC @ 5.5 V
−
−
10
8.0
−
−
ns/V
TJ
Junction Temperature
−
−
150
°C
TA
Operating Ambient Temperature Range
−55
25
125
°C
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Vin from 30% to 70% VCC.
8. Vin from 0.8 V to 2.0 V.
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2
MC74AC00, MC74ACT00
DC CHARACTERISTICS
MC74AC00
Symbol
Parameter
VCC
(V)
TA = +255C
TA = −405C to +855C
Typ
TA = −555C + 1255C
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
IOUT = −50 mA
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
2.4
3.7
4.7
*VIN = VIL or VIH
−12 mA
−24 mA
IOH
−24 mA
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IOUT = 50 mA
V
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
0.5
0.5
0.5
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
VOL
Maximum Low Level
Output Voltage
IIN
Maximum Input
Leakage Current
5.5
−
$0.
1
$1.0
$1.0
mA
VI = VCC, GND
IOLD
†Minimum Dynamic
Output Current
5.5
−
−
75
50
mA
VOLD = 1.65 V Max
5.5
−
−
−75
−50
mA
VOHD = 3.85 V Min
Maximum Quiescent
Supply Current
5.5
−
4.0
40
40
mA
VIN = VCC or GND
IOHD
ICC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
AC CHARACTERISTICS (tr = tf = 3.0 nS; CL = 50 pF; see Figures 3 and 4 for Waveforms)
MC74AC00
Symbol
Parameter
TA = +255C
TA = −405C to +855C
TA = −555C to + 1255C
VCC*
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
tPLH
Propagation Delay
3.3
5.0
2.0
1.5
7.0
6.0
9.5
8.0
2.0
1.5
10.0
8.5
1.0
1.0
11.0
8.5
ns
tPHL
Propagation Delay
3.3
5.0
1.5
1.5
5.5
4.5
8.0
6.5
1.0
1.0
8.5
7.0
1.0
1.0
9.0
7.0
ns
*Voltage Range 3.3 V is 3.3 V $0.3 V.
Voltage Range 5.0 V is 5.0 V $0.5 V.
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3
MC74AC00, MC74ACT00
DC CHARACTERISTICS
MC74ACT00
Symbol
Parameter
VCC
(V)
TA = +255C
TA = −405C to +855C
Typ
TA = −555C to + 1255C
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
IOUT = −50 mA
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
3.7
4.7
*VIN = VIL or VIH
IOH
−24 mA
−24 mA
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
IOUT = 50 mA
V
4.5
5.5
−
−
0.36
0.36
0.44
0.44
0.5
0.5
*VIN = VIL or VIH
IOL
24 mA
24 mA
VOL
Maximum Low Level
Output Voltage
IIN
Maximum Input
Leakage Current
5.5
−
$0.1
$1.0
$1.0
mA
VI = VCC, GND
DICCT
Additional Max. ICC/Input
5.5
0.6
−
1.5
1.6
mA
VI = VCC − 2.1 V
IOLD
†Minimum Dynamic
Output Current
5.5
−
−
75
50
mA
VOLD = 1.65 V Max
5.5
−
−
−75
−50
mA
VOHD = 3.85 V Min
Maximum Quiescent
Supply Current
5.5
−
4.0
40
40
mA
VIN = VCC or GND
IOHD
ICC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (tr = tf = 3.0 nS; CL = 50 pF; see Figures 3 and 4 for Waveforms)
MC74ACT00
Parameter
Symbol
TA = +255C
TA = −405C to +855C
TA = −555C to +1255C
VCC*
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
tPLH
Propagation Delay
5.0
1.5
5.5
9.0
1.0
9.5
1.0
9.5
ns
tPHL
Propagation Delay
5.0
1.5
4.0
7.0
1.0
8.0
1.0
8.0
ns
*Voltage Range 5.0 V is 5.0 V $0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Test Conditions
Unit
CIN
Input Capacitance
4.5
VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance
30
VCC = 5.0 V
pF
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4
MC74AC00, MC74ACT00
tf
tr
VCC
90%
INPUT
A OR B
Vmi
10%
GND
tPLH
OUTPUT Y
tPHL
50%
Vmi
= 50% for MC74AC00
= 1.5 V for MC74ACT00
Figure 3. Switching Waveforms
INPUT
OUTPUT
DEVICE
UNDER
TEST
450 W
50 W Scope
Test Point
CL *
*Includes all probe and jig capacitance
Figure 4. Test Circuit
ORDER INFORMATION
Package
Shipping†
MC74AC00DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74AC00DR2G
SOIC−14
(Pb−Free)
MC74AC00DTR2G
TSSOP−14
(Pb−Free)
MC74ACT00DG
SOIC−14
(Pb−Free)
MC74ACT00DR2G
SOIC−14
(Pb−Free)
MC74ACT00DTR2G
TSSOP−14
(Pb−Free)
Device
2500 / Tape and Reel
55 Units / Rail
2500 / Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
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