MC74AC157, MC74ACT157
Quad 2-Input Multiplexer
The MC74AC157/74ACT157 is a high-speed quad 2-input
multiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four outputs present the
selected data in the true (non-inverted) form.
The MC74AC157/74ACT157 can also be used as a function
generator.
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Features
•Outputs Source/Sink 24 mA
•′ACT157 Has TTL Compatible Inputs
•Pb-Free Packages are Available
PDIP-16
N SUFFIX
CASE 648
16
1
VCC
E
I0c
I1c
Zc
I0d
I1d
Zd
16
15
14
13
12
11
10
9
SOIC-16
D SUFFIX
CASE 751B
16
1
1
2
3
4
5
6
7
S
I0a
I1a
Za
I0b
I1b
Zb
TSSOP-16
DT SUFFIX
CASE 948F
16
8
GND
1
Figure 1. Pinout: 16-Lead Packages Conductors
(Top View)
SOEIAJ-16
M SUFFIX
CASE 966
16
TRUTH TABLE
Inputs
1
Outputs
E
S
I0
I1
Z
H
L
L
L
L
X
H
H
L
L
X
X
X
L
H
X
L
H
X
X
L
L
H
L
H
PIN NAMES
PIN
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FUNCTION
I0a-I0d
Source 0 Data Inputs
I1a-I1d
Source 0 Data Inputs
E
Enable Input
S
Select Input
Za-Zd
Outputs
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 3 of this data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
July, 2007 - Rev. 7
1
Publication Order Number:
MC74AC157/D
MC74AC157, MC74ACT157
E I0a I1a I0b I1b I0c I1c I0d I1d
S
Za
Zb
Zc
Zd
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
Za = E•(I1a•S+I0a•S)
Zb = E•(I1b•S+I0b•S)
Zc = E•(I1c•S+I0c•S)
Zd = E•(I1d•S+I0d•S)
A common use of the MC74AC157/74ACT157 is the
moving of data from two groups of registers to four common
output busses. The particular register from which the data
comes is determined by the state of the Select input. A less
obvious use is as a function generator. The
MC74AC157/74ACT157 can generate any four of the
sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.
The MC74AC157/74ACT157 is a quad 2-input
multiplexer. It selects four bits of data from two sources
under the control of a common Select input (S). The Enable
input (E) is active-LOW. When E is HIGH, all of the outputs
(Z) are forced LOW regardless of all other inputs. The
MC74AC157/74ACT157 is the logic implementation of a
4-pole, 2-position switch where the position of the switch
is determined by the logic levels supplied to the Select input.
The logic equations for the outputs are shown below:
I0a
I1a
I0b
I1b
Zb
Za
NOTE:
I0c
I1c
Zc
I0d
I1d
E
Zd
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
S
MC74AC157, MC74ACT157
MARKING DIAGRAMS
PDIP-16
16
SOIC-16
TSSOP-16
16
MC74AC157N
AWLYYWWG
1
16
16
MC74ACT157N
AWLYYWWG
74AC157
ALYWG
1
1
16
16
ACT
157
ALYWG
G
ACT157G
AWLYWW
1
1
16
AC
157
ALYWG
G
AC157G
AWLYWW
1
SOEIAJ-16
16
74ACT157
ALYWG
1
1
A
WL, L
YY, Y
WW, W
G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
= Pb-Free Package
(Note: Microdot may be in either location)
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
VCC
DC Supply Voltage (Referenced to GND)
VIN
VOUT
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
-65 to +150
°C
IIN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
tr, tf
Parameter
Supply Voltage
Min
Typ
Max
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
-
VCC
VCC @ 3.0 V
-
150
-
VCC @ 4.5 V
-
40
-
VCC @ 5.5 V
-
25
-
VCC @ 4.5 V
-
10
-
VCC @ 5.5 V
-
8.0
-
-
-
140
°C
-40
25
85
°C
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Unit
V
V
ns/V
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
Output Current - High
-
-
-24
mA
IOL
Output Current - Low
-
-
24
mA
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
ns/V
MC74AC157, MC74ACT157
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
-40°C to
+85°C
Typ
VIH
VIL
VOH
VOL
IIN
IOLD
IOHD
ICC
Unit
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC - 0.1 V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC - 0.1 V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
-
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
-
0.36
0.36
0.36
0.44
0.44
0.44
5.5
-
±0.1
5.5
-
5.5
-
5.5
-
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
IOUT = -50 mA
*VIN = VIL or VIH
-12 mA
IOH
-24 mA
-24 mA
V
IOUT = 50 mA
V
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
±1.0
mA
VI = VCC, GND
-
75
mA
VOLD = 1.65 V Max
-
-75
mA
VOHD = 3.85 V Min
8.0
80
mA
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74AC
74AC
TA = +25°C
CL = 50 pF
TA = -40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
S to Zn
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.5
1.5
13.0
10.0
ns
3-6
tPHL
Propagation Delay
S to Zn
3.3
5.0
1.5
1.5
6.5
5.0
11.0
8.5
1.5
1.0
12.0
9.5
ns
3-6
tPLH
Propagation Delay
E to Zn
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.5
1.5
13.0
10.0
ns
3-6
tPHL
Propagation Delay
En to Zn
3.3
5.0
1.5
1.5
6.5
5.5
11.0
9.0
1.5
1.0
12
9.5
ns
3-6
tPLH
Propagation Delay
In to Zn
3.3
5.0
1.5
1.5
5.0
4.0
8.5
6.5
1.0
1.0
9.0
7.0
ns
3-5
3.3
5.0
1.5
1.5
5.0
4.0
8.0
6.5
1.0
1.0
9.0
7.0
ns
3-5
Propagation Delay
In to Zn
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
tPHL
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4
MC74AC157, MC74ACT157
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
-40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC - 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC - 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
-
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
-
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
Maximum Input
Leakage Current
5.5
-
±0.1
±1.0
mA
VI = VCC, GND
Additional Max. ICC/Input
5.5
0.6
-
1.5
mA
VI = VCC -2.1 V
†Minimum Dynamic
Output Current
5.5
-
-
75
mA
VOLD = 1.65 V Max
5.5
-
-
-75
mA
VOHD = 3.85 V Min
5.5
-
8.0
80
mA
VIN = VCC or GND
VOL
IIN
DICCT
IOLD
IOHD
ICC
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
IOUT = -50 mA
*VIN = VIL or VIH
-24 mA
IOH
-24 mA
V
IOUT = 50 mA
V
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = -40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min
Typ
Max
Min
Max
5.0
2.0
-
9.0
1.5
10.0
ns
3-6
Propagation Delay
S to Zn
5.0
2.0
-
9.5
2.0
10.5
ns
3-6
tPLH
Propagation Delay
En to Zn
5.0
1.5
-
10
1.5
11.5
ns
3-6
tPHL
Propagation Delay
En to Zn
5.0
1.5
-
8.5
1.0
9.0
ns
3-6
tPLH
Propagation Delay
In to Zn
5.0
1.5
-
7.0
1.0
8.5
ns
3-5
5.0
1.5
-
7.5
1.0
8.5
ns
3-5
tPLH
Propagation Delay
S to Zn
tPHL
Propagation Delay
In to Zn
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
tPHL
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5
MC74AC157, MC74ACT157
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
50
pF
VCC = 5.0 V
ORDERING INFORMATION
Device Order Number
Package
MC74AC157N
PDIP-16
MC74AC157NG
PDIP-16
(Pb-Free)
MC74ACT157NG
PDIP-16
(Pb-Free)
MC74AC157D
SOIC-16
MC74AC157DG
SOIC-16
(Pb-Free)
MC74ACT157D
SOIC-16
MC74ACT157DG
SOIC-16
(Pb-Free)
MC74AC157DR2
SOIC-16
MC74AC157DR2G
SOIC-16
(Pb-Free)
MC74ACT157DR2
SOIC-16
MC74ACT157DR2G
SOIC-16
(Pb-Free)
MC74AC157DTR2
TSSOP-16*
MC74AC157DTR2G
TSSOP-16*
MC74ACT157DTR2
TSSOP-16*
MC74ACT157DTR2G
TSSOP-16*
MC74ACT157M
SOEIAJ-16
MC74AC157MELG
SOEIAJ-16
(Pb-Free)
MC74ACT157MELG
SOEIAJ-16
(Pb-Free)
Shipping†
25 Units / Rail
48 Units / Rail
2500 Tape & Reel
50 Units / Rail
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
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6
MC74AC157, MC74ACT157
PACKAGE DIMENSIONS
PDIP-16
N SUFFIX
CASE 648-08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
-A16
9
1
8
B
F
C
L
S
-T-
SEATING
PLANE
K
H
D
M
J
G
16 PL
0.25 (0.010)
M
T A
M
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7
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC74AC157, MC74ACT157
PACKAGE DIMENSIONS
SOIC-16
D SUFFIX
CASE 751B-05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
-A-
16
9
1
8
-B-
P
8 PL
0.25 (0.010)
B
M
S
G
R
K
F
X 45 _
C
-T-
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74AC157, MC74ACT157
PACKAGE DIMENSIONS
TSSOP-16
DT SUFFIX
CASE 948F-01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
S
V
S
S
K
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
-U-
L
SECTION N-N
J
PIN 1
IDENT.
N
0.25 (0.010)
8
1
M
0.15 (0.006) T U
S
A
-V-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
N
F
DETAIL E
-W-
C
0.10 (0.004)
-T- SEATING
PLANE
H
D
DETAIL E
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
--- 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74AC157, MC74ACT157
PACKAGE DIMENSIONS
SOEIAJ-16
M SUFFIX
CASE 966-01
ISSUE A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
0_
10 _
0.028
0.035
--0.031
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