MC74AC273DW

MC74AC273, MC74ACT273 Octal D Flip-Flop The MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW−to−HIGH clock transition, is transferred to the corresponding flip−flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. www.onsemi.com SOIC−20WB SUFFIX DW CASE 751D 20 1 Features • • • • • • • • • • Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip−Flops Buffered Common Clock Buffered, Asynchronous Master Reset See MC74AC377 for Clock Enable Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version Outputs Source/Sink 24 mA ′ACT273 Has TTL Compatible Inputs These are Pb−Free Devices VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 Q4 12 13 TSSOP−20 SUFFIX DT CASE 948E 20 1 PIN ASSIGNMENT CP PIN FUNCTION D0−D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0−Q7 Data Outputs 11 D0 D1 D2 D3 D4 D5 D6 D7 CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 2 3 4 MR Q0 D0 D1 5 6 Q1 Q2 (Top View) 7 8 9 10 D2 D3 Q3 GND Logic Symbol Pinout: 20−Lead Packages Conductors ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. MODE SELECT-FUNCTION TABLE Operating Mode Inputs Outputs MR CP Dn Qn DEVICE MARKING INFORMATION Reset (Clear) L X X L Load ′1′ See general marking information in the device marking section on page 6 of this data sheet. H H H Load ′0′ H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition © Semiconductor Components Industries, LLC, 2016 December, 2016 − Rev. 8 1 Publication Order Number: MC74AC273/D MC74AC273, MC74ACT273 D0 D1 D2 D3 D4 D5 D6 D7 CP D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP RD RD RD RD RD RD RD RD MR O0 O1 O2 O3 O4 O5 O6 O7 NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. Logic Diagram www.onsemi.com 2 MC74AC273, MC74ACT273 MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) (Note 1) −0.5 to VCC +0.5 V VOUT IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±50 mA IOUT DC Output Sink/Source Current ±50 mA ICC DC Supply Current, per Output Pin ±50 mA IGND DC Ground Current, per Output Pin ±100 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature Under Bias 140 _C qJA Thermal Resistance (Note 2) SOIC TSSOP 65.8 110.7 _C/W MSL Moisture Sensitivity SOIC TSSOP Level 3 Level 1 FR Flammability Rating Oxygen Index: 30% − 35% VESD ILatchup ESD Withstand Voltage UL 94 V−0 @ 0.125 in Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Latchup Performance > 2000 > 200 > 1000 V ±100 mA Above VCC and Below GND at 85_C (Note 6) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IOUT absolute maximum rating must be observed. 2. The package thermal impedance is calculated in accordance with JESD 51−7. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout tr, tf Parameter Supply Voltage Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − −40 25 85 °C DC Input Voltage, Output Voltage (Ref. to GND) Input Rise and Fall Time (Note 7) ′AC Devices except Schmitt Inputs Unit V V ns/V tr, tf Input Rise and Fall Time (Note 8) ′ACT Devices except Schmitt Inputs TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 8. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. www.onsemi.com 3 MC74AC273, MC74ACT273 DC CHARACTERISTICS Symbol VCC Parameter (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V IOUT = −50 mA 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 V *VIN = VIL or VIH −12 mA −24 mA IOH −24 mA 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 V IOUT = 50 mA 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 V *VIN = VIL or VIH 12 mA 24 mA IOL 24 mA Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND †Minimum Dynamic Output Current 5.5 5.5 − − − − 75 −75 mA VOLD = 1.65 V Max VOHD = 3.85 V Min VOL IIN IOLD IOHD Maximum Low Level Output Voltage ICC Maximum Quiescent Supply Current 5.5 − 8.0 80 mA *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. VIN = VCC or GND AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Figure No. Min Typ Max Min Max fmax Maximum Clock Frequency 3.3 5.0 90 140 125 175 − − 75 125 − − Mhz 3−3 tPLH Propagation Delay Clock to Output 3.3 5.0 4.0 3.0 7.0 5.5 12.5 9.0 3.0 2.5 14.0 10.0 ns 3−6 tPHL Propagation Delay Clock to Output 3.3 5.0 4.0 3.0 7.0 5.0 13.0 10.0 3.5 2.5 14.5 11.0 ns 3−6 13.0 10.0 3.5 2.5 14.0 10.5 ns 3−6 Unit Figure No. Propagation Delay 3.3 4.0 7.0 MR to Output 5.0 3.0 5.0 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. tPHL AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum ts Setup Time, HIGH or LOW Data to CP 3.3 5.0 3.5 2.5 5.5 4.0 6.0 4.5 ns 3−9 th Hold Time, HIGH or LOW Data to CP 3.3 5.0 −2.0 −1.0 0 1.0 0 1.0 ns 3−9 tw Clock Pulse Width HIGH or LOW 3.3 5.0 3.5 2.5 5.5 4.0 6.0 4.5 ns 3−6 tw MR Pulse Width HIGH or LOW 3.3 5.0 2.0 1.5 5.5 4.0 6.0 4.5 ns 3−6 Recovery Time 3.3 1.5 3.5 MR to CP 5.0 1.0 2.0 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. 4.5 3.0 ns 3−9 trec www.onsemi.com 4 MC74AC273, MC74ACT273 DC CHARACTERISTICS 74ACT Symbol Parameter VCC (V) 74ACT TA = TA = +25°C Typ Unit −40°C to +85°C Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 VOL Maximum Low Level Output Voltage IOUT = −50 mA *VIN = VIL or VIH IOH −24 mA −24 mA V IOUT = 50 mA V V *VIN = VIL or VIH 24 mA IOL 24 mA Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND DICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOLD IOHD †Minimum Dynamic Output Current 5.5 5.5 − − − − 75 −75 mA VOLD = 1.65 V Max VOHD = 3.85 V Min 80 mA VIN = VCC or GND IIN ICC Maximum Quiescent Supply Current 5.5 − 8.0 *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Parameter Symbol VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Figure No. Min Typ Max Min Max − MHz 3−3 fmax Maximum Clock Frequency 5.0 125 200 − 125 tPHL Propagation Delay Clock to Output 5.0 3.0 6.0 10 2.5 11.0 ns 3−6 tPLH Propagation Delay Clock to Output 5.0 3.0 6.5 11 2.5 12.0 ns 3−6 tPHL Propagation Delay MR to Output 5.0 3.0 7.0 11 2.5 11.5 ns 3−6 Unit Figure No. *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum ts Setup Time, HIGH or LOW − Data to CP 5.0 3.0 4.5 5.0 ns 3−9 th Hold Time, HIGH or LOW − Data to CP 5.0 −2.5 2.0 2.0 ns 3−9 tw Clock Pulse Width − HIGH or LOW 5.0 2.5 4.0 4.5 ns 3−6 tw MR Pulse Width − HIGH or LOW 5.0 2.5 4.0 4.5 ns 3−6 trec Recovery Time − MR to CP 5.0 −1.0 2.0 3.0 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 50 pF VCC = 5.0 V www.onsemi.com 5 MC74AC273, MC74ACT273 ORDERING INFORMATION Package Shipping† MC74AC273DWG SOIC−20WB (Pb−Free) 38 Units / Rail MC74AC273DWR2G SOIC−20WB (Pb−Free) 1000 / Tape & Reel MC74AC273DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel MC74ACT273DWG SOIC−20WB (Pb−Free) 38 Units / Rail MC74ACT273DWR2G SOIC−20WB (Pb−Free) 1000 / Tape & Reel MC74ACT273DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−20WB TSSOP−20 20 20 AC 273 ALYWG G AC273 AWLYYWWG 1 1 20 20 ACT 273 ALYWG G ACT273 AWLYYWWG 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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