MC74AC373NG

MC74AC373, MC74ACT373 Octal Transparent Latch with 3-State Outputs The MC74AC373/74ACT373 consists of eight latches with 3−state outputs for bus organized system applications. The flip−flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. www.onsemi.com SOIC−20W DW SUFFIX CASE 751D Features • • • • • Eight Latches in a Single Package 3−State Outputs for Bus Interfacing Outputs Source/Sink 24 mA ′ACT373 Has TTL Compatible Inputs These are Pb−Free Devices 1 TSSOP−20 DT SUFFIX CASE 948E 1 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE 20 19 18 17 16 15 14 13 12 11 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. 1 2 3 4 5 6 7 8 9 10 OE O0 D0 D1 O1 O2 D2 D3 O3 GND Figure 1. Pinout: 20−Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN FUNCTION D0−D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0−O7 3−State Latch Outputs D0 D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2017 February, 2017 − Rev. 11 1 Publication Order Number: MC74AC373/D MC74AC373, MC74ACT373 FUNCTIONAL DESCRIPTION The MC74AC373/74ACT373 contains eight D−type latches with 3−state standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2−state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. TRUTH TABLE Inputs Outputs OE LE Dn On H L L L X H H L X L H X Z L H O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before LOW-to-HIGH Transition of Clock D0 D1 D D2 D G O D3 D G O D4 D G O D5 D G O D6 D G O D7 D G O D G LE OE NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2 O G O MC74AC373, MC74ACT373 MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) (Note 1) −0.5 to VCC +0.5 V VOUT IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±50 mA IOUT DC Output Sink/Source Current ±50 mA ICC DC Supply Current, per Output Pin ±50 mA IGND DC Ground Current, per Output Pin ±100 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature Under Bias 140 _C qJA Thermal Resistance (Note 2) SOIC TSSOP 65.8 110.7 _C/W MSL Moisture Sensitivity SOIC TSSOP Level 3 Level 1 FR Flammability Rating Oxygen Index: 30% − 35% VESD ILatchup ESD Withstand Voltage Latchup Performance UL 94 V−0 @ 0.125 in Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Above VCC and Below GND at 85_C (Note 6) > 2000 > 200 > 1000 V ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IOUT absolute maximum rating must be observed. 2. The package thermal impedance is calculated in accordance with JESD 51−7. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT tr, tf Parameter Supply Voltage Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − −40 25 85 °C DC Input Voltage, Output Voltage (Ref. to GND) Input Rise and Fall Time (Note 7) ′AC Devices except Schmitt Inputs Unit V V ns/V tr, tf Input Rise and Fall Time (Note 8) ′ACT Devices except Schmitt Inputs TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 8. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. www.onsemi.com 3 MC74AC373, MC74ACT373 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ VIH VIL VOH VOL Unit Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 Maximum Low Level Output Voltage IOUT = −50 mA V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 mA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND IOZ Maximum 3−State Current 5.5 − ±0.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 mA VIN = VCC or GND IOLD †Minimum Dynamic Output Current IOHD ICC Maximum Quiescent Supply Current Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. www.onsemi.com 4 MC74AC373, MC74ACT373 AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com) Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to On 3.3 5.0 1.5 1.5 10 7.0 13.5 9.5 1.5 1.5 15 10.5 ns 3−5 tPHL Propagation Delay Dn to On 3.3 5.0 1.5 1.5 9.5 7.0 13 9.5 1.5 1.5 14.5 10.5 ns 3−5 tPLH Propagation Delay LE to On 3.3 5.0 1.5 1.5 10 7.5 13.5 9.5 1.5 1.5 15 10.5 ns 3−6 tPHL Propagation Delay LE to On 3.3 5.0 1.5 1.5 9.5 7.0 12.5 9.5 1.5 1.5 14 10.5 ns 3−6 tPZH Output Enable Time 3.3 5.0 1.5 1.5 9.0 7.0 11.5 8.5 1.0 1.0 13 9.5 ns 3−7 tPZL Output Enable Time 3.3 5.0 1.5 1.5 8.5 6.5 11.5 8.5 1.0 1.0 13 9.5 ns 3−8 tPHZ Output Disable Time 3.3 5.0 1.5 1.5 10 8.0 12.5 11 1.0 1.0 14.5 12.5 ns 3−7 tPLZ Output Disable Time 3.3 5.0 1.5 1.5 8.0 6.5 11.5 8.5 1.0 1.0 12.5 10 ns 3−8 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to LE 3.3 5.0 3.5 2.0 5.5 4.0 6.0 4.5 ns 3−9 th Hold Time, HIGH or LOW Dn to LE 3.3 5.0 −3.0 −1.5 1.0 1.0 1.0 1.0 ns 3−9 tw LE Pulse Width, HIGH 3.3 5.0 4.0 2.0 5.5 4.0 6.0 4.5 ns 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 5 MC74AC373, MC74ACT373 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = −40°C to +85°C Typ Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V Maximum 3-State Current 5.5 − ±0.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 mA VIN = VCC or GND VOL IIN DICCT IOZ IOLD IOHD ICC Maximum Low Level Output Voltage †Minimum Dynamic Output Current Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. www.onsemi.com 6 V V IOUT = −50 mA *VIN = VIL or VIH IOH −24 mA −24 mA IOUT = 50 mA MC74AC373, MC74ACT373 AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com) Parameter Symbol VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to On 5.0 2.5 8.5 10 1.5 11.5 ns 3−5 tPHL Propagation Delay Dn to On 5.0 2.0 8.0 10 1.5 11.5 ns 3−5 tPLH Propagation Delay LE to On 5.0 2.5 8.5 11 2.0 11.5 ns 3−6 tPHL Propagation Delay LE to On 5.0 2.0 8.0 10 1.5 11.5 ns 3−6 tPZH Output Enable Time 5.0 2.0 8.0 9.5 1.5 10.5 ns 3−7 tPZL Output Enable Time 5.0 2.0 7.5 9.0 1.5 10.5 ns 3−8 tPHZ Output Disable Time 5.0 2.5 9.0 11 2.5 12.5 ns 3−7 5.0 1.5 7.5 8.5 1.0 10 ns 3−8 tPLZ Output Disable Time *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS (For Figures and Waveforms − See AND8277/D at www.onsemi.com) Parameter Symbol VCC* (V) Typ 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to LE 5.0 3.0 7.0 8.0 ns 3−9 th Hold Time, HIGH or LOW Dn to LE 5.0 0 0 1.0 ns 3−9 5.0 2.0 7.0 8.0 ns 3−6 tw LE Pulse Width, HIGH *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 40 pF VCC = 5.0 V www.onsemi.com 7 MC74AC373, MC74ACT373 ORDERING INFORMATION Package Shipping† MC74AC373DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74AC373DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74ACT373DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74ACT373DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74AC373DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74AC373DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel MC74ACT373DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74ACT373DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−20W TSSOP−20 20 20 AC 373 ALYWG G AC373 AWLYYWWG 1 1 20 20 ACT 373 ALYWG G ACT373 AWLYYWWG 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative