MC74ACT640
Octal 3−State Inverting
Transciever
The MC74ACT640 octal bus transceiver is designed for
asynchronous two-way communication between data buses. The
device transmits data from bus A to bus B when T/R = HIGH, or from
bus B to bus A when T/R = LOW. The enable input can be used to
disable the device so the buses are effectively isolated.
• Bidirectional Data Path
• A and B Outputs Sink 24 mA/Source −24 mA
• TTL Compatible Inputs
w These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
VCC
20
OE
19
B0
18
B1
B2
17
16
B3
B4
15
14
B5
B6
PDIP−20
N SUFFIX
CASE 738
20
1
SO−20
DW SUFFIX
CASE 751
20
1
B7
12
13
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11
20
1
TSSOP−20
DT SUFFIX
CASE 948E
EIAJ−20
M SUFFIX
CASE 967
20
1
1
2
3
4
5
6
7
8
9
10
T/R
A0
A1
A2
A3
A4
A5
A6
A7
GND
ORDERING INFORMATION
Package
Shipping
MC74ACT640N
PDIP−20
18 Units/Rail
MC74ACT640DW
SOIC−20
38 Units/Rail
PIN ASSIGNMENT
MC74AC640DWR2
SOIC−20
1000 Tape & Reel
PIN
FUNCTION
MC74AC640DT
TSSOP−20
75 Units/Rail
A0−A7
Side A Inputs or 3-State Outputs
MC74ACT640DTR2 TSSOP−20 2500 Tape & Reel
OE
Output Enable Input
T/R
Transmit/Receive Input
B0−B7
Side B Inputs or 3-State Outputs
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
Device
MC74ACT640M
EIAJ−20
40 Units/Rail
MC74AC640MEL
EIAJ−20
2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 5 of this data sheet.
TRUTH TABLE
OE
T/R
Applied
Inputs
Valid
Direction
I/P→O/P
Output
H
X
X
X
X
L
H
H
A to B
L
L
H
L
A to B
H
L
L
H
B to A
L
L
L
L
B to A
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1
Publication Order Number:
MC74ACT640/D
MC74ACT640
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 v VI v VCC )0.5
V
*0.5 v VO v VCC )0.5
V
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$50
mA
IO
DC Output Sink/Source Current
$50
mA
ICC
DC Supply Current per Output Pin
$50
mA
IGND
DC Ground Current per Output Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead temperature, 1 mm from Case for 10 Seconds
TJ
Junction temperature under Bias
qJA
Thermal resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85_C (Note 6)
$100
mA
(Note 2)
260
_C
)150
_C
PDIP
SOIC
TSSOP
67
96
128
_C/W
PDIP
SOIC
TSSOP
750
500
450
mW
Level 1
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum−rated
conditions is not implied.
2. IO absolute maximum rating must be observed.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
VCC
DC Input Voltage (Referenced to GND)
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Note 8)
Typ
4.5
VCC = 4.5 V
VCC = 5.5 V
0
Max
Unit
5.5
V
VCC
V
−40
25
+85
°C
0
0
10
8.0
10
8.0
ns/V
TJ
Junction Temperature (PDIP)
140
°C
IOH
Output Current − High
−24
mA
IOL
Output Current − Low
24
mA
7. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level.
8. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.
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2
MC74ACT640
DC CHARACTERISTICS
TA = +255C
Symbol
Parameter
TA = −405C to
+855C
VCC (V)
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
V
VOUT = 0.1 V
or
VCC − 0.1 V
VIL
Maximum Low Level Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
V
VOUT = 0.1 V
or
VCC − 0.1 V
VOH
Minimum High Level Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
V
IOUT = −50 μA
3.86
4.86
3.76
4.76
V
V
*VIN = VIL or VIH
IOH
0.1
0.1
0.1
0.1
V
V
IOUT = 50 μA
4.5
5.5
0.36
0.36
0.44
0.44
V
V
*VIN = VIL or VIH
IOH
±0.1
±1.0
μA
VI = VCC, GND
1.5
mA
VI = VCC − 2.1 V
±0.5
±5.0
μA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
75
−75
mA
mA
VOLD = 1.65 V Max
80
μA
VIN = VCC or GND
4.5
5.5
VOL
Maximum Low Level Output Voltage
4.5
5.5
IIN
Maximum Input Leakage Current
5.5
DICCT
Additional Max. ICC/Input
5.5
IOZ
Maximum 3−State Current
5.5
IOLD
IOHD
†Minimum Dynamic Output Current
5.5
5.5
ICC
Maximum Quiescent Supply Current
5.5
0.001
0.001
0.6
8.0
−24 mA
−24 mA
−24 mA
−24 mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 2 and 3.)
TA = +255C
CL = 50 pF
Parameter
Symbol
TA = −405C to +855C
CL = 50 pF
VCC* (V)
Min
Max
Min
Max
Unit
tPLH
Propagation Delay
An to Bn or Bn to An
5.0
1.5
8.0
1.0
8.5
ns
tPHL
Propagation Delay
An to Bn or Bn to An
5.0
1.5
8.0
1.0
9.0
ns
tPZH
Output Enable Time
OE to An or Bn
5.0
1.5
10.0
1.0
11.0
ns
tPZL
Output Enable Time
OE to An or Bn
5.0
1.5
10.0
1.0
11.0
ns
tPHZ
Output Disable Time
T/R or OE to An or Bn
5.0
1.5
10.0
1.0
11.0
ns
tPLZ
Output Disable Time
T/R or OE to An or Bn
5.0
1.5
10.0
1.0
11.0
ns
*Voltage Range 5.0 V is 5.0 V ±0.5 V
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CI/O
Input/Output Capacitance
15
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
45
pF
VCC = 5.0 V
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3
MC74ACT640
SWITCHING WAVEFORMS
3.0 V
T/R
tr
INPUT
A or B
OUTPUT
A or B
3.0 V
90%
50%
10%
tPHL
GND
tf
tPLH
3.0 V
GND
OE
GND
tPZL tPLZ
90%
50%
10%
tTHL
50%
50%
A OR B
tPZH tPHZ
tTLH
50%
A OR B
Figure 2.
HIGH
IMPEDANCE
10%
VOL
90%
VOH
HIGH
IMPEDANCE
Figure 3.
INPUT
450 W
OUTPUT
DEVICE
UNDER
TEST
50 W SCOPE
TEST POINT
CL *
*Includes all probe and jig capacitance
Figure 4. Test Circuit
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4
MC74ACT640
MARKING DIAGRAMS
PDIP−20
SO−20
TSSOP−20
EIAJ−20
ACT
640
ALYW
74ACT640
AWLYWW
ACT640
AWLYYWW
MC74ACT640N
AWLYYWW
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
20 PIN PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
−A−
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
−T−
K
SEATING
PLANE
G
M
N
E
F
D
J
0.25 (0.010)
20 PL
0.25 (0.010)
20 PL
M
T A
M
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5
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
MC74ACT640
PACKAGE DIMENSIONS
SO−20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D−05
ISSUE F
D
A
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
20
q
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
q
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
TSSOP−20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E−02
ISSUE A
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
11
J J1
B
−U−
PIN 1
IDENT
ÍÍÍ
ÍÍÍ
ÍÍÍ
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74ACT640
PACKAGE DIMENSIONS
EIAJ−20
M SUFFIX
20 PIN PLASTIC EIAJ PACKAGE
CASE 967−01
ISSUE O
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.032
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74ACT640/D
