MC74ACT259NG

MC74AC259, MC74ACT259 8-Bit Addressable Latch The MC74AC259/74ACT259 is a high−speed 8−bit addressable latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1−of−8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW Common Clear for resetting all latches, as well as an active LOW Enable. It is functionally identical to the ALS259 8−bit addressable latch. • • • • • • • MR E D Q7 Q6 Q5 Q4 16 15 14 13 12 11 10 9 MARKING DIAGRAM 16 Serial−to−Parallel Conversion Eight Bits of Storage with Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear These are Pb−Free Devices VCC www.onsemi.com SOIC−16 D SUFFIX CASE 751B 16 1 xxx259G AWLYWW 1 xxx A WL Y WW G = AC or ACT = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. 1 2 3 4 5 6 7 8 A0 A1 A2 Q0 Q1 Q2 Q3 GND Figure 1. Pinout: 16−Lead Packages Conductors (Top View) E A0 D A1 A2 MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Figure 2. Logic Symbol MODE SELECT TABLE E MR L H L H H H L L Mode Addressable Latch Memory Active HIGH 8−Channel Demultiplexer Clear H = HIGH Voltage Level L = LOW Voltage Level © Semiconductor Components Industries, LLC, 2015 March, 2015 − Rev. 7 1 Publication Order Number: MC74AC259/D MC74AC259, MC74ACT259 MODE SELECT−FUNCTION TABLE Operating Mode Inputs Outputs MR E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Master Reset L H X X X X L L L L L L L L Demultiplex (Active HIGH Decoder when D = H) L L L • • • L L L L • • • L d d d • • • d L H L • • • H L L H • • • H L L L • • • H Q=d L L • • • L L Q=d L • • • L L L Q=d • • • L L L L • • • L L L L • • • L L L L • • • L L L L • • • L L L L • • • Q=d Store (Do Nothing) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 Addressable Latch H H H • • • H L L L • • • L d d d • • • d L H L • • • H L L H • • • H L L L • • • H Q=d q0 q0 • • • q0 q1 Q=d q1 • • • q1 q2 q2 Q=d • • • q2 q3 q3 q3 • • • q3 q4 q4 q4 • • • q4 q5 q5 q5 • • • q5 q6 q6 q6 • • • q6 q7 q7 q7 • • • Q=d H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW−to−HIGH Enable transition q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. FUNCTIONAL DESCRIPTION In the one−of−eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the MC74AC/ACT259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The Mode Select Function Table summarizes the operations of the MC74AC/ACT259. The MC74AC259/74ACT259 has four modes of operation as shown in the Mode Selection Table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non−addressed latches remaining in their previous states in the memory mode. All latches remain in their previous state and are unaffected by the Data or Address inputs. www.onsemi.com 2 MC74AC259, MC74ACT259 Q7 Q6 Q5 MR Q4 Q3 A2 A1 Q2 A0 Q1 D E Q0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 3 MC74AC259, MC74ACT259 MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to +7.0 V DC Input Voltage *0.5 ≤ VCC +0.5 V VO DC Output Voltage (Note 1) *0.5 ≤ VCC +0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±50 mA IO DC Output Sink/Source Current ±50 mA ICC DC Supply Current per Output Pin ±50 mA IGND DC Ground Current per Output Pin ±50 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction temperature under Bias +150 °C qJA Thermal Resistance (Note 2) 69.1 °C/W PD Power Dissipation in Still Air at 65°C (Note 3) 500 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 4) Machine Model (Note 5) Charged Device Model (Note 6) ILatch−Up Latch−Up Performance Above VCC and Below GND at 85°C (Note 7) VCC DC Supply Voltage VI Level 1 Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in > 2000 > 200 > 1000 V ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. The package thermal impedance is calculated in accordance with JESD51−7. 3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C. 4. Tested to EIA/JESD22−A114−A. 5. Tested to EIA/JESD22−A115−A. 6. Tested to JESD22−C101−A. 7. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Min Typ Max Unit ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − −40 25 85 °C V V ns/V tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. www.onsemi.com 4 MC74AC259, MC74ACT259 DC CHARACTERISTICS 74AC Symbol Parameter VCC (V) 74AC TA = +25°C Typ VIH VIL VOH VOL Conditions 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 5.5 − ±0.1 5.5 − 5.5 5.5 Maximum Low Level Output Voltage Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current ICC Unit Minimum High Level Input Voltage IIN IOHD TA =−40°C to +85°C Guaranteed Limits Maximum Quiescent Supply Current IOUT = −50 μA V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 μA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 μA VI = VCC, GND − 75 mA VOLD = 1.65 V Max − − −75 mA VOHD = 3.85 V Min − 8.0 80 μA VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. www.onsemi.com 5 MC74AC259, MC74ACT259 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) VCC* (V) Parameter Symbol 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to Qn 3.3 5.0 2.0 2.0 9.0 6.5 14.5 10.0 1.5 1.5 17.0 11.5 ns 3−5 tPHL Propagation Delay Dn to Qn 3.3 5.0 2.0 2.0 9.0 6.0 13.5 9.5 1.5 1.5 16.0 11.0 ns 3−5 tPLH Propagation Delay E to Qn 3.3 5.0 2.0 2.0 10.5 7.0 15.0 10.5 1.5 1.5 17.5 12.5 ns 3−6 tPHL Propagation Delay E to Qn 3.3 5.0 2.0 2.0 8.0 7.5 12.5 9.0 1.5 1.5 15.0 11.0 ns 3−6 tPLH Propagation Delay Address to Qn 3.3 5.0 2.0 2.0 12.0 8.0 19.0 13.0 1.5 1.5 22.5 15.5 ns 3−6 tPHL Propagation Delay Address to Qn 3.3 5.0 2.0 2.0 10.0 7.0 16.0 11.0 1.5 1.5 19.0 13.0 ns 3−6 tPHL Propagation Delay MR to Q 3.3 5.0 2.0 2.0 8.0 6.0 12.0 9.0 1.5 1.5 13.5 10.0 ns 3−7 Unit Fig. No. *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to E 3.3 5.0 − − 3.5 2.5 4.5 3.5 ns 3−9 th Hold Time, HIGH or LOW Dn to E 3.3 5.0 − − 2.5 2.0 2.5 2.0 ns 3−9 ts Setup Time Address to E 3.3 5.0 − − 7.0 4.0 9.0 6.0 ns 3−6 th Hold Time Address to E 3.3 5.0 − − 2.0 2.0 2.0 2.0 ns 3−6 tw Minimum Pulse Width MR 3.3 5.0 − − 6.0 5.5 6.5 6.0 ns 3−6 tw Minimum Pulse Width E 3.3 5.0 − − 6.5 5.5 7.0 6.0 ns 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 6 MC74AC259, MC74ACT259 DC CHARACTERISTICS 74ACT Symbol Parameter VCC (V) 74ACT TA = +25°C Typ TA = −40°C to +85°C Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA VOL Maximum Low Level Output Voltage IOUT = −50 μA *VIN = VIL or VIH −24 mA IOH −24 mA V IOUT = 50 μA V IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 μA VI = VCC, GND ΔICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOLD †Minimum Dynamic Output Current 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 μA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to Qn 5.0 2.0 6.5 11.0 1.5 12.5 ns 3−5 tPHL Propagation Delay Dn or Qn 5.0 2.0 7.0 10.5 1.5 12.0 ns 3−5 tPLH Propagation Delay E to Qn 5.0 2.0 10.5 14.0 1.5 16.5 ns 3−6 tPHL Propagation Delay E or Qn 5.0 2.0 9.0 12.0 1.5 14.0 ns 3−6 tPLH Propagation Delay Address to Qn 5.0 2.0 8.0 11.5 1.5 13.5 ns 3−6 tPHL Propagation Delay Address to Qn 5.0 2.0 6.0 10.0 1.5 12.0 ns 3−6 tPHL Propagation Delay MR to Q 5.0 2.0 10.0 1.5 11.0 ns 3−7 *Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 7 MC74AC259, MC74ACT259 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to E 5.0 − 3.0 4.0 ns 3−9 th Hold Time, HIGH or LOW Dn to E 5.0 − 2.5 2.5 ns 3−9 ts Setup Time Address to E 5.0 − 4.5 6.5 ns 3−6 th Hold Time Address to E 5.0 − 2.5 2.5 ns 3−6 tw Minimum Pulse Width MR 5.0 − 7.0 7.5 ns 3−6 tw Minimum Pulse Width E 5.0 − 7.0 7.5 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 50.0 pF VCC = 5.0 V ORDERING INFORMATION Package Shipping† MC74AC259DG SOIC−16 (Pb−Free) 48 Units / Rail MC74AC259DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74ACT259DG SOIC−16 (Pb−Free) 48 Units / Rail MC74ACT259DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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