MC74ACT564
Octal D-Type Flip-Flop
with 3-State Outputs
The MC74ACT564 is a high−speed, low power octal flip−flop with
a buffered common Clock (CP) and a buffered common Output
Enable (OE).
The information presented to the D inputs is stored in the flip−flops
on the LOW−to−HIGH Clock (CP) transition.
The MC74ACT564 device is functionally indentical to the
MC74ACT574, but with inverted outputs.
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SOIC−20W
DW SUFFIX
CASE 751D
Features
1
• Inputs and Outputs on the Opposite Sides of the Package Allowing
•
•
•
•
•
•
Easy Interface with Microprocessors
Useful as Input or Output Port for Microprocessor
Functionally Indentical to the MC74ACT574 but with Inverted
Outputs
3−State Outputs for Bus−Oriented Applications
Outputs Source/Sink 24 mA
TTL Compatible Inputs
These are Pb−Free Devices
VCC
O0
O1
O2
O3
O4
O5
O6
O7
CP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 5 of this data sheet.
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
D0 D1 D2 D3 D4 D5 D6 D7
CP
PIN ASSIGNMENT
PIN
FUNCTION
D0−D7
Data Inputs
CP
Clock Pulse Input
OE
3−State Output Enable Input
O0−O7
3−State Outputs
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 4
OE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
1
Publication Order Number:
MC74ACT564/D
MC74ACT564
D0
D1
D2
D3
D4
D5
D6
D7
CP
C
D
C
C
D
D
C
D
C
D
C
D
C
D
C
Q
Q
Q
Q
Q
Q
Q
Q
O0
O1
O2
O3
O4
O5
O6
O7
D
OE
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
FUNCTION TABLE
Inputs
Internal
Outputs
Function
OE
CP
D
Q
O
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
L
H
Z
Load
H
H
L
Z
Load
L
L
H
H
Data Available
L
H
L
L
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
H
L
X
Z
=
=
=
=
=
NC =
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW−to−HIGH Transition
No Change
FUNCTIONAL DESCRIPTION
meet the setup and hold times requirements on the
LOW−to−HIGH Clock (CP) transition. With the Output
Enable (OE) LOW, the contents of the eight flip−flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance state. Operation of the OE input does
not affect the state of the flip−flops.
The MC74ACT564 consists of eight edge−triggered
flip−flops with individual D−type inputs and 3−state
complementary outputs. The buffered clock and buffered
Output Enable are common to all flip−flops. The eight
flip−flops will store the state of their individual D inputs that
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2
MC74ACT564
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND) (Note 1)
−0.5 to VCC +0.5
V
VOUT
IIK
DC Input Diode Current
±20
mA
IOK
DC Output Diode Current
±50
mA
IOUT
DC Output Sink/Source Current
±50
mA
ICC
DC Supply Current, per Output Pin
±50
mA
IGND
DC Ground Current, per Output Pin
±100
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead temperature, 1 mm from Case for 10 Seconds
260
_C
TJ
Junction Temperature Under Bias
140
_C
qJA
Thermal Resistance (Note 2)
65.8
_C/W
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
Level 1
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Latchup Performance
UL 94 V−0 @ 0.125 in
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Above VCC and Below GND at 85_C (Note 6)
> 2000
> 200
> 1000
V
±100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IOUT absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Input Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Typ
Max
Unit
4.5
5.5
V
0
VCC
V
−40
25
+85
°C
0
0
10
8.0
10
8.0
ns/V
Output Current − High
−24
mA
Output Current − Low
24
mA
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Note 8)
IOH
IOL
VCC = 4.5 V
VCC = 5.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level.
8. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74ACT564
DC CHARACTERISTICS
Symbol
Parameter
TA = +255C
VCC
(V)
Typ
TA =
−405C to +855C
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
V
VOUT = 0.1 V
or
VCC − 0.1 V
VIL
Maximum Low Level Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
V
VOUT = 0.1 V
or
VCC − 0.1 V
VOH
Minimum High Level Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
V
IOUT = −50 mA
3.86
4.86
3.76
4.76
V
V
*VIN = VIL or VIH
IOH
0.1
0.1
0.1
0.1
V
V
IOUT = 50 mA
4.5
5.5
0.36
0.36
0.44
0.44
V
V
*VIN = VIL or VIH
IOL
Maximum Input Leakage Current
5.5
±0.1
±1.0
mA
VI = VCC, GND
DICCT
Additional Max. ICC/Input
5.5
1.5
mA
VI = VCC − 2.1 V
IOZ
Maximum 3−State Current
5.5
±5.0
mA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
IOLD
IOHD
†Minimum Dynamic Output Current
5.5
5.5
75
−75
mA
mA
VOLD = 1.65 V Max
VOHD = 3.85 V Min
ICC
Maximum Quiescent Supply Current
5.5
80
mA
VIN = VCC or GND
4.5
5.5
VOL
IIN
Maximum Low Level Output Voltage
4.5
5.5
0.001
0.001
0.6
±0.5
8.0
−24 mA
−24 mA
24 mA
24 mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 4, 5, and 6.)
Symbol
VCC*
(V)
Parameter
TA = +25°C
CL = 50 pF
Min
Typ
TA = −40°C to +85°C
CL = 50 pF
Max
Min
Unit
Max
fmax
Maximum Clock Frequency
5.0
85
−
−
75
−
MHz
tPLH
Propagation Delay
CP to Qn
5.0
2.0
−
10.5
1.5
11.5
ns
tPHL
Propagation Delay
CP to Qn
5.0
1.5
−
9.5
1.5
10.5
ns
tPZH
Output Enable Time
5.0
1.5
−
9.0
1.5
9.5
ns
tPZL
Output Enable Time
5.0
1.5
−
8.5
1.0
9.5
ns
tPHZ
Output Disable Time
5.0
1.5
−
10.5
1.5
11.5
ns
tPLZ
Output Disable Time
5.0
1.5
−
8.0
1.0
8.5
ns
*Voltage Range 5.0 V is 5.0 V ±0.5 V
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4
MC74ACT564
AC OPERATING REQUIREMENTS
Symbol
TA = +25°C
CL = 50 pF
VCC*
(V)
Parameter
Typ
TA = −40°C to +85°C
CL = 50 pF
Unit
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
−
2.5
3.0
ns
th
Hold Time, HIGH or LOW
Dn to CP
5.0
−
1.0
1.0
ns
tw
CP Pulse Width
HIGH or LOW
5.0
−
3.0
3.5
ns
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
50
pF
VCC = 5.0 V
ORDERING INFORMATION
Device
MC74ACT564DWR2G
Package
Shipping†
SOIC−20
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC−20W
20
ACT564
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
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5
MC74ACT564
SWITCHING WAVEFORMS
tf
tr
3.0 V
CP
3.0 V
50%
OE
GND
tw
50%
ts
1/fmax
tPLH
Q
th
3.0 V
tPHL
CP
50%
GND
50%
Figure 4.
Figure 5.
VALID
3.0 V
DATA
50%
GND
tsu
th
VCC
CP
50%
GND
Figure 6.
450 W
INPUT
OUTPUT
DEVICE
UNDER
TEST
50 W SCOPE
TEST POINT
CL *
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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