MC74HC03ADT

MC74HC03A Quad 2−Input NAND Gate with Open−Drain Outputs High−Performance Silicon−Gate CMOS The MC74HC03A is identical in pinout to the LS03. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC03A NAND gate has, as its outputs, a high−performance MOS N−Channel transistor. This NAND gate can, therefore, with a suitable pullup resistor, be used in wired−AND applications. Having the output characteristic curves given in this data sheet, this device can be used as an LED driver or in any other application that only requires a sinking current. • Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor • Outputs Directly Interface to CMOS, NMOS and TTL • High Noise Immunity Characteristic of CMOS Devices • Operating Voltage Range: 2 to 6V • Low Input Current: 1µA • In Compliance With the JEDEC Standard No. 7A Requirements • Chip Complexity: 28 FETs or 7 Equivalent Gates DESIGN GUIDE Value Unit Internal Gate Count* Criteria 7.0 ea Internal Gate Propagation Delay 1.5 ns 5.0 µW 0.0075 pJ Internal Gate Power Dissipation Speed Power Product http://onsemi.com MARKING DIAGRAMS 14 PDIP−14 N SUFFIX CASE 646 1 14 SOIC−14 D SUFFIX CASE 751A 14 PIN 14 = VCC PIN 7 = GND * Denotes open−drain outputs OUTPUT PROTECTION DIODE 3,6,8,11 Y* HC 03A ALYW TSSOP−14 DT SUFFIX CASE 948G 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week FUNCTION TABLE Inputs VCC HC03A AWLYWW 1 * Equivalent to a two−input NAND gate LOGIC DIAGRAM MC74HC03AN AWLYYWW Output A B Y L L H H L H L H Z Z Z L Z = High Impedance A B 1,4,9,12 2,5,10,13 ORDERING INFORMATION Pinout: 14−Lead Packages (Top View) VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8 1 2 3 4 5 6 7 A1 B1 Y1 A2 B2 Y2 GND  Semiconductor Components Industries, LLC, 2000 March, 2000 − Rev. 8 35 Device Package Shipping MC74HC03AN PDIP−14 2000 / Box MC74HC03AD SOIC−14 55 / Rail MC74HC03ADR2 SOIC−14 2500 / Reel MC74HC03ADT TSSOP−14 96 / Rail MC74HC03ADTR2 TSSOP−14 2500 / Reel Publication Order Number: MC74HC03A/D MC74HC03A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air 750 500 450 mW Tstg Storage Temperature – 65 to + 150
C Iin TL Plastic DIP† SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND  (Vin or Vout)  VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/
C from 65
to 125
C SOIC Package: – 7 mW/
C from 65
to 125
C TSSOP Package: − 6.1 mW/
C from 65
to 125
C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) 0 VCC V – 55 + 125
C 0 0 0 1000 500 400 ns VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOL Maximum Low−Level Output Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin = VIH or VIL Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 6.0 1.0 10 40 µA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ±0.5 ±5.0 ±10 µA Iin NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 36 MC74HC03A AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns) Symbol Parameter Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit tPLZ, tPZL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 120 45 24 20 150 60 30 26 180 75 36 31 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Maximum Input Capacitance 10 10 10 pF Maximum Three−State Output Capacitance (Output in High−Impedance State) 10 10 10 pF Cin Cout NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V, VEE = 0 V 8.0 pF 2 * Used to determine the no−load dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Buffer)* http://onsemi.com 37 MC74HC03A VCC tf tr INPUT A Rpd OUTPUT DEVICE UNDER TEST GND tPZL tPLZ HIGH IMPEDANCE 90% 50% 10% OUTPUT Y 1kΩ VCC 90% 50% 10% 10% TEST POINT CL* VOL tTHL *Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit 25 VCC=5V TYPICAL T=25°C I D, SINK CURRENT (mA) 20 T=25°C 15 T=85°C 10 T=125°C EXPECTED MINIMUM* 5 0 0 1 2 3 4 VO, OUTPUT VOLTAGE (VOLTS) 5 *The expected minimum curves are not guarantees, but are design aids. Figure 3. Open−Drain Output Characteristics VCC + VR − + VF − VCC PULLUP RESISTOR A1 B1 A2 B2 An Bn 1/4 HC03 Y1 1/4 HC03 Y2 1/4 HC03 OUTPUT LED1 1/4 HC03 DESIGN EXAMPLE CONDITIONS: ID10mA USING FIGURE NO TAG TYPICAL CURVE, at ID=10mA, VDS0.4V LED2 LED ENABLE 1/4 HC03 VCC V  VF  VO R  CC ID Yn  5V  1.7V  0.4V 10mA OUTPUT = Y1 • Y2 • . . . • Yn = A1B1 • A2B2 • . . . • AnBn  290 USE R = 270Ω Figure 4. Wired AND Figure 5. LED Driver With Blanking http://onsemi.com 38