MC74HC161A,
MC74HC163A
Presettable Counters
High−Performance Silicon−Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the
LS161 and LS163. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC161A and HC163A are programmable 4−bit binary counters
with asynchronous and synchronous reset, respectively.
Features
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
16
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 192 FETs or 48 Equivalent Gates
These are Pb−Free Devices
1
HC16xAG
AWLYWW
1
16
HC
16xA
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
16
1
1
x
A
WL, L
YY, Y
WW, W
G or G
= 1 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 13
1
Publication Order Number:
MC74HC161A/D
MC74HC161A, MC74HC163A
RESET
1
16
CLOCK
2
15
P0
3
14
P1
4
13
Q1
P2
5
12
Q2
P3
6
11
Q3
ENABLE P
7
10
ENABLE T
GND
8
9
VCC
RIPPLE
CARRY OUT
Q0
FUNCTION TABLE
Inputs
Clock
LOAD
Output
Reset*
Load
Enable P
Enable T
Q
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset
Load Preset Data
Count
No Count
No Count
*HC163A only. HC161A is an Asynchronous Reset Device
H = high level, L = low level, X = don’t care
Figure 1. Pin Assignment
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK
3
14
4
13
5
12
6
11
2
15
Q1
Q2
9
LOAD
RIPPLE
CARRY
OUT
PIN 16 = VCC
PIN 8 = GND
7
ENABLE P
10
ENABLE T
Figure 2. Logic Diagram
DEVICE/MODE TABLE
Device
Count
Mode
Reset Mode
HC161A
Binary
Asynchronous
HC163A
Binary
Synchronous
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2
BCD OR
BINARY
OUTPUT
Q3
1
RESET
COUNT
ENABLES
Q0
MC74HC161A, MC74HC163A
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 to VCC )0.5
V
*0.5 v VO v VCC )0.5
V
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
(Note 1)
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$25
mA
IO
DC Output Sink Current
$25
mA
ICC
DC Supply Current per Supply Pin
$50
mA
IGND
DC Ground Current per Ground Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILATCHUP
_C
_C
SOIC
TSSOP
112
148
_C/W
SOIC
TSSOP
500
450
mW
Level 1
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Latchup Performance
260
)150
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
u2000
u200
V
Above VCC and Below GND at 85_C (Note 4)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Min
Max
Unit
DC Supply Voltage
Parameter
(Referenced to GND)
2.0
6.0
V
DC Input Voltage, Output Voltage
(Referenced to GND)
0
VCC
V
*55
)125
_C
0
0
0
0
1000
600
500
400
ns
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 4)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
5. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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MC74HC161A, MC74HC163A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
–55 to 25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level
Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level
Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Symbol
Parameter
Test Conditions
Vin = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
|Iout| v 3.6 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
Vin = VIH or VIL
|Iout| v 20 mA
Vin = VIH or VIL
|Iout| v 3.6 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
V
Iin
Maximum Input
Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
160
mA
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MC74HC161A, MC74HC163A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
V
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency
(50% Duty Cycle)
(Note 6)
4, 10
2.0
3.0
4.5
6.0
6
15
30
35
5
12
24
28
4
10
20
24
MHz
tPLH
Maximum Propagation Delay,
Clock to Q
4, 10
2.0
3.0
4.5
6.0
120
75
20
16
160
120
23
20
200
150
28
22
ns
4, 10
2.0
3.0
4.5
6.0
145
100
22
18
185
135
25
20
220
150
30
23
ns
Symbol
Parameter
Figure
tPHL
tPHL
Maximum Propagation Delay,
Reset to Q (HC161A Only)
5, 10
2.0
3.0
4.5
6.0
145
100
20
17
185
135
22
19
220
150
25
21
ns
tPLH
Maximum Propagation Delay,
Enable T to Ripple Carry Out
6, 10
2.0
3.0
4.5
6.0
110
60
16
14
150
115
18
15
190
140
20
17
ns
6, 10
2.0
3.0
4.5
6.0
135
100
18
15
175
130
20
16
210
160
22
20
ns
4, 10
2.0
3.0
4.5
6.0
120
75
22
18
160
135
27
22
200
150
30
25
ns
4, 10
2.0
3.0
4.5
6.0
145
100
22
20
185
135
28
24
220
150
35
28
ns
tPHL
tPLH
Maximum Propagation Delay,
Clock to Ripple Carry Out
tPHL
tPHL
Maximum Propagation Delay,
Reset to Ripple Carry Out
(HC161A Only)
5, 10
2.0
3.0
4.5
6.0
155
120
22
18
190
140
26
22
230
155
30
25
ns
tTLH,
tTHL
Maximum Output Transition Time,
Any Output
5, 10
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Maximum Input Capacitance
4, 10
−
10
10
10
pF
Cin
6. Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
Typical @ 25°C, VCC = 5.0 V
CPD
45
Power Dissipation Capacitance (Per Gate) (Note 7)
7. Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
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5
pF
MC74HC161A, MC74HC163A
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
V
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
Unit
tsu
Minimum Setup Time,
Preset Data Inputs to Clock
8
2.0
3.0
4.5
6.0
40
20
15
12
60
30
20
18
80
40
30
20
ns
tsu
Minimum Setup Time,
Load to Clock
8
2.0
3.0
4.5
6.0
60
25
15
12
75
30
20
18
90
40
30
20
ns
tsu
Minimum Setup Time,
Reset to Clock (HC163A Only)
7
2.0
3.0
4.5
6.0
60
25
20
17
75
30
25
23
90
40
35
25
ns
tsu
Minimum Setup Time,
Enable T or Enable P to Clock
9
2.0
3.0
4.5
6.0
80
35
20
17
95
40
25
23
110
50
35
25
ns
th
Minimum Hold Time,
Clock to Load or Preset Data Inputs
8
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time,
Clock to Reset (HC163A Only)
7
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time,
Clock to Enable T or Enable P
9
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time,
Reset Inactive to Clock (HC161A Only)
5
2.0
3.0
4.5
6.0
80
35
15
12
95
40
20
17
110
50
26
23
ns
trec
Minimum Recovery Time,
Load Inactive to Clock
8
2.0
3.0
4.5
6.0
80
35
15
12
95
40
20
17
110
50
26
23
ns
tw
Minimum Pulse Width,
Clock
4
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tw
Minimum Pulse Width,
Reset (HC161A Only)
5
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
tr, tf
Parameter
Figure
Maximum Input Rise and Fall Times
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MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION
CONTROL FUNCTIONS
The HC161A/163A are programmable 4−bit synchronous
counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading, and
count−enable controls.
The HC161A and HC163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.
Resetting
A low level on the Reset pin (Pin 1) resets the internal
flip−flops and sets the outputs (Q0 through Q3) to a low
level. The HC161A resets asynchronously, and the HC163A
resets with the rising edge of the Clock input (synchronous
reset).
INPUTS
Loading
Clock (Pin 2)
With the rising edge of the Clock, a low level on Load
(Pin 9) loads the data from the Preset Data input pins (P0,
P1, P2, P3) into the internal flip−flops and onto the output
pins, Q0 through Q3. The count function is disabled as long
as Load is low.
The internal flip−flops toggle and the output count
advances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading, occur with
the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the
internal flip−flops and appear at the counter outputs.
P0 (Pin 3) is the least−significant bit and P3 (Pin 6) is the
most−significant bit.
Count Enable/Disable
OUTPUTS
The count is either enabled or disabled by the control
inputs according to Table 1. In general, Enable P is a
count−enable control: Enable T is both a count−enable and
a Ripple−Carry Output control.
These devices have two count−enable control pins:
Enable P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Count Enable = Enable P • Enable T • Load
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These are the counter outputs. Q0 (Pin 14) is the
least−significant bit and Q3 (Pin 11) is the most−significant
bit.
Table 1. Count Enable/Disable
Control Inputs
Ripple Carry Out (Pin 15)
Result at Outputs
When the counter is in its maximum state, 1111, this
output goes high, providing an external look−ahead carry
pulse that may be used to enable successive cascaded
counters. Ripple Carry Out remains high only during the
maximum count state. The logic equation for this output is:
Load
Enable P
Enable T
Q0 − Q3
H
H
H
Count
L
H
H
No
Count
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3
X
L
H
No
Count
High when Q0−Q3
are maximum*
OUTPUT STATE DIAGRAMS
X
X
L
No
Count
L
0
1
2
3
5
14
6
13
7
12
11
10
9
High when Q0−Q3
are maximum*
*Q0 through Q3 are maximum when Q3, Q2, Q1, Q0 = 1111.
4
15
Ripple Carry Out
8
Figure 3. Binary Counters
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MC74HC161A, MC74HC163A
SWITCHING WAVEFORMS
tr
tf
90%
50%
10%
CLOCK
tw
VCC
RESET
GND
1/fmax
tPHL
tPLH
90%
50%
10%
50%
ANY
OUTPUT
trec
50%
CLOCK
tTHL
tTLH
Figure 4.
tr
tf
tPLH
RIPPLE
CARRY
OUT
VCC
GND
Figure 5.
VCC
90%
50%
10%
ENABLE T
GND
tPHL
tw
ANY
OUTPUT
VCC
50%
50%
RESET
GND
90%
50%
10%
th
tsu
tPHL
VCC
CLOCK
tTLH
50%
GND
tTHL
Figure 6.
Figure 7. HC163A Only
VALID
INPUTS
P0, P1,
P2, P3
GND
tsu
LOAD
VALID
ENABLE T
OR
ENABLE P
th
VCC
50%
th
VCC
50%
tsu
GND
tsu
CLOCK
VCC
50%
th
50%
CLOCK
GND
VCC
GND
trec
VCC
50%
GND
Figure 8.
Figure 9.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL *
*Includes all probe and jig capacitance
Figure 10.
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3
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9
Figure 11. 4−Bit Binary Counter with Asynchronous Reset (MC74HC161A)
CLOCK
LOAD
RESET
ENABLE T
ENABLE P
P3
P2
2
9
1
10
7
6
5
P1 4
P0
C
C
LOAD
LOAD
R
VCC= PIN 16
GND = PIN 8
Q3
Q2
Q1
Q0
15 RIPPLE
CARRY
OUT
11
12
13
14
The flip−flops shown in the circuit diagrams are Toggle−Enable flip−flops. A Toggle−
Enable flip−flop is a combination of a D flip−flop and a T flip−flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip−flop. The logic level at the Pn input is then clocked to the Q output of the flip−flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip−flop low.
T3
R
Q3
C
C
LOAD
LOAD
P3
T2
R
Q2
C
C
LOAD
LOAD Q2
P2
T1
Q1
R
C
C
LOAD
LOAD Q1
P1
T0
R
Q0
C
C
LOAD
LOAD Q0
P0
MC74HC161A, MC74HC163A
MC74HC161A, MC74HC163A
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.
RESET (HC161A)
(ASYNCHRONOUS)
RESET (HC163A)
(SYNCHRONOUS)
LOAD
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK (HC161A)
CLOCK (HC163A)
COUNT
ENABLES
ENABLE P
ENABLE T
Q0
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
12
13 14
15
0
COUNT
RESET
LOAD
Figure 12. Timing Diagram
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1
2
INHIBIT
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11
Figure 13. 4−Bit Binary Counter with Synchronous Reset (MC74HC163A)
CLOCK
LOAD
RESET
ENABLE T
ENABLE P
P3
P2
P1
P0
2
9
1
10
7
6
5
4
3
C
C
LOAD
LOAD
R
VCC= PIN 16
GND = PIN 8
Q3
Q2
Q1
Q0
15 RIPPLE
CARRY
OUT
11
12
13
14
The flip−flops shown in the circuit diagrams are Toggle−Enable flip−flops. A Toggle−
Enable flip−flop is a combination of a D flip−flop and a T flip−flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip−flop. The logic level at the Pn input is then clocked to the Q output of the flip−flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip−flop low.
T3
R
Q3
C
C
LOAD
LOAD
P3
T2
R
Q2
C
C
LOAD
LOAD Q2
P2
T1
Q1
R
C
C
LOAD
LOAD Q1
P1
T0
R
Q0
C
C
LOAD
LOAD Q0
P0
MC74HC161A, MC74HC163A
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD
INPUTS
INPUTS
H = COUNT
L = DISABLE
H = COUNT
L = DISABLE
INPUTS
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
ENABLE P
ENABLE P
ENABLE P
RIPPLE
ENABLE T CARRY
OUT
RIPPLE
ENABLE T CARRY
OUT
RIPPLE
ENABLE T CARRY
OUT
CLOCK
CLOCK
CLOCK
R
R
R
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
TO MORE
SIGNIFICANT
STAGES
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
OUTPUTS
CLOCK
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will
depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 14. N−Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
CLOCK
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
ENABLE P
ENABLE P
ENABLE P
RIPPLE
ENABLE T CARRY
OUT
RIPPLE
ENABLE T CARRY
OUT
RIPPLE
ENABLE T CARRY
OUT
CLOCK
CLOCK
CLOCK
R
R
R
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
Figure 15. Nibble Ripple Counter
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12
OUTPUTS
TO MORE
SIGNIFICANT
STAGES
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A
HC163A
OTHER Q0
INPUTS
Q1
OTHER Q0
INPUTS
Q1
OPTIONAL BUFFER
FOR NOISE REJECTION
Q2
OPTIONAL BUFFER
FOR NOISE REJECTION
Q2
OUTPUT
Q3
OUTPUT
Q3
RESET
RESET
Figure 16. Modulo−5 Counter
Figure 17. Modulo−11 Counter
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch−free due to
the synchronous Reset.
ORDERING INFORMATION
Package
Shipping†
MC74HC161ADTG
TSSOP−16
(Pb−Free)
96 Units / Tube
MC74HC163ADTG
TSSOP−16
(Pb−Free)
96 Units / Tube
MC74HC161ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC161ADR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
TSSOP−16*
2500 Units / Tape & Reel
MC74HC163ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC163ADR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
TSSOP−16*
2500 Units / Tape & Reel
Device
MC74HC161ADTR2G
MC74HC163ADTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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