DATA SHEET
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Hex D Flip-Flop with
Common Clock and Reset
High−Performance Silicon−Gate CMOS
MC74HC174A
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active−low.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 162 FETs or 40.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
16
16
1
1
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
MARKING DIAGRAMS
16
16
HC
174A
ALYWG
G
HC174AG
AWLYWW
1
1
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
RESET
1
16
VCC
Q0
2
15
Q5
D0
3
14
D5
D1
4
13
D4
Q1
5
12
Q4
D2
6
11
D3
Q2
7
10
Q3
GND
8
9
CLOCK
ORDERING INFORMATION
Package
Shipping†
MC74HC174ADR2G
SOIC−16
(Pb−Free)
2500 /
Tape & Reel
MC74HC174ADTR2G
TSSOP−16
(Pb−Free)
2500 /
Tape & Reel
NLV74HC174ADR2G*
SOIC−16
(Pb−Free)
2500 /
Tape & Reel
NLV74HC174ADTR2G*
TSSOP−16
(Pb−Free)
2500 /
Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2012
July, 2022 − Rev. 13
1
Publication Order Number:
MC74HC174A/D
MC74HC174A
3
2
4
5
D2
D3
6
7
11
10
D4
13
12
14
15
D0
D1
DATA
INPUTS
D5
CLOCK
9
RESET
1
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
Q4
Q5
PIN 16 = VCC
PIN 8 = GND
Figure 1. Logic Diagram
FUNCTION TABLE
DESIGN/VALUE TABLE
Inputs
Output
Design Criteria
Value
Units
Reset
Clock
D
Q
Internal Gate Count*
40.5
ea.
L
X
X
L
Internal Gate Propagation Delay
1.5
ns
H
H
H
Internal Gate Power Dissipation
5.0
mW
H
L
L
Speed Power Product
0.0075
pJ
X
No Change
X
No Change
H
H
L
*Equivalent to a two−input NAND gate.
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2
MC74HC174A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
(Referenced to GND)
−0.5 to +7.0
V
VIN
DC Input Voltage
(Referenced to GND)
−0.5 to VCC + 0.5
V
(Referenced to GND) (Note 1)
VOUT
−0.5 to VCC + 0.5
V
DC Input Current, per Pin
20
mA
IOUT
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
IIN
TSTG
DC Output Voltage
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILATCHUP
mA
_C
SOIC, TSSOP
260
_C
+150
_C
SOIC
TSSOP
112
148
_C/W
SOIC
TSSOP
500
450
mW
Level 1
Oxygen Index: 30−35%
ESD Withstand Voltage
Latchup Performance
50
−65 to +150
UL 94 V−0 @ 0.125 in.
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above VCC and Below GND at 85_C (Note 5)
u2000
u100
u500
V
300
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Parameter
VCC
DC Supply Voltage
VIN,
VOUT
DC Input Voltage, Output Voltage
TA
Operating Temperature, All Package Types
tr, tf
CLOCK Input Rise and Fall Time (Figure 2)
Min
(Referenced to GND)
(Referenced to GND) (Note 6)
VCC = 2.0 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
V
0
VCC
V
−55
+125
_C
0
0
0
0
1000
700
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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3
MC74HC174A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
V
−55_C to 25_C
v85_C
v125_C
Unit
VIH
Minimum High−Level Input
Voltage
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| v 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| v 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
VIN = VIH or VIL
|IOUT| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN = VIH or VIL
|IOUT| v 4.0 mA
|IOUT| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VIN = VIH or VIL
|IOUT| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN = VIH or VIL
|IOUT| v 4.0 mA
|IOUT| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOL
Parameter
Test Conditions
Maximum Low−Level Output
Voltage
V
IIN
Maximum Input Leakage Current
VIN = VCC or GND
6.0
0.1
1.0
1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
VIN = VCC or GND
IOUT = 0 mA
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
Guaranteed Limit
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
V
−55_C to 25_C
v85_C
v125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 5)
Parameter
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 5)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tPLH
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 5)
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Typical @ 25_C, VCC = 5.0 V
CPD
Power Dissipation Capacitance, per Enabled Output
(Note 7)
7. Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
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4
62
pF
MC74HC174A
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
−55_C to 25_C
v85_C
v125_C
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Symbol
Parameter
Figure
V
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
4
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Data
4
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec
Minimum Recovery Time,
Reset Inactive to Clock
3
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
2
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tw
Minimum Pulse Width, Reset
3
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Rise and Fall Times
2
2.0
4.5
6.0
tr, tf
1000
500
400
1000
500
400
1000
500
400
ns
SWITCHING WAVEFORMS AND TEST CIRCUIT
tr
CLOCK
tf
VCC
90%
50%
10%
tw
GND
GND
tPHL
tPLH
tPHL
Q
90%
50%
10%
trec
tTLH
50%
CLOCK
tTHL
Figure 2. Switching Waveform
Figure 3. Switching Waveform
TEST POINT
VALID
VCC
DATA
VCC
50%
1/fmax
Q
tw
RESET
OUTPUT
50%
tsu
th
DEVICE
UNDER
TEST
GND
CL *
VCC
CLOCK
50%
GND
*Includes all probe and jig capacitance
Figure 4. Switching Waveform
Figure 5. Test Circuit
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5
VCC
GND
MC74HC174A
CLOCK
9
D0
3
RESET
1
D1
4
D2
6
D3
11
C
D
Q
D4
D5
Q
Q
Q
D
Q
D
Q
R
Figure 6. Expanded Logic Diagram
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6
Q2
10
Q3
12
Q4
R
C
14
7
R
C
13
Q1
R
C
D
5
R
C
D
Q0
R
C
D
2
15
Q5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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